mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
[MIPS] Fixup migration to GENERIC_TIME
Since we already moved to GENERIC_TIME, we should implement alternatives
of old do_gettimeoffset routines to get sub-jiffies resolution from
gettimeofday(). This patch includes:
* MIPS clocksource support (based on works by Manish Lachwani).
* remove unused gettimeoffset routines and related codes.
* remove unised 64bit do_div64_32().
* simplify mips_hpt_init. (no argument needed, __init tag)
* simplify c0_hpt_timer_init. (no need to write to c0_count)
* remove some hpt_init routines.
* mips_hpt_mask variable to specify bitmask of hpt value.
* convert jmr3927_do_gettimeoffset to jmr3927_hpt_read.
* convert ip27_do_gettimeoffset to ip27_hpt_read.
* convert bcm1480_do_gettimeoffset to bcm1480_hpt_read.
* simplify sb1250 hpt functions. (no need to subtract and shift)
Signed-off-by: Atsushi Nemoto <[email protected]>
Signed-off-by: Ralf Baechle <[email protected]>
This commit is contained in:
Atsushi Nemoto
Ralf Baechle
parent
70e46f48cb
commit
16b7b2ac01
13 changed files with 103 additions and 522 deletions
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@ -53,9 +53,6 @@ static unsigned long r4k_cur; /* What counter should be at next timer irq */
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int no_au1xxx_32khz;
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extern int allow_au1k_wait; /* default off for CP0 Counter */
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/* Cycle counter value at the previous timer interrupt.. */
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static unsigned int timerhi = 0, timerlo = 0;
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#ifdef CONFIG_PM
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#if HZ < 100 || HZ > 1000
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#error "unsupported HZ value! Must be in [100,1000]"
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@ -90,10 +87,6 @@ void mips_timer_interrupt(void)
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goto null;
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do {
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count = read_c0_count();
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timerhi += (count < timerlo); /* Wrap around */
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timerlo = count;
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kstat_this_cpu.irqs[irq]++;
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do_timer(1);
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#ifndef CONFIG_SMP
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@ -297,88 +290,6 @@ unsigned long cal_r4koff(void)
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return (cpu_speed / HZ);
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}
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/* This is for machines which generate the exact clock. */
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#define USECS_PER_JIFFY (1000000/HZ)
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#define USECS_PER_JIFFY_FRAC (0x100000000LL*1000000/HZ&0xffffffff)
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static unsigned long
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div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
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{
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unsigned long r0;
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do_div64_32(r0, v1, v2, v3);
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return r0;
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}
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static unsigned long do_fast_cp0_gettimeoffset(void)
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{
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u32 count;
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unsigned long res, tmp;
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unsigned long r0;
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/* Last jiffy when do_fast_gettimeoffset() was called. */
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static unsigned long last_jiffies=0;
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unsigned long quotient;
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/*
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* Cached "1/(clocks per usec)*2^32" value.
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* It has to be recalculated once each jiffy.
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*/
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static unsigned long cached_quotient=0;
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tmp = jiffies;
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quotient = cached_quotient;
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if (tmp && last_jiffies != tmp) {
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last_jiffies = tmp;
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if (last_jiffies != 0) {
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r0 = div64_32(timerhi, timerlo, tmp);
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quotient = div64_32(USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0);
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cached_quotient = quotient;
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}
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}
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/* Get last timer tick in absolute kernel time */
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count = read_c0_count();
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/* .. relative to previous jiffy (32 bits is enough) */
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count -= timerlo;
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__asm__("multu\t%1,%2\n\t"
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"mfhi\t%0"
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: "=r" (res)
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: "r" (count), "r" (quotient)
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: "hi", "lo", GCC_REG_ACCUM);
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/*
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* Due to possible jiffies inconsistencies, we need to check
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* the result so that we'll get a timer that is monotonic.
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*/
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if (res >= USECS_PER_JIFFY)
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res = USECS_PER_JIFFY-1;
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return res;
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}
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#ifdef CONFIG_PM
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static unsigned long do_fast_pm_gettimeoffset(void)
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{
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unsigned long pc0;
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unsigned long offset;
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pc0 = au_readl(SYS_TOYREAD);
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au_sync();
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offset = pc0 - last_pc0;
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if (offset > 2*MATCH20_INC) {
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printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
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(unsigned)offset, (unsigned)last_pc0,
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(unsigned)last_match20, (unsigned)pc0);
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}
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offset = (unsigned long)((offset * 305) / 10);
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return offset;
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}
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#endif
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void __init plat_timer_setup(struct irqaction *irq)
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{
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unsigned int est_freq;
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@ -416,7 +327,6 @@ void __init plat_timer_setup(struct irqaction *irq)
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unsigned int c0_status;
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printk("WARNING: no 32KHz clock found.\n");
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do_gettimeoffset = do_fast_cp0_gettimeoffset;
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/* Ensure we get CPO_COUNTER interrupts.
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*/
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@ -441,19 +351,11 @@ void __init plat_timer_setup(struct irqaction *irq)
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while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
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startup_match20_interrupt(counter0_irq);
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do_gettimeoffset = do_fast_pm_gettimeoffset;
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/* We can use the real 'wait' instruction.
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*/
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allow_au1k_wait = 1;
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}
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#else
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/* We have to do this here instead of in timer_init because
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* the generic code in arch/mips/kernel/time.c will write
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* over our function pointer.
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*/
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do_gettimeoffset = do_fast_cp0_gettimeoffset;
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#endif
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}
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@ -160,11 +160,6 @@ static unsigned int dec_ioasic_hpt_read(void)
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return ioasic_read(IO_REG_FCTR);
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}
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static void dec_ioasic_hpt_init(unsigned int count)
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{
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ioasic_write(IO_REG_FCTR, ioasic_read(IO_REG_FCTR) - count);
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}
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void __init dec_time_init(void)
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{
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@ -174,11 +169,9 @@ void __init dec_time_init(void)
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mips_timer_state = dec_timer_state;
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mips_timer_ack = dec_timer_ack;
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if (!cpu_has_counter && IOASIC) {
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if (!cpu_has_counter && IOASIC)
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/* For pre-R4k systems we use the I/O ASIC's counter. */
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mips_hpt_read = dec_ioasic_hpt_read;
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mips_hpt_init = dec_ioasic_hpt_init;
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}
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/* Set up the rate of periodic DS1287 interrupts. */
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CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);
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@ -170,12 +170,20 @@ static void jmr3927_machine_power_off(void)
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while (1);
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}
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static unsigned int jmr3927_hpt_read(void)
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{
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/* We assume this function is called xtime_lock held. */
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return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
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}
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#define USE_RTC_DS1742
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#ifdef USE_RTC_DS1742
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extern void rtc_ds1742_init(unsigned long base);
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#endif
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static void __init jmr3927_time_init(void)
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{
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mips_hpt_read = jmr3927_hpt_read;
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mips_hpt_frequency = JMR3927_TIMER_CLK;
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#ifdef USE_RTC_DS1742
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if (jmr3927_have_nvram()) {
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rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
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@ -183,12 +191,8 @@ static void __init jmr3927_time_init(void)
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#endif
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}
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unsigned long jmr3927_do_gettimeoffset(void);
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void __init plat_timer_setup(struct irqaction *irq)
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{
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do_gettimeoffset = jmr3927_do_gettimeoffset;
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jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
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jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
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jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
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@ -200,34 +204,6 @@ void __init plat_timer_setup(struct irqaction *irq)
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#define USECS_PER_JIFFY (1000000/HZ)
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unsigned long jmr3927_do_gettimeoffset(void)
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{
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unsigned long count;
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unsigned long res = 0;
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/* MUST read TRR before TISR. */
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count = jmr3927_tmrptr->trr;
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if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
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/* timer interrupt is pending. use Max value. */
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res = USECS_PER_JIFFY - 1;
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} else {
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/* convert to usec */
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/* res = count / (JMR3927_TIMER_CLK / 1000000); */
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res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
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/*
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* Due to possible jiffies inconsistencies, we need to check
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* the result so that we'll get a timer that is monotonic.
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*/
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if (res >= USECS_PER_JIFFY)
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res = USECS_PER_JIFFY-1;
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}
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return res;
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}
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//#undef DO_WRITE_THROUGH
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#define DO_WRITE_THROUGH
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#define DO_ENABLE_CACHE
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@ -11,6 +11,7 @@
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/clocksource.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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@ -67,15 +68,9 @@ int (*rtc_mips_set_time)(unsigned long) = null_rtc_set_time;
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int (*rtc_mips_set_mmss)(unsigned long);
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/* usecs per counter cycle, shifted to left by 32 bits */
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static unsigned int sll32_usecs_per_cycle;
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/* how many counter cycles in a jiffy */
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static unsigned long cycles_per_jiffy __read_mostly;
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/* Cycle counter value at the previous timer interrupt.. */
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static unsigned int timerhi, timerlo;
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/* expirelo is the count value for next CPU timer interrupt */
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static unsigned int expirelo;
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@ -93,7 +88,7 @@ static unsigned int null_hpt_read(void)
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return 0;
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}
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static void null_hpt_init(unsigned int count)
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static void __init null_hpt_init(void)
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{
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/* nothing */
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}
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@ -128,186 +123,18 @@ static unsigned int c0_hpt_read(void)
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return read_c0_count();
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}
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/* For use solely as a high precision timer. */
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static void c0_hpt_init(unsigned int count)
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{
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write_c0_count(read_c0_count() - count);
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}
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/* For use both as a high precision timer and an interrupt source. */
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static void c0_hpt_timer_init(unsigned int count)
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static void __init c0_hpt_timer_init(void)
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{
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count = read_c0_count() - count;
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expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
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write_c0_count(expirelo - cycles_per_jiffy);
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expirelo = read_c0_count() + cycles_per_jiffy;
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write_c0_compare(expirelo);
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write_c0_count(count);
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}
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int (*mips_timer_state)(void);
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void (*mips_timer_ack)(void);
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unsigned int (*mips_hpt_read)(void);
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void (*mips_hpt_init)(unsigned int);
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/*
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* Gettimeoffset routines. These routines returns the time duration
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* since last timer interrupt in usecs.
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*
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* If the exact CPU counter frequency is known, use fixed_rate_gettimeoffset.
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* Otherwise use calibrate_gettimeoffset()
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*
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* If the CPU does not have the counter register, you can either supply
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* your own gettimeoffset() routine, or use null_gettimeoffset(), which
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* gives the same resolution as HZ.
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*/
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static unsigned long null_gettimeoffset(void)
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{
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return 0;
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}
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/* The function pointer to one of the gettimeoffset funcs. */
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unsigned long (*do_gettimeoffset)(void) = null_gettimeoffset;
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static unsigned long fixed_rate_gettimeoffset(void)
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{
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u32 count;
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unsigned long res;
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/* Get last timer tick in absolute kernel time */
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count = mips_hpt_read();
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/* .. relative to previous jiffy (32 bits is enough) */
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count -= timerlo;
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__asm__("multu %1,%2"
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: "=h" (res)
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: "r" (count), "r" (sll32_usecs_per_cycle)
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: "lo", GCC_REG_ACCUM);
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/*
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* Due to possible jiffies inconsistencies, we need to check
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* the result so that we'll get a timer that is monotonic.
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*/
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if (res >= USECS_PER_JIFFY)
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res = USECS_PER_JIFFY - 1;
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return res;
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}
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/*
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* Cached "1/(clocks per usec) * 2^32" value.
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* It has to be recalculated once each jiffy.
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*/
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static unsigned long cached_quotient;
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/* Last jiffy when calibrate_divXX_gettimeoffset() was called. */
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static unsigned long last_jiffies;
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/*
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* This is moved from dec/time.c:do_ioasic_gettimeoffset() by Maciej.
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*/
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static unsigned long calibrate_div32_gettimeoffset(void)
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{
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u32 count;
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unsigned long res, tmp;
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unsigned long quotient;
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tmp = jiffies;
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quotient = cached_quotient;
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if (last_jiffies != tmp) {
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last_jiffies = tmp;
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if (last_jiffies != 0) {
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unsigned long r0;
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do_div64_32(r0, timerhi, timerlo, tmp);
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do_div64_32(quotient, USECS_PER_JIFFY,
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USECS_PER_JIFFY_FRAC, r0);
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cached_quotient = quotient;
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}
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}
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/* Get last timer tick in absolute kernel time */
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count = mips_hpt_read();
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/* .. relative to previous jiffy (32 bits is enough) */
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count -= timerlo;
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__asm__("multu %1,%2"
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: "=h" (res)
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: "r" (count), "r" (quotient)
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: "lo", GCC_REG_ACCUM);
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/*
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* Due to possible jiffies inconsistencies, we need to check
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* the result so that we'll get a timer that is monotonic.
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*/
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if (res >= USECS_PER_JIFFY)
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res = USECS_PER_JIFFY - 1;
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return res;
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}
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static unsigned long calibrate_div64_gettimeoffset(void)
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{
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u32 count;
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unsigned long res, tmp;
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unsigned long quotient;
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tmp = jiffies;
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quotient = cached_quotient;
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if (last_jiffies != tmp) {
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last_jiffies = tmp;
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if (last_jiffies) {
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unsigned long r0;
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__asm__(".set push\n\t"
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".set mips3\n\t"
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"lwu %0,%3\n\t"
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"dsll32 %1,%2,0\n\t"
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"or %1,%1,%0\n\t"
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"ddivu $0,%1,%4\n\t"
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"mflo %1\n\t"
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"dsll32 %0,%5,0\n\t"
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"or %0,%0,%6\n\t"
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"ddivu $0,%0,%1\n\t"
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"mflo %0\n\t"
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".set pop"
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: "=&r" (quotient), "=&r" (r0)
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: "r" (timerhi), "m" (timerlo),
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"r" (tmp), "r" (USECS_PER_JIFFY),
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"r" (USECS_PER_JIFFY_FRAC)
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: "hi", "lo", GCC_REG_ACCUM);
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cached_quotient = quotient;
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}
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}
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/* Get last timer tick in absolute kernel time */
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count = mips_hpt_read();
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/* .. relative to previous jiffy (32 bits is enough) */
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count -= timerlo;
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__asm__("multu %1,%2"
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: "=h" (res)
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: "r" (count), "r" (quotient)
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: "lo", GCC_REG_ACCUM);
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/*
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* Due to possible jiffies inconsistencies, we need to check
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* the result so that we'll get a timer that is monotonic.
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*/
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if (res >= USECS_PER_JIFFY)
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res = USECS_PER_JIFFY - 1;
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return res;
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||||
}
|
||||
|
||||
void (*mips_hpt_init)(void) __initdata = null_hpt_init;
|
||||
unsigned int mips_hpt_mask = 0xffffffff;
|
||||
|
||||
/* last time when xtime and rtc are sync'ed up */
|
||||
static long last_rtc_update;
|
||||
|
|
@ -334,18 +161,10 @@ void local_timer_interrupt(int irq, void *dev_id)
|
|||
*/
|
||||
irqreturn_t timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
unsigned long j;
|
||||
unsigned int count;
|
||||
|
||||
write_seqlock(&xtime_lock);
|
||||
|
||||
count = mips_hpt_read();
|
||||
mips_timer_ack();
|
||||
|
||||
/* Update timerhi/timerlo for intra-jiffy calibration. */
|
||||
timerhi += count < timerlo; /* Wrap around */
|
||||
timerlo = count;
|
||||
|
||||
/*
|
||||
* call the generic timer interrupt handling
|
||||
*/
|
||||
|
|
@ -368,47 +187,6 @@ irqreturn_t timer_interrupt(int irq, void *dev_id)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* If jiffies has overflown in this timer_interrupt, we must
|
||||
* update the timer[hi]/[lo] to make fast gettimeoffset funcs
|
||||
* quotient calc still valid. -arca
|
||||
*
|
||||
* The first timer interrupt comes late as interrupts are
|
||||
* enabled long after timers are initialized. Therefore the
|
||||
* high precision timer is fast, leading to wrong gettimeoffset()
|
||||
* calculations. We deal with it by setting it based on the
|
||||
* number of its ticks between the second and the third interrupt.
|
||||
* That is still somewhat imprecise, but it's a good estimate.
|
||||
* --macro
|
||||
*/
|
||||
j = jiffies;
|
||||
if (j < 4) {
|
||||
static unsigned int prev_count;
|
||||
static int hpt_initialized;
|
||||
|
||||
switch (j) {
|
||||
case 0:
|
||||
timerhi = timerlo = 0;
|
||||
mips_hpt_init(count);
|
||||
break;
|
||||
case 2:
|
||||
prev_count = count;
|
||||
break;
|
||||
case 3:
|
||||
if (!hpt_initialized) {
|
||||
unsigned int c3 = 3 * (count - prev_count);
|
||||
|
||||
timerhi = 0;
|
||||
timerlo = c3;
|
||||
mips_hpt_init(count - c3);
|
||||
hpt_initialized = 1;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
write_sequnlock(&xtime_lock);
|
||||
|
||||
/*
|
||||
|
|
@ -476,12 +254,11 @@ asmlinkage void ll_local_timer_interrupt(int irq)
|
|||
* 1) board_time_init() -
|
||||
* a) (optional) set up RTC routines,
|
||||
* b) (optional) calibrate and set the mips_hpt_frequency
|
||||
* (only needed if you intended to use fixed_rate_gettimeoffset
|
||||
* or use cpu counter as timer interrupt source)
|
||||
* (only needed if you intended to use cpu counter as timer interrupt
|
||||
* source)
|
||||
* 2) setup xtime based on rtc_mips_get_time().
|
||||
* 3) choose a appropriate gettimeoffset routine.
|
||||
* 4) calculate a couple of cached variables for later usage
|
||||
* 5) plat_timer_setup() -
|
||||
* 3) calculate a couple of cached variables for later usage
|
||||
* 4) plat_timer_setup() -
|
||||
* a) (optional) over-write any choices made above by time_init().
|
||||
* b) machine specific code should setup the timer irqaction.
|
||||
* c) enable the timer interrupt
|
||||
|
|
@ -533,13 +310,48 @@ static unsigned int __init calibrate_hpt(void)
|
|||
} while (--i);
|
||||
hpt_end = mips_hpt_read();
|
||||
|
||||
hpt_count = hpt_end - hpt_start;
|
||||
hpt_count = (hpt_end - hpt_start) & mips_hpt_mask;
|
||||
hz = HZ;
|
||||
frequency = (u64)hpt_count * (u64)hz;
|
||||
|
||||
return frequency >> log_2_loops;
|
||||
}
|
||||
|
||||
static cycle_t read_mips_hpt(void)
|
||||
{
|
||||
return (cycle_t)mips_hpt_read();
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_mips = {
|
||||
.name = "MIPS",
|
||||
.read = read_mips_hpt,
|
||||
.is_continuous = 1,
|
||||
};
|
||||
|
||||
static void __init init_mips_clocksource(void)
|
||||
{
|
||||
u64 temp;
|
||||
u32 shift;
|
||||
|
||||
if (!mips_hpt_frequency || mips_hpt_read == null_hpt_read)
|
||||
return;
|
||||
|
||||
/* Calclate a somewhat reasonable rating value */
|
||||
clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
|
||||
/* Find a shift value */
|
||||
for (shift = 32; shift > 0; shift--) {
|
||||
temp = (u64) NSEC_PER_SEC << shift;
|
||||
do_div(temp, mips_hpt_frequency);
|
||||
if ((temp >> 32) == 0)
|
||||
break;
|
||||
}
|
||||
clocksource_mips.shift = shift;
|
||||
clocksource_mips.mult = (u32)temp;
|
||||
clocksource_mips.mask = mips_hpt_mask;
|
||||
|
||||
clocksource_register(&clocksource_mips);
|
||||
}
|
||||
|
||||
void __init time_init(void)
|
||||
{
|
||||
if (board_time_init)
|
||||
|
|
@ -555,41 +367,21 @@ void __init time_init(void)
|
|||
-xtime.tv_sec, -xtime.tv_nsec);
|
||||
|
||||
/* Choose appropriate high precision timer routines. */
|
||||
if (!cpu_has_counter && !mips_hpt_read) {
|
||||
if (!cpu_has_counter && !mips_hpt_read)
|
||||
/* No high precision timer -- sorry. */
|
||||
mips_hpt_read = null_hpt_read;
|
||||
mips_hpt_init = null_hpt_init;
|
||||
} else if (!mips_hpt_frequency && !mips_timer_state) {
|
||||
else if (!mips_hpt_frequency && !mips_timer_state) {
|
||||
/* A high precision timer of unknown frequency. */
|
||||
if (!mips_hpt_read) {
|
||||
if (!mips_hpt_read)
|
||||
/* No external high precision timer -- use R4k. */
|
||||
mips_hpt_read = c0_hpt_read;
|
||||
mips_hpt_init = c0_hpt_init;
|
||||
}
|
||||
|
||||
if (cpu_has_mips32r1 || cpu_has_mips32r2 ||
|
||||
(current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
|
||||
(current_cpu_data.isa_level == MIPS_CPU_ISA_II))
|
||||
/*
|
||||
* We need to calibrate the counter but we don't have
|
||||
* 64-bit division.
|
||||
*/
|
||||
do_gettimeoffset = calibrate_div32_gettimeoffset;
|
||||
else
|
||||
/*
|
||||
* We need to calibrate the counter but we *do* have
|
||||
* 64-bit division.
|
||||
*/
|
||||
do_gettimeoffset = calibrate_div64_gettimeoffset;
|
||||
} else {
|
||||
/* We know counter frequency. Or we can get it. */
|
||||
if (!mips_hpt_read) {
|
||||
/* No external high precision timer -- use R4k. */
|
||||
mips_hpt_read = c0_hpt_read;
|
||||
|
||||
if (mips_timer_state)
|
||||
mips_hpt_init = c0_hpt_init;
|
||||
else {
|
||||
if (!mips_timer_state) {
|
||||
/* No external timer interrupt -- use R4k. */
|
||||
mips_hpt_init = c0_hpt_timer_init;
|
||||
mips_timer_ack = c0_timer_ack;
|
||||
|
|
@ -598,16 +390,9 @@ void __init time_init(void)
|
|||
if (!mips_hpt_frequency)
|
||||
mips_hpt_frequency = calibrate_hpt();
|
||||
|
||||
do_gettimeoffset = fixed_rate_gettimeoffset;
|
||||
|
||||
/* Calculate cache parameters. */
|
||||
cycles_per_jiffy = (mips_hpt_frequency + HZ / 2) / HZ;
|
||||
|
||||
/* sll32_usecs_per_cycle = 10^6 * 2^32 / mips_counter_freq */
|
||||
do_div64_32(sll32_usecs_per_cycle,
|
||||
1000000, mips_hpt_frequency / 2,
|
||||
mips_hpt_frequency);
|
||||
|
||||
/* Report the high precision timer rate for a reference. */
|
||||
printk("Using %u.%03u MHz high precision timer.\n",
|
||||
((mips_hpt_frequency + 500) / 1000) / 1000,
|
||||
|
|
@ -619,7 +404,7 @@ void __init time_init(void)
|
|||
mips_timer_ack = null_timer_ack;
|
||||
|
||||
/* This sets up the high precision timer for the first interrupt. */
|
||||
mips_hpt_init(mips_hpt_read());
|
||||
mips_hpt_init();
|
||||
|
||||
/*
|
||||
* Call board specific timer interrupt setup.
|
||||
|
|
@ -633,6 +418,8 @@ void __init time_init(void)
|
|||
* is not invoked accidentally.
|
||||
*/
|
||||
plat_timer_setup(&timer_irqaction);
|
||||
|
||||
init_mips_clocksource();
|
||||
}
|
||||
|
||||
#define FEBRUARY 2
|
||||
|
|
|
|||
|
|
@ -41,8 +41,8 @@ extern unsigned int mips_hpt_frequency;
|
|||
* 1) board_time_init() -
|
||||
* a) (optional) set up RTC routines,
|
||||
* b) (optional) calibrate and set the mips_hpt_frequency
|
||||
* (only needed if you intended to use fixed_rate_gettimeoffset
|
||||
* or use cpu counter as timer interrupt source)
|
||||
* (only needed if you intended to use cpu counter as timer interrupt
|
||||
* source)
|
||||
*/
|
||||
|
||||
void pnx8550_time_init(void)
|
||||
|
|
|
|||
|
|
@ -3,9 +3,7 @@
|
|||
|
||||
#include <asm/pmon.h>
|
||||
#include <asm/titan_dep.h>
|
||||
|
||||
extern unsigned int (*mips_hpt_read)(void);
|
||||
extern void (*mips_hpt_init)(unsigned int);
|
||||
#include <asm/time.h>
|
||||
|
||||
#define LAUNCHSTACK_SIZE 256
|
||||
|
||||
|
|
@ -101,7 +99,7 @@ void prom_cpus_done(void)
|
|||
*/
|
||||
void prom_init_secondary(void)
|
||||
{
|
||||
mips_hpt_init(mips_hpt_read());
|
||||
mips_hpt_init();
|
||||
|
||||
set_c0_status(ST0_CO | ST0_IE | ST0_IM);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -134,13 +134,6 @@ again:
|
|||
irq_exit();
|
||||
}
|
||||
|
||||
unsigned long ip27_do_gettimeoffset(void)
|
||||
{
|
||||
unsigned long ct_cur1;
|
||||
ct_cur1 = REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT) + CYCLES_PER_JIFFY;
|
||||
return (ct_cur1 - ct_cur[0]) * NSEC_PER_CYCLE / 1000;
|
||||
}
|
||||
|
||||
/* Includes for ioc3_init(). */
|
||||
#include <asm/sn/types.h>
|
||||
#include <asm/sn/sn0/addrs.h>
|
||||
|
|
@ -248,12 +241,17 @@ void __init plat_timer_setup(struct irqaction *irq)
|
|||
setup_irq(irqno, &rt_irqaction);
|
||||
}
|
||||
|
||||
static unsigned int ip27_hpt_read(void)
|
||||
{
|
||||
return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT);
|
||||
}
|
||||
|
||||
void __init ip27_time_init(void)
|
||||
{
|
||||
mips_hpt_read = ip27_hpt_read;
|
||||
mips_hpt_frequency = CYCLES_PER_SEC;
|
||||
xtime.tv_sec = get_m48t35_time();
|
||||
xtime.tv_nsec = 0;
|
||||
|
||||
do_gettimeoffset = ip27_do_gettimeoffset;
|
||||
}
|
||||
|
||||
void __init cpu_time_init(void)
|
||||
|
|
|
|||
|
|
@ -47,6 +47,12 @@
|
|||
#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
|
||||
#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
|
||||
|
||||
#ifdef CONFIG_SIMULATION
|
||||
#define BCM1480_HPT_VALUE 50000
|
||||
#else
|
||||
#define BCM1480_HPT_VALUE 1000000
|
||||
#endif
|
||||
|
||||
extern int bcm1480_steal_irq(int irq);
|
||||
|
||||
void bcm1480_time_init(void)
|
||||
|
|
@ -59,11 +65,6 @@ void bcm1480_time_init(void)
|
|||
BUG();
|
||||
}
|
||||
|
||||
if (!cpu) {
|
||||
/* Use our own gettimeoffset() routine */
|
||||
do_gettimeoffset = bcm1480_gettimeoffset;
|
||||
}
|
||||
|
||||
bcm1480_mask_irq(cpu, irq);
|
||||
|
||||
/* Map the timer interrupt to ip[4] of this cpu */
|
||||
|
|
@ -74,11 +75,7 @@ void bcm1480_time_init(void)
|
|||
/* Disable the timer and set up the count */
|
||||
__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
|
||||
__raw_writeq(
|
||||
#ifndef CONFIG_SIMULATION
|
||||
1000000/HZ
|
||||
#else
|
||||
50000/HZ
|
||||
#endif
|
||||
BCM1480_HPT_VALUE/HZ
|
||||
, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
|
||||
|
||||
/* Set the timer running */
|
||||
|
|
@ -122,16 +119,16 @@ void bcm1480_timer_interrupt(void)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* We use our own do_gettimeoffset() instead of the generic one,
|
||||
* because the generic one does not work for SMP case.
|
||||
* In addition, since we use general timer 0 for system time,
|
||||
* we can get accurate intra-jiffy offset without calibration.
|
||||
*/
|
||||
unsigned long bcm1480_gettimeoffset(void)
|
||||
static unsigned int bcm1480_hpt_read(void)
|
||||
{
|
||||
/* We assume this function is called xtime_lock held. */
|
||||
unsigned long count =
|
||||
__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
|
||||
|
||||
return 1000000/HZ - count;
|
||||
return (jiffies + 1) * (BCM1480_HPT_VALUE / HZ) - count;
|
||||
}
|
||||
|
||||
void __init bcm1480_hpt_setup(void)
|
||||
{
|
||||
mips_hpt_read = bcm1480_hpt_read;
|
||||
mips_hpt_frequency = BCM1480_HPT_VALUE;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -47,15 +47,11 @@
|
|||
|
||||
#define SB1250_HPT_NUM 3
|
||||
#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
|
||||
#define SB1250_HPT_SHIFT ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH)
|
||||
|
||||
|
||||
extern int sb1250_steal_irq(int irq);
|
||||
|
||||
static unsigned int sb1250_hpt_read(void);
|
||||
static void sb1250_hpt_init(unsigned int);
|
||||
|
||||
static unsigned int hpt_offset;
|
||||
|
||||
void __init sb1250_hpt_setup(void)
|
||||
{
|
||||
|
|
@ -69,13 +65,9 @@ void __init sb1250_hpt_setup(void)
|
|||
__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
|
||||
IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
|
||||
|
||||
/*
|
||||
* we need to fill 32 bits, so just use the upper 23 bits and pretend
|
||||
* the timer is going 512Mhz instead of 1Mhz
|
||||
*/
|
||||
mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT;
|
||||
mips_hpt_init = sb1250_hpt_init;
|
||||
mips_hpt_frequency = V_SCD_TIMER_FREQ;
|
||||
mips_hpt_read = sb1250_hpt_read;
|
||||
mips_hpt_mask = M_SCD_TIMER_INIT;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -149,11 +141,7 @@ void sb1250_timer_interrupt(void)
|
|||
|
||||
/*
|
||||
* The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
|
||||
* again. There's no easy way to set to a specific value so store init value
|
||||
* in hpt_offset and subtract each time.
|
||||
*
|
||||
* Note: Timer isn't full 32bits so shift it into the upper part making
|
||||
* it appear to run at a higher frequency.
|
||||
* again.
|
||||
*/
|
||||
static unsigned int sb1250_hpt_read(void)
|
||||
{
|
||||
|
|
@ -161,13 +149,5 @@ static unsigned int sb1250_hpt_read(void)
|
|||
|
||||
count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
|
||||
|
||||
count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT;
|
||||
|
||||
return count - hpt_offset;
|
||||
}
|
||||
|
||||
static void sb1250_hpt_init(unsigned int count)
|
||||
{
|
||||
hpt_offset = count;
|
||||
return;
|
||||
return SB1250_HPT_VALUE - count;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue