From 16c6dbef2715459f7feecd46d09ef70197a1a914 Mon Sep 17 00:00:00 2001
From: Raghavendra Rao Ananta <rananta@quicinc.com>
Date: Thu, 24 Sep 2020 12:29:13 -0700
Subject: [PATCH] ARM: dts: msm: Vote for DDR BW for MPSS PIL on Lahaina

It is possible that the DDR bandwidth requirements are not
met during modem SSR. Hence, explicitly vote for DDR turbo
frequency during modem PIL.

Change-Id: I5134feaf593673beb8bbdafc416814a5d41fb47b
---
 qcom/lahaina.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index 2f48611e3666..c95a6dfe9c44 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -4425,6 +4425,8 @@
 		qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
 		qcom,proxy-reg-names = "vdd_cx", "vdd_mss";
 
+		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
+
 		qcom,firmware-name = "modem";
 		memory-region = <&pil_modem_mem>;
 		qcom,proxy-timeout-ms = <10000>;