mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
Third round of Renesas ARM SoC board updates for v3.10
Highlights: * Add Lager board support * Add ape6evm board support * Add Bock-W board support * Mackerel MMCIF/SDHI clean ups * Add ethernet support to kzm9g-reference This pull request is based on a merge of: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux2-for-v3.10 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards2-for-v3.10 The merge with renesas-pinmux2-for-v3.10 was made to provide run-time dependencies for the following changes: ARM: shmobile: APE6EVM LAN9220 support ARM: shmobile: APE6EVM PFC support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJRW4ucAAoJENfPZGlqN0++oHQP/jpJ6AAAwuFfcfPSnpWIkJY6 cidxxBwf445EcW1OXAKez4Ki4gJ8+AcYBp39dm5nm1HUSrmJgOVgbeQ/benakUi/ 5/Qgj0Hi4HmiYzrDuZo1SgBu3iHZy38KzbzpUFwBXYJW3snlM4WYET08FHzun/3j hvWI5fEgYC4FBzbU68Vc6R1aCZM+yio1wezRz+zMjkSJ2f6dGwM16oXbh0nLgWKk VdvAOTmNbzFIs/3frATcozBI956SJPha7SMq7YUSE0MRIcjpTtvhGnnWFyq3NQH6 JeSs7qKcXBJ8foOE333J+KGyXpMp/FgJxQo0C3N3/fbaiPH6+eE0gkRL27MUPdRy EES9FPGSzuDEe6WPG9pUOJEbkD3BjBUuokC8LDCPrFK1jXdPtz2yAeNOAz+sLDLe oYpmlE2D8dG7DbxrFNRrhFGgujHI4gV9I54IM58xEq3+MpzK0GS4GYYf3+Qas7ob P5qDenAIEC5b+Ox578iRyy35kP8cwbm9BV7zLAXCLVTjWEjcAWPRi+6r9TYt7DV1 /FzW2csVqyN/ec6WljJblImty1tvV1GuuHPQ8azu6ZHlxXQDPAo5KIROTVW/ud7m daReu65vkGwN8PMPpT/jMh38b8wGBkR9TgI2vCLOQ95PTY1UVdkyZIynUkMV5jX8 PxkEzDA3qHoMDI4/XPbD =Zhif -----END PGP SIGNATURE----- Merge tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2 Third round of Renesas ARM SoC board updates for v3.10 Highlights: * Add Lager board support * Add ape6evm board support * Add Bock-W board support * Mackerel MMCIF/SDHI clean ups * Add ethernet support to kzm9g-reference This pull request is based on a merge of: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux2-for-v3.10 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards2-for-v3.10 The merge with renesas-pinmux2-for-v3.10 was made to provide run-time dependencies for the following changes: ARM: shmobile: APE6EVM LAN9220 support ARM: shmobile: APE6EVM PFC support * tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (307 commits) ARM: shmobile: mackerel: clean up MMCIF vs. SDHI1 selection ARM: shmobile: mackerel: add interrupt names for SDHI0 ARM: shmobile: mackerel: switch SDHI and MMCIF interfaces to slot-gpio ARM: shmobile: mackerel: remove OCR masks, where regulators are used ARM: shmobile: mackerel: SDHI resources do not have to be numbered ARM: shmobile: Initial r8a7790 Lager board support ARM: shmobile: APE6EVM LAN9220 support ARM: shmobile: APE6EVM PFC support ARM: shmobile: APE6EVM base support ARM: shmobile: kzm9g-reference: add ethernet support ARM: shmobile: add R-Car M1A Bock-W platform support sh-pfc: r8a73a4: Remove unused GPIO bias data ARM: shmobile: r8a73a4: Remove all GPIO enums sh-pfc: r8a73a4: Remove function GPIOs ARM: shmobile: r8a73a4: Remove IRQC function GPIOs ARM: shmobile: r8a73a4: Remove SCIF function GPIOs sh-pfc: r8a73a4: Remove IRQC function GPIOS sh-pfc: r8a73a4: Remove SCIF function GPIOS sh-pfc: r8a73a4: Add IRQC pin groups and functions sh-pfc: r8a73a4: Add SCIF pin groups and functions ... Signed-off-by: Olof Johansson <[email protected]>
This commit is contained in:
Olof Johansson
commit
16eaaee4d8
141 changed files with 16949 additions and 7600 deletions
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@ -204,6 +204,12 @@ config GPIO_PXA
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help
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Say yes here to support the PXA GPIO device
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config GPIO_RCAR
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tristate "Renesas R-Car GPIO"
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depends on ARM
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help
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Say yes here to support GPIO on Renesas R-Car SoCs.
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config GPIO_SPEAR_SPICS
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bool "ST SPEAr13xx SPI Chip Select as GPIO support"
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depends on PLAT_SPEAR
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@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
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obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
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obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
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obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
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obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
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obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
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obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
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obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
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@ -15,6 +15,7 @@
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/bitops.h>
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#include <linux/workqueue.h>
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#include <linux/gpio.h>
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@ -22,6 +23,7 @@
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#include <linux/amba/bus.h>
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#include <linux/amba/pl061.h>
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#include <linux/slab.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm.h>
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#include <asm/mach/irq.h>
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@ -51,8 +53,7 @@ struct pl061_gpio {
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spinlock_t lock;
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void __iomem *base;
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int irq_base;
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struct irq_chip_generic *irq_gc;
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struct irq_domain *domain;
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struct gpio_chip gc;
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#ifdef CONFIG_PM
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@ -60,6 +61,17 @@ struct pl061_gpio {
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#endif
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};
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static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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/*
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* Map back to global GPIO space and request muxing, the direction
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* parameter does not matter for this controller.
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*/
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int gpio = chip->base + offset;
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return pinctrl_request_gpio(gpio);
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}
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static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
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{
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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@ -122,24 +134,20 @@ static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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if (chip->irq_base <= 0)
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return -EINVAL;
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return chip->irq_base + offset;
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return irq_create_mapping(chip->domain, offset);
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}
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static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pl061_gpio *chip = gc->private;
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int offset = d->irq - chip->irq_base;
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struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
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int offset = irqd_to_hwirq(d);
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unsigned long flags;
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u8 gpiois, gpioibe, gpioiev;
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if (offset < 0 || offset >= PL061_GPIO_NR)
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return -EINVAL;
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raw_spin_lock_irqsave(&gc->lock, flags);
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spin_lock_irqsave(&chip->lock, flags);
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gpioiev = readb(chip->base + GPIOIEV);
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@ -168,7 +176,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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writeb(gpioiev, chip->base + GPIOIEV);
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raw_spin_unlock_irqrestore(&gc->lock, flags);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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@ -192,31 +200,61 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
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chained_irq_exit(irqchip, desc);
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}
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static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base)
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static void pl061_irq_mask(struct irq_data *d)
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{
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struct irq_chip_type *ct;
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struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
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u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
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u8 gpioie;
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chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base,
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chip->base, handle_simple_irq);
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chip->irq_gc->private = chip;
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ct = chip->irq_gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_set_type = pl061_irq_type;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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ct->regs.mask = GPIOIE;
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irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR),
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IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
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spin_lock(&chip->lock);
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gpioie = readb(chip->base + GPIOIE) & ~mask;
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writeb(gpioie, chip->base + GPIOIE);
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spin_unlock(&chip->lock);
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}
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static void pl061_irq_unmask(struct irq_data *d)
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{
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struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
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u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
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u8 gpioie;
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spin_lock(&chip->lock);
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gpioie = readb(chip->base + GPIOIE) | mask;
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writeb(gpioie, chip->base + GPIOIE);
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spin_unlock(&chip->lock);
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}
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static struct irq_chip pl061_irqchip = {
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.name = "pl061 gpio",
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.irq_mask = pl061_irq_mask,
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.irq_unmask = pl061_irq_unmask,
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.irq_set_type = pl061_irq_type,
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};
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static int pl061_irq_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct pl061_gpio *chip = d->host_data;
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irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq,
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"pl061");
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irq_set_chip_data(virq, chip);
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irq_set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static const struct irq_domain_ops pl061_domain_ops = {
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.map = pl061_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
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{
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struct device *dev = &adev->dev;
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struct pl061_platform_data *pdata = dev->platform_data;
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struct pl061_gpio *chip;
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int ret, irq, i;
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int ret, irq, i, irq_base;
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chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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@ -224,24 +262,31 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
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if (pdata) {
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chip->gc.base = pdata->gpio_base;
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chip->irq_base = pdata->irq_base;
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} else if (adev->dev.of_node) {
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irq_base = pdata->irq_base;
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if (irq_base <= 0)
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return -ENODEV;
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} else {
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chip->gc.base = -1;
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chip->irq_base = 0;
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} else
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return -ENODEV;
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irq_base = 0;
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}
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if (!devm_request_mem_region(dev, adev->res.start,
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resource_size(&adev->res), "pl061"))
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resource_size(&adev->res), "pl061"))
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return -EBUSY;
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chip->base = devm_ioremap(dev, adev->res.start,
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resource_size(&adev->res));
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if (chip->base == NULL)
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resource_size(&adev->res));
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if (!chip->base)
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return -ENOMEM;
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chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
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irq_base, &pl061_domain_ops, chip);
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if (!chip->domain)
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return -ENODEV;
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spin_lock_init(&chip->lock);
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chip->gc.request = pl061_gpio_request;
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chip->gc.direction_input = pl061_direction_input;
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chip->gc.direction_output = pl061_direction_output;
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chip->gc.get = pl061_get_value;
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@ -259,12 +304,6 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
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/*
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* irq_chip support
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*/
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if (chip->irq_base <= 0)
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return 0;
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pl061_init_gc(chip, chip->irq_base);
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writeb(0, chip->base + GPIOIE); /* disable irqs */
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irq = adev->irq[0];
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if (irq < 0)
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396
drivers/gpio/gpio-rcar.c
Normal file
396
drivers/gpio/gpio-rcar.c
Normal file
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@ -0,0 +1,396 @@
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/*
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* Renesas R-Car GPIO Support
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*
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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struct gpio_rcar_priv {
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void __iomem *base;
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spinlock_t lock;
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struct gpio_rcar_config config;
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struct platform_device *pdev;
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struct gpio_chip gpio_chip;
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struct irq_chip irq_chip;
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struct irq_domain *irq_domain;
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};
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#define IOINTSEL 0x00
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#define INOUTSEL 0x04
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#define OUTDT 0x08
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#define INDT 0x0c
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#define INTDT 0x10
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#define INTCLR 0x14
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#define INTMSK 0x18
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#define MSKCLR 0x1c
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#define POSNEG 0x20
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#define EDGLEVEL 0x24
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#define FILONOFF 0x28
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static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
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{
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return ioread32(p->base + offs);
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}
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static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
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u32 value)
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{
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iowrite32(value, p->base + offs);
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}
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static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
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int bit, bool value)
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{
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u32 tmp = gpio_rcar_read(p, offs);
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if (value)
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tmp |= BIT(bit);
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else
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tmp &= ~BIT(bit);
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gpio_rcar_write(p, offs, tmp);
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}
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static void gpio_rcar_irq_disable(struct irq_data *d)
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{
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struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
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gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
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}
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static void gpio_rcar_irq_enable(struct irq_data *d)
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{
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struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
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gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
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}
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static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
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unsigned int hwirq,
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bool active_high_rising_edge,
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bool level_trigger)
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{
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unsigned long flags;
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|
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/* follow steps in the GPIO documentation for
|
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* "Setting Edge-Sensitive Interrupt Input Mode" and
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* "Setting Level-Sensitive Interrupt Input Mode"
|
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*/
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spin_lock_irqsave(&p->lock, flags);
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/* Configure postive or negative logic in POSNEG */
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gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
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/* Configure edge or level trigger in EDGLEVEL */
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gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
|
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|
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/* Select "Interrupt Input Mode" in IOINTSEL */
|
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gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
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|
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/* Write INTCLR in case of edge trigger */
|
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if (!level_trigger)
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gpio_rcar_write(p, INTCLR, BIT(hwirq));
|
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|
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spin_unlock_irqrestore(&p->lock, flags);
|
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}
|
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|
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static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
|
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{
|
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struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
|
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unsigned int hwirq = irqd_to_hwirq(d);
|
||||
|
||||
dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
|
||||
|
||||
switch (type & IRQ_TYPE_SENSE_MASK) {
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct gpio_rcar_priv *p = dev_id;
|
||||
u32 pending;
|
||||
unsigned int offset, irqs_handled = 0;
|
||||
|
||||
while ((pending = gpio_rcar_read(p, INTDT))) {
|
||||
offset = __ffs(pending);
|
||||
gpio_rcar_write(p, INTCLR, BIT(offset));
|
||||
generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
|
||||
irqs_handled++;
|
||||
}
|
||||
|
||||
return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
|
||||
}
|
||||
|
||||
static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
|
||||
{
|
||||
return container_of(chip, struct gpio_rcar_priv, gpio_chip);
|
||||
}
|
||||
|
||||
static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
|
||||
unsigned int gpio,
|
||||
bool output)
|
||||
{
|
||||
struct gpio_rcar_priv *p = gpio_to_priv(chip);
|
||||
unsigned long flags;
|
||||
|
||||
/* follow steps in the GPIO documentation for
|
||||
* "Setting General Output Mode" and
|
||||
* "Setting General Input Mode"
|
||||
*/
|
||||
|
||||
spin_lock_irqsave(&p->lock, flags);
|
||||
|
||||
/* Configure postive logic in POSNEG */
|
||||
gpio_rcar_modify_bit(p, POSNEG, gpio, false);
|
||||
|
||||
/* Select "General Input/Output Mode" in IOINTSEL */
|
||||
gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
|
||||
|
||||
/* Select Input Mode or Output Mode in INOUTSEL */
|
||||
gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
|
||||
|
||||
spin_unlock_irqrestore(&p->lock, flags);
|
||||
}
|
||||
|
||||
static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return pinctrl_request_gpio(chip->base + offset);
|
||||
}
|
||||
|
||||
static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
pinctrl_free_gpio(chip->base + offset);
|
||||
|
||||
/* Set the GPIO as an input to ensure that the next GPIO request won't
|
||||
* drive the GPIO pin as an output.
|
||||
*/
|
||||
gpio_rcar_config_general_input_output_mode(chip, offset, false);
|
||||
}
|
||||
|
||||
static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
gpio_rcar_config_general_input_output_mode(chip, offset, false);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset));
|
||||
}
|
||||
|
||||
static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
{
|
||||
struct gpio_rcar_priv *p = gpio_to_priv(chip);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&p->lock, flags);
|
||||
gpio_rcar_modify_bit(p, OUTDT, offset, value);
|
||||
spin_unlock_irqrestore(&p->lock, flags);
|
||||
}
|
||||
|
||||
static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
|
||||
int value)
|
||||
{
|
||||
/* write GPIO value to output before selecting output mode of pin */
|
||||
gpio_rcar_set(chip, offset, value);
|
||||
gpio_rcar_config_general_input_output_mode(chip, offset, true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
|
||||
}
|
||||
|
||||
static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
struct gpio_rcar_priv *p = h->host_data;
|
||||
|
||||
dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);
|
||||
|
||||
irq_set_chip_data(virq, h->host_data);
|
||||
irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
|
||||
set_irq_flags(virq, IRQF_VALID); /* kill me now */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
|
||||
.map = gpio_rcar_irq_domain_map,
|
||||
};
|
||||
|
||||
static int gpio_rcar_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct gpio_rcar_config *pdata = pdev->dev.platform_data;
|
||||
struct gpio_rcar_priv *p;
|
||||
struct resource *io, *irq;
|
||||
struct gpio_chip *gpio_chip;
|
||||
struct irq_chip *irq_chip;
|
||||
const char *name = dev_name(&pdev->dev);
|
||||
int ret;
|
||||
|
||||
p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
|
||||
if (!p) {
|
||||
dev_err(&pdev->dev, "failed to allocate driver data\n");
|
||||
ret = -ENOMEM;
|
||||
goto err0;
|
||||
}
|
||||
|
||||
/* deal with driver instance configuration */
|
||||
if (pdata)
|
||||
p->config = *pdata;
|
||||
|
||||
p->pdev = pdev;
|
||||
platform_set_drvdata(pdev, p);
|
||||
spin_lock_init(&p->lock);
|
||||
|
||||
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
|
||||
if (!io || !irq) {
|
||||
dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
|
||||
ret = -EINVAL;
|
||||
goto err0;
|
||||
}
|
||||
|
||||
p->base = devm_ioremap_nocache(&pdev->dev, io->start,
|
||||
resource_size(io));
|
||||
if (!p->base) {
|
||||
dev_err(&pdev->dev, "failed to remap I/O memory\n");
|
||||
ret = -ENXIO;
|
||||
goto err0;
|
||||
}
|
||||
|
||||
gpio_chip = &p->gpio_chip;
|
||||
gpio_chip->request = gpio_rcar_request;
|
||||
gpio_chip->free = gpio_rcar_free;
|
||||
gpio_chip->direction_input = gpio_rcar_direction_input;
|
||||
gpio_chip->get = gpio_rcar_get;
|
||||
gpio_chip->direction_output = gpio_rcar_direction_output;
|
||||
gpio_chip->set = gpio_rcar_set;
|
||||
gpio_chip->to_irq = gpio_rcar_to_irq;
|
||||
gpio_chip->label = name;
|
||||
gpio_chip->owner = THIS_MODULE;
|
||||
gpio_chip->base = p->config.gpio_base;
|
||||
gpio_chip->ngpio = p->config.number_of_pins;
|
||||
|
||||
irq_chip = &p->irq_chip;
|
||||
irq_chip->name = name;
|
||||
irq_chip->irq_mask = gpio_rcar_irq_disable;
|
||||
irq_chip->irq_unmask = gpio_rcar_irq_enable;
|
||||
irq_chip->irq_enable = gpio_rcar_irq_enable;
|
||||
irq_chip->irq_disable = gpio_rcar_irq_disable;
|
||||
irq_chip->irq_set_type = gpio_rcar_irq_set_type;
|
||||
irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;
|
||||
|
||||
p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
|
||||
p->config.number_of_pins,
|
||||
p->config.irq_base,
|
||||
&gpio_rcar_irq_domain_ops, p);
|
||||
if (!p->irq_domain) {
|
||||
ret = -ENXIO;
|
||||
dev_err(&pdev->dev, "cannot initialize irq domain\n");
|
||||
goto err1;
|
||||
}
|
||||
|
||||
if (devm_request_irq(&pdev->dev, irq->start,
|
||||
gpio_rcar_irq_handler, 0, name, p)) {
|
||||
dev_err(&pdev->dev, "failed to request IRQ\n");
|
||||
ret = -ENOENT;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
ret = gpiochip_add(gpio_chip);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to add GPIO controller\n");
|
||||
goto err1;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
|
||||
|
||||
/* warn in case of mismatch if irq base is specified */
|
||||
if (p->config.irq_base) {
|
||||
ret = irq_find_mapping(p->irq_domain, 0);
|
||||
if (p->config.irq_base != ret)
|
||||
dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
|
||||
p->config.irq_base, ret);
|
||||
}
|
||||
|
||||
ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
|
||||
gpio_chip->base, gpio_chip->ngpio);
|
||||
if (ret < 0)
|
||||
dev_warn(&pdev->dev, "failed to add pin range\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err1:
|
||||
irq_domain_remove(p->irq_domain);
|
||||
err0:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int gpio_rcar_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
ret = gpiochip_remove(&p->gpio_chip);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
irq_domain_remove(p->irq_domain);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver gpio_rcar_device_driver = {
|
||||
.probe = gpio_rcar_probe,
|
||||
.remove = gpio_rcar_remove,
|
||||
.driver = {
|
||||
.name = "gpio_rcar",
|
||||
}
|
||||
};
|
||||
|
||||
module_platform_driver(gpio_rcar_device_driver);
|
||||
|
||||
MODULE_AUTHOR("Magnus Damm");
|
||||
MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -193,7 +193,7 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
|
|||
if (!np)
|
||||
return;
|
||||
|
||||
do {
|
||||
for (;; index++) {
|
||||
ret = of_parse_phandle_with_args(np, "gpio-ranges",
|
||||
"#gpio-range-cells", index, &pinspec);
|
||||
if (ret)
|
||||
|
|
@ -203,27 +203,15 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
|
|||
if (!pctldev)
|
||||
break;
|
||||
|
||||
/*
|
||||
* This assumes that the n GPIO pins are consecutive in the
|
||||
* GPIO number space, and that the pins are also consecutive
|
||||
* in their local number space. Currently it is not possible
|
||||
* to add different ranges for one and the same GPIO chip,
|
||||
* as the code assumes that we have one consecutive range
|
||||
* on both, mapping 1-to-1.
|
||||
*
|
||||
* TODO: make the OF bindings handle multiple sparse ranges
|
||||
* on the same GPIO chip.
|
||||
*/
|
||||
ret = gpiochip_add_pin_range(chip,
|
||||
pinctrl_dev_get_devname(pctldev),
|
||||
0, /* offset in gpiochip */
|
||||
pinspec.args[0],
|
||||
pinspec.args[1]);
|
||||
pinspec.args[1],
|
||||
pinspec.args[2]);
|
||||
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
} while (index++);
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
|
|
|
|||
Loading…
Reference in a new issue