From 16f96a48fb6dfb5e5fe06f5ad92e2f57daa618cb Mon Sep 17 00:00:00 2001
From: Rama Krishna Phani A <rphani@codeaurora.org>
Date: Tue, 8 Dec 2020 11:11:07 +0530
Subject: [PATCH] msm: pcie: add support for gcc_aggre_noc_pcie_*_axi_clk

PCIe root complex(RC) driver needs to support enable/disable
gcc_aggre_noc_pcie*_axi_clk.

Change-Id: I80d7301033c9005afd50028aa1fecb8ca983dc93
Signed-off-by: Rama Krishna Phani A <rphani@codeaurora.org>
---
 drivers/pci/controller/pci-msm.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c
index ea6b41f57f2f..5e805aba8250 100644
--- a/drivers/pci/controller/pci-msm.c
+++ b/drivers/pci/controller/pci-msm.c
@@ -192,7 +192,7 @@
 #define MAX_RC_NAME_LEN (15)
 #define MSM_PCIE_MAX_VREG (5)
 #define MSM_PCIE_VREG_0P9 (2)
-#define MSM_PCIE_MAX_CLK (18)
+#define MSM_PCIE_MAX_CLK (21)
 #define MSM_PCIE_MAX_PIPE_CLK (1)
 #define MAX_RC_NUM (5)
 #define MAX_DEVICE_NUM (20)
@@ -991,7 +991,10 @@ static struct msm_pcie_clk_info_t
 	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
 	{NULL, "pcie_phy_aux_clk", 0, false, false},
 	{NULL, "pcie_pipe_clk_mux", 0, false, false},
-	{NULL, "pcie_pipe_clk_ext_src", 0, false, false}
+	{NULL, "pcie_pipe_clk_ext_src", 0, false, false},
+	{NULL, "pcie_aggre_noc_south_sf_axi_clk", 0, false, false},
+	{NULL, "pcie_aggre_noc_4_axi_clk", 0, false, false},
+	{NULL, "pcie_0_pipediv2_clk", 0, false, false}
 	},
 	{
 	{NULL, "pcie_1_ref_clk_src", 0, false, false},
@@ -1011,7 +1014,10 @@ static struct msm_pcie_clk_info_t
 	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
 	{NULL, "pcie_phy_aux_clk", 0, false, false},
 	{NULL, "pcie_pipe_clk_mux", 0, false, false},
-	{NULL, "pcie_pipe_clk_ext_src", 0, false, false}
+	{NULL, "pcie_pipe_clk_ext_src", 0, false, false},
+	{NULL, "pcie_aggre_noc_south_sf_axi_clk", 0, false, false},
+	{NULL, "pcie_aggre_noc_4_axi_clk", 0, false, false},
+	{NULL, "pcie_1_pipediv2_clk", 0, false, false}
 	},
 	{
 	{NULL, "pcie_2_ref_clk_src", 0, false, false},
@@ -1031,7 +1037,10 @@ static struct msm_pcie_clk_info_t
 	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
 	{NULL, "pcie_phy_aux_clk", 0, false, false},
 	{NULL, "pcie_pipe_clk_mux", 0, false, false},
-	{NULL, "pcie_pipe_clk_ext_src", 0, false, false}
+	{NULL, "pcie_pipe_clk_ext_src", 0, false, false},
+	{NULL, "pcie_aggre_noc_south_sf_axi_clk", 0, false, false},
+	{NULL, "pcie_aggre_noc_4_axi_clk", 0, false, false},
+	{NULL, "pcie_2_pipediv2_clk", 0, false, false}
 	},
 	{
 	{NULL, "pcie_3_ref_clk_src", 0, false, false},
@@ -1051,7 +1060,10 @@ static struct msm_pcie_clk_info_t
 	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
 	{NULL, "pcie_phy_aux_clk", 0, false, false},
 	{NULL, "pcie_pipe_clk_mux", 0, false, false},
-	{NULL, "pcie_pipe_clk_ext_src", 0, false, false}
+	{NULL, "pcie_pipe_clk_ext_src", 0, false, false},
+	{NULL, "pcie_aggre_noc_south_sf_axi_clk", 0, false, false},
+	{NULL, "pcie_aggre_noc_4_axi_clk", 0, false, false},
+	{NULL, "pcie_3_pipediv2_clk", 0, false, false}
 	},
 	{
 	{NULL, "pcie_4_ref_clk_src", 0, false, false},
@@ -1071,7 +1083,10 @@ static struct msm_pcie_clk_info_t
 	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
 	{NULL, "pcie_phy_aux_clk", 0, false, false},
 	{NULL, "pcie_pipe_clk_mux", 0, false, false},
-	{NULL, "pcie_pipe_clk_ext_src", 0, false, false}
+	{NULL, "pcie_pipe_clk_ext_src", 0, false, false},
+	{NULL, "pcie_aggre_noc_south_sf_axi_clk", 0, false, false},
+	{NULL, "pcie_aggre_noc_4_axi_clk", 0, false, false},
+	{NULL, "pcie_4_pipediv2_clk", 0, false, false}
 	}
 };