mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 21:22:09 -04:00
Merge "msm: cvp: Add AXI reset pulse"
This commit is contained in:
commit
1723ebdd64
5 changed files with 60 additions and 33 deletions
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@ -3213,18 +3213,21 @@ err_clk_get:
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}
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static int __handle_reset_clk(struct msm_cvp_platform_resources *res,
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int reset_index, enum reset_state state)
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int reset_index, enum reset_state state,
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enum power_state pwr_state)
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{
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int rc = 0;
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struct reset_control *rst;
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struct reset_info rst_info;
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struct reset_set *rst_set = &res->reset_set;
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if (!rst_set->reset_tbl)
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return 0;
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rst = rst_set->reset_tbl[reset_index].rst;
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dprintk(CVP_DBG, "reset_clk: name %s reset_state %d rst %pK\n",
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rst_set->reset_tbl[reset_index].name, state, rst);
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rst_info = rst_set->reset_tbl[reset_index];
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rst = rst_info.rst;
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dprintk(CVP_DBG, "reset_clk: name %s reset_state %d rst %pK ps=%d\n",
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rst_set->reset_tbl[reset_index].name, state, rst, pwr_state);
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switch (state) {
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case INIT:
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@ -3244,6 +3247,9 @@ static int __handle_reset_clk(struct msm_cvp_platform_resources *res,
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goto failed_to_reset;
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}
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if (pwr_state != rst_info.required_state)
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break;
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rc = reset_control_assert(rst);
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break;
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case DEASSERT:
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@ -3251,6 +3257,10 @@ static int __handle_reset_clk(struct msm_cvp_platform_resources *res,
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rc = PTR_ERR(rst);
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goto failed_to_reset;
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}
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if (pwr_state != rst_info.required_state)
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break;
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rc = reset_control_deassert(rst);
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break;
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default:
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@ -3285,6 +3295,7 @@ static inline void __disable_unprepare_clks(struct iris_hfi_device *device)
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static int reset_ahb2axi_bridge(struct iris_hfi_device *device)
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{
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int rc, i;
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enum power_state s;
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if (!device) {
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dprintk(CVP_ERR, "NULL device\n");
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@ -3292,8 +3303,13 @@ static int reset_ahb2axi_bridge(struct iris_hfi_device *device)
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goto failed_to_reset;
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}
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if (device->power_enabled)
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s = CVP_POWER_ON;
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else
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s = CVP_POWER_OFF;
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for (i = 0; i < device->res->reset_set.count; i++) {
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rc = __handle_reset_clk(device->res, i, ASSERT);
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rc = __handle_reset_clk(device->res, i, ASSERT, s);
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if (rc) {
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dprintk(CVP_ERR,
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"failed to assert reset clocks\n");
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@ -3303,7 +3319,7 @@ static int reset_ahb2axi_bridge(struct iris_hfi_device *device)
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/* wait for deassert */
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usleep_range(150, 250);
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rc = __handle_reset_clk(device->res, i, DEASSERT);
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rc = __handle_reset_clk(device->res, i, DEASSERT, s);
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if (rc) {
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dprintk(CVP_ERR,
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"failed to deassert reset clocks\n");
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@ -3534,7 +3550,7 @@ static int __init_resources(struct iris_hfi_device *device,
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}
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for (i = 0; i < device->res->reset_set.count; i++) {
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rc = __handle_reset_clk(res, i, INIT);
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rc = __handle_reset_clk(res, i, INIT, 0);
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if (rc) {
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dprintk(CVP_ERR, "Failed to init reset clocks\n");
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rc = -ENODEV;
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@ -3916,7 +3932,6 @@ static int __iris_power_on(struct iris_hfi_device *device)
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if (device->power_enabled)
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return 0;
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device->power_enabled = true;
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/* Vote for all hardware resources */
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rc = __vote_buses(device, device->bus_vote.data,
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device->bus_vote.data_count);
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@ -3950,6 +3965,9 @@ static int __iris_power_on(struct iris_hfi_device *device)
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rc = 0;
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}
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/*Do not access registers before this point!*/
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device->power_enabled = true;
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dprintk(CVP_DBG, "Done with scaling\n");
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/*
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* Re-program all of the registers that get reset as a result of
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@ -4083,23 +4101,8 @@ static void power_off_iris2(struct iris_hfi_device *device)
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/* HPG 6.1.2 Step 3, debug bridge to low power */
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__write_register(device,
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CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x7);
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reg_status = 0;
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count = 0;
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while ((reg_status != 0x7) && count < max_count) {
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lpi_status = __read_register(device,
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CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
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reg_status = lpi_status & 0x7;
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/* Wait for debug bridge lpi status to be set */
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usleep_range(50, 100);
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count++;
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}
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dprintk(CVP_DBG,
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"DBLP Set : lpi_status %d reg_status %d (count %d)\n",
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lpi_status, reg_status, count);
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if (count == max_count) {
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dprintk(CVP_WARN,
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"DBLP Set: status %x %x\n", reg_status, lpi_status);
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}
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usleep_range(50, 100);
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/* HPG 6.1.2 Step 4, debug bridge to lpi release */
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__write_register(device,
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@ -4119,6 +4122,10 @@ static void power_off_iris2(struct iris_hfi_device *device)
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dprintk(CVP_WARN,
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"DBLP Release: lpi_status %x\n", lpi_status);
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}
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/* HPG 6.1.2 Step 5 */
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if (__disable_regulators(device))
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dprintk(CVP_WARN, "Failed to disable regulators\n");
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/* HPG 6.1.2 Step 6 */
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__disable_unprepare_clks(device);
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@ -4127,12 +4134,10 @@ static void power_off_iris2(struct iris_hfi_device *device)
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if (call_iris_op(device, reset_ahb2axi_bridge, device))
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dprintk(CVP_ERR, "Failed to reset ahb2axi\n");
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/* HPG 6.1.2 Step 5 */
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if (__disable_regulators(device))
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dprintk(CVP_WARN, "Failed to disable regulators\n");
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if (__unvote_buses(device))
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dprintk(CVP_WARN, "Failed to unvote for buses\n");
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/*Do not access registers after this point!*/
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device->power_enabled = false;
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}
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@ -38,4 +38,5 @@ void print_client_buffer(u32 tag, const char *str,
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struct msm_cvp_inst *inst, struct cvp_kmd_buffer *cbuf);
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void print_smem(u32 tag, const char *str, struct msm_cvp_inst *inst,
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struct msm_cvp_smem *smem);
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int msm_cvp_noc_error_info(struct msm_cvp_core *core);
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#endif
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@ -108,7 +108,7 @@ static struct msm_cvp_common_data sm8350_common_data[] = {
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},
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{
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.key = "qcom,sw-power-collapse",
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.value = 0,
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.value = 1,
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},
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{
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.key = "qcom,domain-attr-non-fatal-faults",
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@ -626,17 +626,20 @@ err_load_clk_table_fail:
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return rc;
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}
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#define MAX_CLK_RESETS 5
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static int msm_cvp_load_reset_table(
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struct msm_cvp_platform_resources *res)
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{
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struct platform_device *pdev = res->pdev;
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struct reset_set *rst = &res->reset_set;
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int num_clocks = 0, c = 0;
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int num_clocks = 0, c = 0, ret = 0;
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int pwr_stats[MAX_CLK_RESETS];
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num_clocks = of_property_count_strings(pdev->dev.of_node,
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"reset-names");
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if (num_clocks <= 0) {
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dprintk(CVP_DBG, "No reset clocks found\n");
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if (num_clocks <= 0 || num_clocks > MAX_CLK_RESETS) {
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dprintk(CVP_ERR, "Num reset clocks out of range\n");
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rst->count = 0;
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return 0;
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}
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@ -648,12 +651,21 @@ static int msm_cvp_load_reset_table(
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rst->count = num_clocks;
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dprintk(CVP_DBG, "Found %d reset clocks\n", num_clocks);
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ret = of_property_read_u32_array(pdev->dev.of_node,
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"reset-power-status", pwr_stats,
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num_clocks);
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if (ret) {
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dprintk(CVP_ERR, "Failed to read reset pwr state: %d\n", ret);
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devm_kfree(&pdev->dev, rst->reset_tbl);
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return ret;
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}
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for (c = 0; c < num_clocks; ++c) {
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struct reset_info *rc = &res->reset_set.reset_tbl[c];
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of_property_read_string_index(pdev->dev.of_node,
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"reset-names", c, &rc->name);
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rc->required_state = pwr_stats[c];
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}
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return 0;
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@ -895,6 +907,7 @@ int msm_cvp_smmu_fault_handler(struct iommu_domain *domain,
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msm_cvp_comm_print_inst_info(inst);
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}
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core->smmu_fault_handled = true;
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msm_cvp_noc_error_info(core);
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mutex_unlock(&core->lock);
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/*
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* Return -EINVAL to elicit the default behaviour of smmu driver.
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@ -83,8 +83,16 @@ struct bus_set {
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u32 count;
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};
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enum power_state {
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CVP_POWER_INIT,
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CVP_POWER_ON,
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CVP_POWER_OFF,
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CVP_POWER_INVALID,
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};
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struct reset_info {
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struct reset_control *rst;
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enum power_state required_state;
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const char *name;
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};
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