mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
pinctrl: add pinctrl-mxs support
Add pinctrl support for Freescale MXS SoCs, i.MX23 and i.MX28. The driver supports device tree probe only. Signed-off-by: Shawn Guo <[email protected]> Acked-by: Stephen Warren <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
This commit is contained in:
Shawn Guo
Linus Walleij
parent
d8fe35727a
commit
17723111e6
7 changed files with 2261 additions and 0 deletions
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@ -49,6 +49,21 @@ config PINCTRL_MMP2
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select PINCTRL_PXA3xx
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select PINCONF
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config PINCTRL_MXS
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bool
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config PINCTRL_IMX23
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bool
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select PINMUX
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select PINCONF
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select PINCTRL_MXS
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config PINCTRL_IMX28
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bool
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select PINMUX
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select PINCONF
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select PINCTRL_MXS
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config PINCTRL_PXA168
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bool "PXA168 pin controller driver"
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depends on ARCH_MMP
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@ -13,6 +13,9 @@ obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
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obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
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obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
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obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
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obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
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obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
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obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
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obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
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obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
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obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
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305
drivers/pinctrl/pinctrl-imx23.c
Normal file
305
drivers/pinctrl/pinctrl-imx23.c
Normal file
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@ -0,0 +1,305 @@
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-mxs.h"
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enum imx23_pin_enum {
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GPMI_D00 = PINID(0, 0),
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GPMI_D01 = PINID(0, 1),
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GPMI_D02 = PINID(0, 2),
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GPMI_D03 = PINID(0, 3),
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GPMI_D04 = PINID(0, 4),
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GPMI_D05 = PINID(0, 5),
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GPMI_D06 = PINID(0, 6),
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GPMI_D07 = PINID(0, 7),
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GPMI_D08 = PINID(0, 8),
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GPMI_D09 = PINID(0, 9),
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GPMI_D10 = PINID(0, 10),
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GPMI_D11 = PINID(0, 11),
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GPMI_D12 = PINID(0, 12),
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GPMI_D13 = PINID(0, 13),
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GPMI_D14 = PINID(0, 14),
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GPMI_D15 = PINID(0, 15),
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GPMI_CLE = PINID(0, 16),
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GPMI_ALE = PINID(0, 17),
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GPMI_CE2N = PINID(0, 18),
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GPMI_RDY0 = PINID(0, 19),
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GPMI_RDY1 = PINID(0, 20),
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GPMI_RDY2 = PINID(0, 21),
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GPMI_RDY3 = PINID(0, 22),
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GPMI_WPN = PINID(0, 23),
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GPMI_WRN = PINID(0, 24),
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GPMI_RDN = PINID(0, 25),
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AUART1_CTS = PINID(0, 26),
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AUART1_RTS = PINID(0, 27),
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AUART1_RX = PINID(0, 28),
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AUART1_TX = PINID(0, 29),
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I2C_SCL = PINID(0, 30),
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I2C_SDA = PINID(0, 31),
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LCD_D00 = PINID(1, 0),
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LCD_D01 = PINID(1, 1),
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LCD_D02 = PINID(1, 2),
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LCD_D03 = PINID(1, 3),
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LCD_D04 = PINID(1, 4),
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LCD_D05 = PINID(1, 5),
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LCD_D06 = PINID(1, 6),
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LCD_D07 = PINID(1, 7),
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LCD_D08 = PINID(1, 8),
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LCD_D09 = PINID(1, 9),
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LCD_D10 = PINID(1, 10),
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LCD_D11 = PINID(1, 11),
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LCD_D12 = PINID(1, 12),
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LCD_D13 = PINID(1, 13),
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LCD_D14 = PINID(1, 14),
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LCD_D15 = PINID(1, 15),
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LCD_D16 = PINID(1, 16),
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LCD_D17 = PINID(1, 17),
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LCD_RESET = PINID(1, 18),
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LCD_RS = PINID(1, 19),
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LCD_WR = PINID(1, 20),
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LCD_CS = PINID(1, 21),
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LCD_DOTCK = PINID(1, 22),
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LCD_ENABLE = PINID(1, 23),
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LCD_HSYNC = PINID(1, 24),
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LCD_VSYNC = PINID(1, 25),
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PWM0 = PINID(1, 26),
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PWM1 = PINID(1, 27),
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PWM2 = PINID(1, 28),
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PWM3 = PINID(1, 29),
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PWM4 = PINID(1, 30),
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SSP1_CMD = PINID(2, 0),
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SSP1_DETECT = PINID(2, 1),
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SSP1_DATA0 = PINID(2, 2),
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SSP1_DATA1 = PINID(2, 3),
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SSP1_DATA2 = PINID(2, 4),
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SSP1_DATA3 = PINID(2, 5),
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SSP1_SCK = PINID(2, 6),
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ROTARYA = PINID(2, 7),
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ROTARYB = PINID(2, 8),
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EMI_A00 = PINID(2, 9),
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EMI_A01 = PINID(2, 10),
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EMI_A02 = PINID(2, 11),
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EMI_A03 = PINID(2, 12),
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EMI_A04 = PINID(2, 13),
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EMI_A05 = PINID(2, 14),
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EMI_A06 = PINID(2, 15),
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EMI_A07 = PINID(2, 16),
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EMI_A08 = PINID(2, 17),
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EMI_A09 = PINID(2, 18),
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EMI_A10 = PINID(2, 19),
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EMI_A11 = PINID(2, 20),
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EMI_A12 = PINID(2, 21),
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EMI_BA0 = PINID(2, 22),
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EMI_BA1 = PINID(2, 23),
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EMI_CASN = PINID(2, 24),
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EMI_CE0N = PINID(2, 25),
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EMI_CE1N = PINID(2, 26),
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GPMI_CE1N = PINID(2, 27),
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GPMI_CE0N = PINID(2, 28),
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EMI_CKE = PINID(2, 29),
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EMI_RASN = PINID(2, 30),
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EMI_WEN = PINID(2, 31),
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EMI_D00 = PINID(3, 0),
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EMI_D01 = PINID(3, 1),
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EMI_D02 = PINID(3, 2),
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EMI_D03 = PINID(3, 3),
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EMI_D04 = PINID(3, 4),
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EMI_D05 = PINID(3, 5),
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EMI_D06 = PINID(3, 6),
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EMI_D07 = PINID(3, 7),
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EMI_D08 = PINID(3, 8),
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EMI_D09 = PINID(3, 9),
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EMI_D10 = PINID(3, 10),
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EMI_D11 = PINID(3, 11),
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EMI_D12 = PINID(3, 12),
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EMI_D13 = PINID(3, 13),
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EMI_D14 = PINID(3, 14),
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EMI_D15 = PINID(3, 15),
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EMI_DQM0 = PINID(3, 16),
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EMI_DQM1 = PINID(3, 17),
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EMI_DQS0 = PINID(3, 18),
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EMI_DQS1 = PINID(3, 19),
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EMI_CLK = PINID(3, 20),
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EMI_CLKN = PINID(3, 21),
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};
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static const struct pinctrl_pin_desc imx23_pins[] = {
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MXS_PINCTRL_PIN(GPMI_D00),
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MXS_PINCTRL_PIN(GPMI_D01),
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MXS_PINCTRL_PIN(GPMI_D02),
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MXS_PINCTRL_PIN(GPMI_D03),
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MXS_PINCTRL_PIN(GPMI_D04),
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MXS_PINCTRL_PIN(GPMI_D05),
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MXS_PINCTRL_PIN(GPMI_D06),
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MXS_PINCTRL_PIN(GPMI_D07),
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MXS_PINCTRL_PIN(GPMI_D08),
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MXS_PINCTRL_PIN(GPMI_D09),
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MXS_PINCTRL_PIN(GPMI_D10),
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MXS_PINCTRL_PIN(GPMI_D11),
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MXS_PINCTRL_PIN(GPMI_D12),
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MXS_PINCTRL_PIN(GPMI_D13),
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MXS_PINCTRL_PIN(GPMI_D14),
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MXS_PINCTRL_PIN(GPMI_D15),
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MXS_PINCTRL_PIN(GPMI_CLE),
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MXS_PINCTRL_PIN(GPMI_ALE),
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MXS_PINCTRL_PIN(GPMI_CE2N),
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MXS_PINCTRL_PIN(GPMI_RDY0),
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MXS_PINCTRL_PIN(GPMI_RDY1),
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MXS_PINCTRL_PIN(GPMI_RDY2),
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MXS_PINCTRL_PIN(GPMI_RDY3),
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MXS_PINCTRL_PIN(GPMI_WPN),
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MXS_PINCTRL_PIN(GPMI_WRN),
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MXS_PINCTRL_PIN(GPMI_RDN),
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MXS_PINCTRL_PIN(AUART1_CTS),
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MXS_PINCTRL_PIN(AUART1_RTS),
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MXS_PINCTRL_PIN(AUART1_RX),
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MXS_PINCTRL_PIN(AUART1_TX),
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MXS_PINCTRL_PIN(I2C_SCL),
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MXS_PINCTRL_PIN(I2C_SDA),
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MXS_PINCTRL_PIN(LCD_D00),
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MXS_PINCTRL_PIN(LCD_D01),
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MXS_PINCTRL_PIN(LCD_D02),
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MXS_PINCTRL_PIN(LCD_D03),
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MXS_PINCTRL_PIN(LCD_D04),
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MXS_PINCTRL_PIN(LCD_D05),
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MXS_PINCTRL_PIN(LCD_D06),
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MXS_PINCTRL_PIN(LCD_D07),
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MXS_PINCTRL_PIN(LCD_D08),
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MXS_PINCTRL_PIN(LCD_D09),
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MXS_PINCTRL_PIN(LCD_D10),
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MXS_PINCTRL_PIN(LCD_D11),
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MXS_PINCTRL_PIN(LCD_D12),
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MXS_PINCTRL_PIN(LCD_D13),
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MXS_PINCTRL_PIN(LCD_D14),
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MXS_PINCTRL_PIN(LCD_D15),
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MXS_PINCTRL_PIN(LCD_D16),
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MXS_PINCTRL_PIN(LCD_D17),
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MXS_PINCTRL_PIN(LCD_RESET),
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MXS_PINCTRL_PIN(LCD_RS),
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MXS_PINCTRL_PIN(LCD_WR),
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MXS_PINCTRL_PIN(LCD_CS),
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MXS_PINCTRL_PIN(LCD_DOTCK),
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MXS_PINCTRL_PIN(LCD_ENABLE),
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MXS_PINCTRL_PIN(LCD_HSYNC),
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MXS_PINCTRL_PIN(LCD_VSYNC),
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MXS_PINCTRL_PIN(PWM0),
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MXS_PINCTRL_PIN(PWM1),
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MXS_PINCTRL_PIN(PWM2),
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MXS_PINCTRL_PIN(PWM3),
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MXS_PINCTRL_PIN(PWM4),
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MXS_PINCTRL_PIN(SSP1_CMD),
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MXS_PINCTRL_PIN(SSP1_DETECT),
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MXS_PINCTRL_PIN(SSP1_DATA0),
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MXS_PINCTRL_PIN(SSP1_DATA1),
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MXS_PINCTRL_PIN(SSP1_DATA2),
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MXS_PINCTRL_PIN(SSP1_DATA3),
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MXS_PINCTRL_PIN(SSP1_SCK),
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MXS_PINCTRL_PIN(ROTARYA),
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MXS_PINCTRL_PIN(ROTARYB),
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MXS_PINCTRL_PIN(EMI_A00),
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MXS_PINCTRL_PIN(EMI_A01),
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MXS_PINCTRL_PIN(EMI_A02),
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MXS_PINCTRL_PIN(EMI_A03),
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MXS_PINCTRL_PIN(EMI_A04),
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MXS_PINCTRL_PIN(EMI_A05),
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MXS_PINCTRL_PIN(EMI_A06),
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MXS_PINCTRL_PIN(EMI_A07),
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MXS_PINCTRL_PIN(EMI_A08),
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MXS_PINCTRL_PIN(EMI_A09),
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MXS_PINCTRL_PIN(EMI_A10),
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MXS_PINCTRL_PIN(EMI_A11),
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MXS_PINCTRL_PIN(EMI_A12),
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MXS_PINCTRL_PIN(EMI_BA0),
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MXS_PINCTRL_PIN(EMI_BA1),
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MXS_PINCTRL_PIN(EMI_CASN),
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MXS_PINCTRL_PIN(EMI_CE0N),
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MXS_PINCTRL_PIN(EMI_CE1N),
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MXS_PINCTRL_PIN(GPMI_CE1N),
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MXS_PINCTRL_PIN(GPMI_CE0N),
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MXS_PINCTRL_PIN(EMI_CKE),
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MXS_PINCTRL_PIN(EMI_RASN),
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MXS_PINCTRL_PIN(EMI_WEN),
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MXS_PINCTRL_PIN(EMI_D00),
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MXS_PINCTRL_PIN(EMI_D01),
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MXS_PINCTRL_PIN(EMI_D02),
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MXS_PINCTRL_PIN(EMI_D03),
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MXS_PINCTRL_PIN(EMI_D04),
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MXS_PINCTRL_PIN(EMI_D05),
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MXS_PINCTRL_PIN(EMI_D06),
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MXS_PINCTRL_PIN(EMI_D07),
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MXS_PINCTRL_PIN(EMI_D08),
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MXS_PINCTRL_PIN(EMI_D09),
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MXS_PINCTRL_PIN(EMI_D10),
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MXS_PINCTRL_PIN(EMI_D11),
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MXS_PINCTRL_PIN(EMI_D12),
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MXS_PINCTRL_PIN(EMI_D13),
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MXS_PINCTRL_PIN(EMI_D14),
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MXS_PINCTRL_PIN(EMI_D15),
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MXS_PINCTRL_PIN(EMI_DQM0),
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MXS_PINCTRL_PIN(EMI_DQM1),
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MXS_PINCTRL_PIN(EMI_DQS0),
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MXS_PINCTRL_PIN(EMI_DQS1),
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MXS_PINCTRL_PIN(EMI_CLK),
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MXS_PINCTRL_PIN(EMI_CLKN),
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};
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static struct mxs_regs imx23_regs = {
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.muxsel = 0x100,
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.drive = 0x200,
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.pull = 0x400,
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};
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static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
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.regs = &imx23_regs,
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.pins = imx23_pins,
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.npins = ARRAY_SIZE(imx23_pins),
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};
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static int __devinit imx23_pinctrl_probe(struct platform_device *pdev)
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{
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return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
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}
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static struct of_device_id imx23_pinctrl_of_match[] __devinitdata = {
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{ .compatible = "fsl,imx23-pinctrl", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
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static struct platform_driver imx23_pinctrl_driver = {
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.driver = {
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.name = "imx23-pinctrl",
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.owner = THIS_MODULE,
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.of_match_table = imx23_pinctrl_of_match,
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},
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.probe = imx23_pinctrl_probe,
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.remove = __devexit_p(mxs_pinctrl_remove),
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};
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static int __init imx23_pinctrl_init(void)
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{
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return platform_driver_register(&imx23_pinctrl_driver);
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}
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arch_initcall(imx23_pinctrl_init);
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static void __exit imx23_pinctrl_exit(void)
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{
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platform_driver_unregister(&imx23_pinctrl_driver);
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}
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module_exit(imx23_pinctrl_exit);
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MODULE_AUTHOR("Shawn Guo <[email protected]>");
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MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
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MODULE_LICENSE("GPL v2");
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421
drivers/pinctrl/pinctrl-imx28.c
Normal file
421
drivers/pinctrl/pinctrl-imx28.c
Normal file
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@ -0,0 +1,421 @@
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-mxs.h"
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enum imx28_pin_enum {
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GPMI_D00 = PINID(0, 0),
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GPMI_D01 = PINID(0, 1),
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GPMI_D02 = PINID(0, 2),
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GPMI_D03 = PINID(0, 3),
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GPMI_D04 = PINID(0, 4),
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GPMI_D05 = PINID(0, 5),
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GPMI_D06 = PINID(0, 6),
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GPMI_D07 = PINID(0, 7),
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GPMI_CE0N = PINID(0, 16),
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GPMI_CE1N = PINID(0, 17),
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GPMI_CE2N = PINID(0, 18),
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GPMI_CE3N = PINID(0, 19),
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GPMI_RDY0 = PINID(0, 20),
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GPMI_RDY1 = PINID(0, 21),
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GPMI_RDY2 = PINID(0, 22),
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GPMI_RDY3 = PINID(0, 23),
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GPMI_RDN = PINID(0, 24),
|
||||
GPMI_WRN = PINID(0, 25),
|
||||
GPMI_ALE = PINID(0, 26),
|
||||
GPMI_CLE = PINID(0, 27),
|
||||
GPMI_RESETN = PINID(0, 28),
|
||||
LCD_D00 = PINID(1, 0),
|
||||
LCD_D01 = PINID(1, 1),
|
||||
LCD_D02 = PINID(1, 2),
|
||||
LCD_D03 = PINID(1, 3),
|
||||
LCD_D04 = PINID(1, 4),
|
||||
LCD_D05 = PINID(1, 5),
|
||||
LCD_D06 = PINID(1, 6),
|
||||
LCD_D07 = PINID(1, 7),
|
||||
LCD_D08 = PINID(1, 8),
|
||||
LCD_D09 = PINID(1, 9),
|
||||
LCD_D10 = PINID(1, 10),
|
||||
LCD_D11 = PINID(1, 11),
|
||||
LCD_D12 = PINID(1, 12),
|
||||
LCD_D13 = PINID(1, 13),
|
||||
LCD_D14 = PINID(1, 14),
|
||||
LCD_D15 = PINID(1, 15),
|
||||
LCD_D16 = PINID(1, 16),
|
||||
LCD_D17 = PINID(1, 17),
|
||||
LCD_D18 = PINID(1, 18),
|
||||
LCD_D19 = PINID(1, 19),
|
||||
LCD_D20 = PINID(1, 20),
|
||||
LCD_D21 = PINID(1, 21),
|
||||
LCD_D22 = PINID(1, 22),
|
||||
LCD_D23 = PINID(1, 23),
|
||||
LCD_RD_E = PINID(1, 24),
|
||||
LCD_WR_RWN = PINID(1, 25),
|
||||
LCD_RS = PINID(1, 26),
|
||||
LCD_CS = PINID(1, 27),
|
||||
LCD_VSYNC = PINID(1, 28),
|
||||
LCD_HSYNC = PINID(1, 29),
|
||||
LCD_DOTCLK = PINID(1, 30),
|
||||
LCD_ENABLE = PINID(1, 31),
|
||||
SSP0_DATA0 = PINID(2, 0),
|
||||
SSP0_DATA1 = PINID(2, 1),
|
||||
SSP0_DATA2 = PINID(2, 2),
|
||||
SSP0_DATA3 = PINID(2, 3),
|
||||
SSP0_DATA4 = PINID(2, 4),
|
||||
SSP0_DATA5 = PINID(2, 5),
|
||||
SSP0_DATA6 = PINID(2, 6),
|
||||
SSP0_DATA7 = PINID(2, 7),
|
||||
SSP0_CMD = PINID(2, 8),
|
||||
SSP0_DETECT = PINID(2, 9),
|
||||
SSP0_SCK = PINID(2, 10),
|
||||
SSP1_SCK = PINID(2, 12),
|
||||
SSP1_CMD = PINID(2, 13),
|
||||
SSP1_DATA0 = PINID(2, 14),
|
||||
SSP1_DATA3 = PINID(2, 15),
|
||||
SSP2_SCK = PINID(2, 16),
|
||||
SSP2_MOSI = PINID(2, 17),
|
||||
SSP2_MISO = PINID(2, 18),
|
||||
SSP2_SS0 = PINID(2, 19),
|
||||
SSP2_SS1 = PINID(2, 20),
|
||||
SSP2_SS2 = PINID(2, 21),
|
||||
SSP3_SCK = PINID(2, 24),
|
||||
SSP3_MOSI = PINID(2, 25),
|
||||
SSP3_MISO = PINID(2, 26),
|
||||
SSP3_SS0 = PINID(2, 27),
|
||||
AUART0_RX = PINID(3, 0),
|
||||
AUART0_TX = PINID(3, 1),
|
||||
AUART0_CTS = PINID(3, 2),
|
||||
AUART0_RTS = PINID(3, 3),
|
||||
AUART1_RX = PINID(3, 4),
|
||||
AUART1_TX = PINID(3, 5),
|
||||
AUART1_CTS = PINID(3, 6),
|
||||
AUART1_RTS = PINID(3, 7),
|
||||
AUART2_RX = PINID(3, 8),
|
||||
AUART2_TX = PINID(3, 9),
|
||||
AUART2_CTS = PINID(3, 10),
|
||||
AUART2_RTS = PINID(3, 11),
|
||||
AUART3_RX = PINID(3, 12),
|
||||
AUART3_TX = PINID(3, 13),
|
||||
AUART3_CTS = PINID(3, 14),
|
||||
AUART3_RTS = PINID(3, 15),
|
||||
PWM0 = PINID(3, 16),
|
||||
PWM1 = PINID(3, 17),
|
||||
PWM2 = PINID(3, 18),
|
||||
SAIF0_MCLK = PINID(3, 20),
|
||||
SAIF0_LRCLK = PINID(3, 21),
|
||||
SAIF0_BITCLK = PINID(3, 22),
|
||||
SAIF0_SDATA0 = PINID(3, 23),
|
||||
I2C0_SCL = PINID(3, 24),
|
||||
I2C0_SDA = PINID(3, 25),
|
||||
SAIF1_SDATA0 = PINID(3, 26),
|
||||
SPDIF = PINID(3, 27),
|
||||
PWM3 = PINID(3, 28),
|
||||
PWM4 = PINID(3, 29),
|
||||
LCD_RESET = PINID(3, 30),
|
||||
ENET0_MDC = PINID(4, 0),
|
||||
ENET0_MDIO = PINID(4, 1),
|
||||
ENET0_RX_EN = PINID(4, 2),
|
||||
ENET0_RXD0 = PINID(4, 3),
|
||||
ENET0_RXD1 = PINID(4, 4),
|
||||
ENET0_TX_CLK = PINID(4, 5),
|
||||
ENET0_TX_EN = PINID(4, 6),
|
||||
ENET0_TXD0 = PINID(4, 7),
|
||||
ENET0_TXD1 = PINID(4, 8),
|
||||
ENET0_RXD2 = PINID(4, 9),
|
||||
ENET0_RXD3 = PINID(4, 10),
|
||||
ENET0_TXD2 = PINID(4, 11),
|
||||
ENET0_TXD3 = PINID(4, 12),
|
||||
ENET0_RX_CLK = PINID(4, 13),
|
||||
ENET0_COL = PINID(4, 14),
|
||||
ENET0_CRS = PINID(4, 15),
|
||||
ENET_CLK = PINID(4, 16),
|
||||
JTAG_RTCK = PINID(4, 20),
|
||||
EMI_D00 = PINID(5, 0),
|
||||
EMI_D01 = PINID(5, 1),
|
||||
EMI_D02 = PINID(5, 2),
|
||||
EMI_D03 = PINID(5, 3),
|
||||
EMI_D04 = PINID(5, 4),
|
||||
EMI_D05 = PINID(5, 5),
|
||||
EMI_D06 = PINID(5, 6),
|
||||
EMI_D07 = PINID(5, 7),
|
||||
EMI_D08 = PINID(5, 8),
|
||||
EMI_D09 = PINID(5, 9),
|
||||
EMI_D10 = PINID(5, 10),
|
||||
EMI_D11 = PINID(5, 11),
|
||||
EMI_D12 = PINID(5, 12),
|
||||
EMI_D13 = PINID(5, 13),
|
||||
EMI_D14 = PINID(5, 14),
|
||||
EMI_D15 = PINID(5, 15),
|
||||
EMI_ODT0 = PINID(5, 16),
|
||||
EMI_DQM0 = PINID(5, 17),
|
||||
EMI_ODT1 = PINID(5, 18),
|
||||
EMI_DQM1 = PINID(5, 19),
|
||||
EMI_DDR_OPEN_FB = PINID(5, 20),
|
||||
EMI_CLK = PINID(5, 21),
|
||||
EMI_DQS0 = PINID(5, 22),
|
||||
EMI_DQS1 = PINID(5, 23),
|
||||
EMI_DDR_OPEN = PINID(5, 26),
|
||||
EMI_A00 = PINID(6, 0),
|
||||
EMI_A01 = PINID(6, 1),
|
||||
EMI_A02 = PINID(6, 2),
|
||||
EMI_A03 = PINID(6, 3),
|
||||
EMI_A04 = PINID(6, 4),
|
||||
EMI_A05 = PINID(6, 5),
|
||||
EMI_A06 = PINID(6, 6),
|
||||
EMI_A07 = PINID(6, 7),
|
||||
EMI_A08 = PINID(6, 8),
|
||||
EMI_A09 = PINID(6, 9),
|
||||
EMI_A10 = PINID(6, 10),
|
||||
EMI_A11 = PINID(6, 11),
|
||||
EMI_A12 = PINID(6, 12),
|
||||
EMI_A13 = PINID(6, 13),
|
||||
EMI_A14 = PINID(6, 14),
|
||||
EMI_BA0 = PINID(6, 16),
|
||||
EMI_BA1 = PINID(6, 17),
|
||||
EMI_BA2 = PINID(6, 18),
|
||||
EMI_CASN = PINID(6, 19),
|
||||
EMI_RASN = PINID(6, 20),
|
||||
EMI_WEN = PINID(6, 21),
|
||||
EMI_CE0N = PINID(6, 22),
|
||||
EMI_CE1N = PINID(6, 23),
|
||||
EMI_CKE = PINID(6, 24),
|
||||
};
|
||||
|
||||
static const struct pinctrl_pin_desc imx28_pins[] = {
|
||||
MXS_PINCTRL_PIN(GPMI_D00),
|
||||
MXS_PINCTRL_PIN(GPMI_D01),
|
||||
MXS_PINCTRL_PIN(GPMI_D02),
|
||||
MXS_PINCTRL_PIN(GPMI_D03),
|
||||
MXS_PINCTRL_PIN(GPMI_D04),
|
||||
MXS_PINCTRL_PIN(GPMI_D05),
|
||||
MXS_PINCTRL_PIN(GPMI_D06),
|
||||
MXS_PINCTRL_PIN(GPMI_D07),
|
||||
MXS_PINCTRL_PIN(GPMI_CE0N),
|
||||
MXS_PINCTRL_PIN(GPMI_CE1N),
|
||||
MXS_PINCTRL_PIN(GPMI_CE2N),
|
||||
MXS_PINCTRL_PIN(GPMI_CE3N),
|
||||
MXS_PINCTRL_PIN(GPMI_RDY0),
|
||||
MXS_PINCTRL_PIN(GPMI_RDY1),
|
||||
MXS_PINCTRL_PIN(GPMI_RDY2),
|
||||
MXS_PINCTRL_PIN(GPMI_RDY3),
|
||||
MXS_PINCTRL_PIN(GPMI_RDN),
|
||||
MXS_PINCTRL_PIN(GPMI_WRN),
|
||||
MXS_PINCTRL_PIN(GPMI_ALE),
|
||||
MXS_PINCTRL_PIN(GPMI_CLE),
|
||||
MXS_PINCTRL_PIN(GPMI_RESETN),
|
||||
MXS_PINCTRL_PIN(LCD_D00),
|
||||
MXS_PINCTRL_PIN(LCD_D01),
|
||||
MXS_PINCTRL_PIN(LCD_D02),
|
||||
MXS_PINCTRL_PIN(LCD_D03),
|
||||
MXS_PINCTRL_PIN(LCD_D04),
|
||||
MXS_PINCTRL_PIN(LCD_D05),
|
||||
MXS_PINCTRL_PIN(LCD_D06),
|
||||
MXS_PINCTRL_PIN(LCD_D07),
|
||||
MXS_PINCTRL_PIN(LCD_D08),
|
||||
MXS_PINCTRL_PIN(LCD_D09),
|
||||
MXS_PINCTRL_PIN(LCD_D10),
|
||||
MXS_PINCTRL_PIN(LCD_D11),
|
||||
MXS_PINCTRL_PIN(LCD_D12),
|
||||
MXS_PINCTRL_PIN(LCD_D13),
|
||||
MXS_PINCTRL_PIN(LCD_D14),
|
||||
MXS_PINCTRL_PIN(LCD_D15),
|
||||
MXS_PINCTRL_PIN(LCD_D16),
|
||||
MXS_PINCTRL_PIN(LCD_D17),
|
||||
MXS_PINCTRL_PIN(LCD_D18),
|
||||
MXS_PINCTRL_PIN(LCD_D19),
|
||||
MXS_PINCTRL_PIN(LCD_D20),
|
||||
MXS_PINCTRL_PIN(LCD_D21),
|
||||
MXS_PINCTRL_PIN(LCD_D22),
|
||||
MXS_PINCTRL_PIN(LCD_D23),
|
||||
MXS_PINCTRL_PIN(LCD_RD_E),
|
||||
MXS_PINCTRL_PIN(LCD_WR_RWN),
|
||||
MXS_PINCTRL_PIN(LCD_RS),
|
||||
MXS_PINCTRL_PIN(LCD_CS),
|
||||
MXS_PINCTRL_PIN(LCD_VSYNC),
|
||||
MXS_PINCTRL_PIN(LCD_HSYNC),
|
||||
MXS_PINCTRL_PIN(LCD_DOTCLK),
|
||||
MXS_PINCTRL_PIN(LCD_ENABLE),
|
||||
MXS_PINCTRL_PIN(SSP0_DATA0),
|
||||
MXS_PINCTRL_PIN(SSP0_DATA1),
|
||||
MXS_PINCTRL_PIN(SSP0_DATA2),
|
||||
MXS_PINCTRL_PIN(SSP0_DATA3),
|
||||
MXS_PINCTRL_PIN(SSP0_DATA4),
|
||||
MXS_PINCTRL_PIN(SSP0_DATA5),
|
||||
MXS_PINCTRL_PIN(SSP0_DATA6),
|
||||
MXS_PINCTRL_PIN(SSP0_DATA7),
|
||||
MXS_PINCTRL_PIN(SSP0_CMD),
|
||||
MXS_PINCTRL_PIN(SSP0_DETECT),
|
||||
MXS_PINCTRL_PIN(SSP0_SCK),
|
||||
MXS_PINCTRL_PIN(SSP1_SCK),
|
||||
MXS_PINCTRL_PIN(SSP1_CMD),
|
||||
MXS_PINCTRL_PIN(SSP1_DATA0),
|
||||
MXS_PINCTRL_PIN(SSP1_DATA3),
|
||||
MXS_PINCTRL_PIN(SSP2_SCK),
|
||||
MXS_PINCTRL_PIN(SSP2_MOSI),
|
||||
MXS_PINCTRL_PIN(SSP2_MISO),
|
||||
MXS_PINCTRL_PIN(SSP2_SS0),
|
||||
MXS_PINCTRL_PIN(SSP2_SS1),
|
||||
MXS_PINCTRL_PIN(SSP2_SS2),
|
||||
MXS_PINCTRL_PIN(SSP3_SCK),
|
||||
MXS_PINCTRL_PIN(SSP3_MOSI),
|
||||
MXS_PINCTRL_PIN(SSP3_MISO),
|
||||
MXS_PINCTRL_PIN(SSP3_SS0),
|
||||
MXS_PINCTRL_PIN(AUART0_RX),
|
||||
MXS_PINCTRL_PIN(AUART0_TX),
|
||||
MXS_PINCTRL_PIN(AUART0_CTS),
|
||||
MXS_PINCTRL_PIN(AUART0_RTS),
|
||||
MXS_PINCTRL_PIN(AUART1_RX),
|
||||
MXS_PINCTRL_PIN(AUART1_TX),
|
||||
MXS_PINCTRL_PIN(AUART1_CTS),
|
||||
MXS_PINCTRL_PIN(AUART1_RTS),
|
||||
MXS_PINCTRL_PIN(AUART2_RX),
|
||||
MXS_PINCTRL_PIN(AUART2_TX),
|
||||
MXS_PINCTRL_PIN(AUART2_CTS),
|
||||
MXS_PINCTRL_PIN(AUART2_RTS),
|
||||
MXS_PINCTRL_PIN(AUART3_RX),
|
||||
MXS_PINCTRL_PIN(AUART3_TX),
|
||||
MXS_PINCTRL_PIN(AUART3_CTS),
|
||||
MXS_PINCTRL_PIN(AUART3_RTS),
|
||||
MXS_PINCTRL_PIN(PWM0),
|
||||
MXS_PINCTRL_PIN(PWM1),
|
||||
MXS_PINCTRL_PIN(PWM2),
|
||||
MXS_PINCTRL_PIN(SAIF0_MCLK),
|
||||
MXS_PINCTRL_PIN(SAIF0_LRCLK),
|
||||
MXS_PINCTRL_PIN(SAIF0_BITCLK),
|
||||
MXS_PINCTRL_PIN(SAIF0_SDATA0),
|
||||
MXS_PINCTRL_PIN(I2C0_SCL),
|
||||
MXS_PINCTRL_PIN(I2C0_SDA),
|
||||
MXS_PINCTRL_PIN(SAIF1_SDATA0),
|
||||
MXS_PINCTRL_PIN(SPDIF),
|
||||
MXS_PINCTRL_PIN(PWM3),
|
||||
MXS_PINCTRL_PIN(PWM4),
|
||||
MXS_PINCTRL_PIN(LCD_RESET),
|
||||
MXS_PINCTRL_PIN(ENET0_MDC),
|
||||
MXS_PINCTRL_PIN(ENET0_MDIO),
|
||||
MXS_PINCTRL_PIN(ENET0_RX_EN),
|
||||
MXS_PINCTRL_PIN(ENET0_RXD0),
|
||||
MXS_PINCTRL_PIN(ENET0_RXD1),
|
||||
MXS_PINCTRL_PIN(ENET0_TX_CLK),
|
||||
MXS_PINCTRL_PIN(ENET0_TX_EN),
|
||||
MXS_PINCTRL_PIN(ENET0_TXD0),
|
||||
MXS_PINCTRL_PIN(ENET0_TXD1),
|
||||
MXS_PINCTRL_PIN(ENET0_RXD2),
|
||||
MXS_PINCTRL_PIN(ENET0_RXD3),
|
||||
MXS_PINCTRL_PIN(ENET0_TXD2),
|
||||
MXS_PINCTRL_PIN(ENET0_TXD3),
|
||||
MXS_PINCTRL_PIN(ENET0_RX_CLK),
|
||||
MXS_PINCTRL_PIN(ENET0_COL),
|
||||
MXS_PINCTRL_PIN(ENET0_CRS),
|
||||
MXS_PINCTRL_PIN(ENET_CLK),
|
||||
MXS_PINCTRL_PIN(JTAG_RTCK),
|
||||
MXS_PINCTRL_PIN(EMI_D00),
|
||||
MXS_PINCTRL_PIN(EMI_D01),
|
||||
MXS_PINCTRL_PIN(EMI_D02),
|
||||
MXS_PINCTRL_PIN(EMI_D03),
|
||||
MXS_PINCTRL_PIN(EMI_D04),
|
||||
MXS_PINCTRL_PIN(EMI_D05),
|
||||
MXS_PINCTRL_PIN(EMI_D06),
|
||||
MXS_PINCTRL_PIN(EMI_D07),
|
||||
MXS_PINCTRL_PIN(EMI_D08),
|
||||
MXS_PINCTRL_PIN(EMI_D09),
|
||||
MXS_PINCTRL_PIN(EMI_D10),
|
||||
MXS_PINCTRL_PIN(EMI_D11),
|
||||
MXS_PINCTRL_PIN(EMI_D12),
|
||||
MXS_PINCTRL_PIN(EMI_D13),
|
||||
MXS_PINCTRL_PIN(EMI_D14),
|
||||
MXS_PINCTRL_PIN(EMI_D15),
|
||||
MXS_PINCTRL_PIN(EMI_ODT0),
|
||||
MXS_PINCTRL_PIN(EMI_DQM0),
|
||||
MXS_PINCTRL_PIN(EMI_ODT1),
|
||||
MXS_PINCTRL_PIN(EMI_DQM1),
|
||||
MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
|
||||
MXS_PINCTRL_PIN(EMI_CLK),
|
||||
MXS_PINCTRL_PIN(EMI_DQS0),
|
||||
MXS_PINCTRL_PIN(EMI_DQS1),
|
||||
MXS_PINCTRL_PIN(EMI_DDR_OPEN),
|
||||
MXS_PINCTRL_PIN(EMI_A00),
|
||||
MXS_PINCTRL_PIN(EMI_A01),
|
||||
MXS_PINCTRL_PIN(EMI_A02),
|
||||
MXS_PINCTRL_PIN(EMI_A03),
|
||||
MXS_PINCTRL_PIN(EMI_A04),
|
||||
MXS_PINCTRL_PIN(EMI_A05),
|
||||
MXS_PINCTRL_PIN(EMI_A06),
|
||||
MXS_PINCTRL_PIN(EMI_A07),
|
||||
MXS_PINCTRL_PIN(EMI_A08),
|
||||
MXS_PINCTRL_PIN(EMI_A09),
|
||||
MXS_PINCTRL_PIN(EMI_A10),
|
||||
MXS_PINCTRL_PIN(EMI_A11),
|
||||
MXS_PINCTRL_PIN(EMI_A12),
|
||||
MXS_PINCTRL_PIN(EMI_A13),
|
||||
MXS_PINCTRL_PIN(EMI_A14),
|
||||
MXS_PINCTRL_PIN(EMI_BA0),
|
||||
MXS_PINCTRL_PIN(EMI_BA1),
|
||||
MXS_PINCTRL_PIN(EMI_BA2),
|
||||
MXS_PINCTRL_PIN(EMI_CASN),
|
||||
MXS_PINCTRL_PIN(EMI_RASN),
|
||||
MXS_PINCTRL_PIN(EMI_WEN),
|
||||
MXS_PINCTRL_PIN(EMI_CE0N),
|
||||
MXS_PINCTRL_PIN(EMI_CE1N),
|
||||
MXS_PINCTRL_PIN(EMI_CKE),
|
||||
};
|
||||
|
||||
static struct mxs_regs imx28_regs = {
|
||||
.muxsel = 0x100,
|
||||
.drive = 0x300,
|
||||
.pull = 0x600,
|
||||
};
|
||||
|
||||
static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
|
||||
.regs = &imx28_regs,
|
||||
.pins = imx28_pins,
|
||||
.npins = ARRAY_SIZE(imx28_pins),
|
||||
};
|
||||
|
||||
static int __devinit imx28_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
|
||||
}
|
||||
|
||||
static struct of_device_id imx28_pinctrl_of_match[] __devinitdata = {
|
||||
{ .compatible = "fsl,imx28-pinctrl", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
|
||||
|
||||
static struct platform_driver imx28_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "imx28-pinctrl",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = imx28_pinctrl_of_match,
|
||||
},
|
||||
.probe = imx28_pinctrl_probe,
|
||||
.remove = __devexit_p(mxs_pinctrl_remove),
|
||||
};
|
||||
|
||||
static int __init imx28_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&imx28_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(imx28_pinctrl_init);
|
||||
|
||||
static void __exit imx28_pinctrl_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&imx28_pinctrl_driver);
|
||||
}
|
||||
module_exit(imx28_pinctrl_exit);
|
||||
|
||||
MODULE_AUTHOR("Shawn Guo <[email protected]>");
|
||||
MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
508
drivers/pinctrl/pinctrl-mxs.c
Normal file
508
drivers/pinctrl/pinctrl-mxs.c
Normal file
|
|
@ -0,0 +1,508 @@
|
|||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinconf.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include "core.h"
|
||||
#include "pinctrl-mxs.h"
|
||||
|
||||
#define SUFFIX_LEN 4
|
||||
|
||||
struct mxs_pinctrl_data {
|
||||
struct device *dev;
|
||||
struct pinctrl_dev *pctl;
|
||||
void __iomem *base;
|
||||
struct mxs_pinctrl_soc_data *soc;
|
||||
};
|
||||
|
||||
static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return d->soc->ngroups;
|
||||
}
|
||||
|
||||
static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
|
||||
unsigned group)
|
||||
{
|
||||
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return d->soc->groups[group].name;
|
||||
}
|
||||
|
||||
static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
|
||||
const unsigned **pins, unsigned *num_pins)
|
||||
{
|
||||
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*pins = d->soc->groups[group].pins;
|
||||
*num_pins = d->soc->groups[group].npins;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
|
||||
unsigned offset)
|
||||
{
|
||||
seq_printf(s, " %s", dev_name(pctldev->dev));
|
||||
}
|
||||
|
||||
static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct device_node *np,
|
||||
struct pinctrl_map **map, unsigned *num_maps)
|
||||
{
|
||||
struct pinctrl_map *new_map;
|
||||
char *group;
|
||||
unsigned new_num;
|
||||
unsigned long config = 0;
|
||||
unsigned long *pconfig;
|
||||
int length = strlen(np->name) + SUFFIX_LEN;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = of_property_read_u32(np, "fsl,drive-strength", &val);
|
||||
if (!ret)
|
||||
config = val | MA_PRESENT;
|
||||
ret = of_property_read_u32(np, "fsl,voltage", &val);
|
||||
if (!ret)
|
||||
config |= val << VOL_SHIFT | VOL_PRESENT;
|
||||
ret = of_property_read_u32(np, "fsl,pull-up", &val);
|
||||
if (!ret)
|
||||
config |= val << PULL_SHIFT | PULL_PRESENT;
|
||||
|
||||
new_num = config ? 2 : 1;
|
||||
new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
|
||||
if (!new_map)
|
||||
return -ENOMEM;
|
||||
|
||||
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
|
||||
new_map[0].data.mux.function = np->name;
|
||||
|
||||
/* Compose group name */
|
||||
group = kzalloc(length, GFP_KERNEL);
|
||||
if (!group)
|
||||
return -ENOMEM;
|
||||
of_property_read_u32(np, "reg", &val);
|
||||
snprintf(group, length, "%s.%d", np->name, val);
|
||||
new_map[0].data.mux.group = group;
|
||||
|
||||
if (config) {
|
||||
pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
|
||||
if (!pconfig) {
|
||||
ret = -ENOMEM;
|
||||
goto free;
|
||||
}
|
||||
|
||||
new_map[1].type = PIN_MAP_TYPE_CONFIGS_GROUP;
|
||||
new_map[1].data.configs.group_or_pin = group;
|
||||
new_map[1].data.configs.configs = pconfig;
|
||||
new_map[1].data.configs.num_configs = 1;
|
||||
}
|
||||
|
||||
*map = new_map;
|
||||
*num_maps = new_num;
|
||||
|
||||
return 0;
|
||||
|
||||
free:
|
||||
kfree(new_map);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map *map, unsigned num_maps)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_maps; i++) {
|
||||
if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
|
||||
kfree(map[i].data.mux.group);
|
||||
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
|
||||
kfree(map[i].data.configs.configs);
|
||||
}
|
||||
|
||||
kfree(map);
|
||||
}
|
||||
|
||||
static struct pinctrl_ops mxs_pinctrl_ops = {
|
||||
.get_groups_count = mxs_get_groups_count,
|
||||
.get_group_name = mxs_get_group_name,
|
||||
.get_group_pins = mxs_get_group_pins,
|
||||
.pin_dbg_show = mxs_pin_dbg_show,
|
||||
.dt_node_to_map = mxs_dt_node_to_map,
|
||||
.dt_free_map = mxs_dt_free_map,
|
||||
};
|
||||
|
||||
static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return d->soc->nfunctions;
|
||||
}
|
||||
|
||||
static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
|
||||
unsigned function)
|
||||
{
|
||||
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return d->soc->functions[function].name;
|
||||
}
|
||||
|
||||
static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
|
||||
unsigned group,
|
||||
const char * const **groups,
|
||||
unsigned * const num_groups)
|
||||
{
|
||||
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*groups = d->soc->functions[group].groups;
|
||||
*num_groups = d->soc->functions[group].ngroups;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
unsigned group)
|
||||
{
|
||||
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct mxs_group *g = &d->soc->groups[group];
|
||||
void __iomem *reg;
|
||||
u8 bank, shift;
|
||||
u16 pin;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < g->npins; i++) {
|
||||
bank = PINID_TO_BANK(g->pins[i]);
|
||||
pin = PINID_TO_PIN(g->pins[i]);
|
||||
reg = d->base + d->soc->regs->muxsel;
|
||||
reg += bank * 0x20 + pin / 16 * 0x10;
|
||||
shift = pin % 16 * 2;
|
||||
|
||||
writel(0x3 << shift, reg + CLR);
|
||||
writel(g->muxsel[i] << shift, reg + SET);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mxs_pinctrl_disable(struct pinctrl_dev *pctldev,
|
||||
unsigned function, unsigned group)
|
||||
{
|
||||
/* Nothing to do here */
|
||||
}
|
||||
|
||||
static struct pinmux_ops mxs_pinmux_ops = {
|
||||
.get_functions_count = mxs_pinctrl_get_funcs_count,
|
||||
.get_function_name = mxs_pinctrl_get_func_name,
|
||||
.get_function_groups = mxs_pinctrl_get_func_groups,
|
||||
.enable = mxs_pinctrl_enable,
|
||||
.disable = mxs_pinctrl_disable,
|
||||
};
|
||||
|
||||
static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
|
||||
unsigned pin, unsigned long *config)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
|
||||
unsigned pin, unsigned long config)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
|
||||
unsigned group, unsigned long *config)
|
||||
{
|
||||
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*config = d->soc->groups[group].config;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
|
||||
unsigned group, unsigned long config)
|
||||
{
|
||||
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct mxs_group *g = &d->soc->groups[group];
|
||||
void __iomem *reg;
|
||||
u8 ma, vol, pull, bank, shift;
|
||||
u16 pin;
|
||||
int i;
|
||||
|
||||
ma = CONFIG_TO_MA(config);
|
||||
vol = CONFIG_TO_VOL(config);
|
||||
pull = CONFIG_TO_PULL(config);
|
||||
|
||||
for (i = 0; i < g->npins; i++) {
|
||||
bank = PINID_TO_BANK(g->pins[i]);
|
||||
pin = PINID_TO_PIN(g->pins[i]);
|
||||
|
||||
/* drive */
|
||||
reg = d->base + d->soc->regs->drive;
|
||||
reg += bank * 0x40 + pin / 8 * 0x10;
|
||||
|
||||
/* mA */
|
||||
if (config & MA_PRESENT) {
|
||||
shift = pin % 8 * 4;
|
||||
writel(0x3 << shift, reg + CLR);
|
||||
writel(ma << shift, reg + SET);
|
||||
}
|
||||
|
||||
/* vol */
|
||||
if (config & VOL_PRESENT) {
|
||||
shift = pin % 8 * 4 + 2;
|
||||
if (vol)
|
||||
writel(1 << shift, reg + SET);
|
||||
else
|
||||
writel(1 << shift, reg + CLR);
|
||||
}
|
||||
|
||||
/* pull */
|
||||
if (config & PULL_PRESENT) {
|
||||
reg = d->base + d->soc->regs->pull;
|
||||
reg += bank * 0x10;
|
||||
shift = pin;
|
||||
if (pull)
|
||||
writel(1 << shift, reg + SET);
|
||||
else
|
||||
writel(1 << shift, reg + CLR);
|
||||
}
|
||||
}
|
||||
|
||||
/* cache the config value for mxs_pinconf_group_get() */
|
||||
g->config = config;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned pin)
|
||||
{
|
||||
/* Not support */
|
||||
}
|
||||
|
||||
static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned group)
|
||||
{
|
||||
unsigned long config;
|
||||
|
||||
if (!mxs_pinconf_group_get(pctldev, group, &config))
|
||||
seq_printf(s, "0x%lx", config);
|
||||
}
|
||||
|
||||
struct pinconf_ops mxs_pinconf_ops = {
|
||||
.pin_config_get = mxs_pinconf_get,
|
||||
.pin_config_set = mxs_pinconf_set,
|
||||
.pin_config_group_get = mxs_pinconf_group_get,
|
||||
.pin_config_group_set = mxs_pinconf_group_set,
|
||||
.pin_config_dbg_show = mxs_pinconf_dbg_show,
|
||||
.pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
|
||||
};
|
||||
|
||||
static struct pinctrl_desc mxs_pinctrl_desc = {
|
||||
.pctlops = &mxs_pinctrl_ops,
|
||||
.pmxops = &mxs_pinmux_ops,
|
||||
.confops = &mxs_pinconf_ops,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev,
|
||||
struct device_node *np, int idx,
|
||||
const char **out_name)
|
||||
{
|
||||
struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
|
||||
struct mxs_group *g = &d->soc->groups[idx];
|
||||
struct property *prop;
|
||||
const char *propname = "fsl,pinmux-ids";
|
||||
char *group;
|
||||
int length = strlen(np->name) + SUFFIX_LEN;
|
||||
int i;
|
||||
u32 val;
|
||||
|
||||
group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
|
||||
if (!group)
|
||||
return -ENOMEM;
|
||||
of_property_read_u32(np, "reg", &val);
|
||||
snprintf(group, length, "%s.%d", np->name, val);
|
||||
g->name = group;
|
||||
|
||||
prop = of_find_property(np, propname, &length);
|
||||
if (!prop)
|
||||
return -EINVAL;
|
||||
g->npins = length / sizeof(u32);
|
||||
|
||||
g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
|
||||
GFP_KERNEL);
|
||||
if (!g->pins)
|
||||
return -ENOMEM;
|
||||
|
||||
g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
|
||||
GFP_KERNEL);
|
||||
if (!g->muxsel)
|
||||
return -ENOMEM;
|
||||
|
||||
of_property_read_u32_array(np, propname, g->pins, g->npins);
|
||||
for (i = 0; i < g->npins; i++) {
|
||||
g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
|
||||
g->pins[i] = MUXID_TO_PINID(g->pins[i]);
|
||||
}
|
||||
|
||||
*out_name = g->name;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev,
|
||||
struct mxs_pinctrl_data *d)
|
||||
{
|
||||
struct mxs_pinctrl_soc_data *soc = d->soc;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device_node *child;
|
||||
struct mxs_function *f;
|
||||
const char *fn, *fnull = "";
|
||||
int i = 0, idxf = 0, idxg = 0;
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
child = of_get_next_child(np, NULL);
|
||||
if (!child) {
|
||||
dev_err(&pdev->dev, "no group is defined\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
/* Count total functions and groups */
|
||||
fn = fnull;
|
||||
for_each_child_of_node(np, child) {
|
||||
/* Skip pure pinconf node */
|
||||
if (of_property_read_u32(child, "reg", &val))
|
||||
continue;
|
||||
if (strcmp(fn, child->name)) {
|
||||
fn = child->name;
|
||||
soc->nfunctions++;
|
||||
}
|
||||
soc->ngroups++;
|
||||
}
|
||||
|
||||
soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
|
||||
sizeof(*soc->functions), GFP_KERNEL);
|
||||
if (!soc->functions)
|
||||
return -ENOMEM;
|
||||
|
||||
soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
|
||||
sizeof(*soc->groups), GFP_KERNEL);
|
||||
if (!soc->groups)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Count groups for each function */
|
||||
fn = fnull;
|
||||
f = &soc->functions[idxf];
|
||||
for_each_child_of_node(np, child) {
|
||||
if (of_property_read_u32(child, "reg", &val))
|
||||
continue;
|
||||
if (strcmp(fn, child->name)) {
|
||||
f = &soc->functions[idxf++];
|
||||
f->name = fn = child->name;
|
||||
}
|
||||
f->ngroups++;
|
||||
};
|
||||
|
||||
/* Get groups for each function */
|
||||
idxf = 0;
|
||||
fn = fnull;
|
||||
for_each_child_of_node(np, child) {
|
||||
if (of_property_read_u32(child, "reg", &val))
|
||||
continue;
|
||||
if (strcmp(fn, child->name)) {
|
||||
f = &soc->functions[idxf++];
|
||||
f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
|
||||
sizeof(*f->groups),
|
||||
GFP_KERNEL);
|
||||
if (!f->groups)
|
||||
return -ENOMEM;
|
||||
fn = child->name;
|
||||
i = 0;
|
||||
}
|
||||
ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
|
||||
&f->groups[i++]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __devinit mxs_pinctrl_probe(struct platform_device *pdev,
|
||||
struct mxs_pinctrl_soc_data *soc)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct mxs_pinctrl_data *d;
|
||||
int ret;
|
||||
|
||||
d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
|
||||
if (!d)
|
||||
return -ENOMEM;
|
||||
|
||||
d->dev = &pdev->dev;
|
||||
d->soc = soc;
|
||||
|
||||
d->base = of_iomap(np, 0);
|
||||
if (!d->base)
|
||||
return -EADDRNOTAVAIL;
|
||||
|
||||
mxs_pinctrl_desc.pins = d->soc->pins;
|
||||
mxs_pinctrl_desc.npins = d->soc->npins;
|
||||
mxs_pinctrl_desc.name = dev_name(&pdev->dev);
|
||||
|
||||
platform_set_drvdata(pdev, d);
|
||||
|
||||
ret = mxs_pinctrl_probe_dt(pdev, d);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
|
||||
if (!d->pctl) {
|
||||
dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
iounmap(d->base);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
|
||||
|
||||
int __devexit mxs_pinctrl_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
|
||||
|
||||
pinctrl_unregister(d->pctl);
|
||||
iounmap(d->base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
|
||||
91
drivers/pinctrl/pinctrl-mxs.h
Normal file
91
drivers/pinctrl/pinctrl-mxs.h
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#ifndef __PINCTRL_MXS_H
|
||||
#define __PINCTRL_MXS_H
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
|
||||
#define SET 0x4
|
||||
#define CLR 0x8
|
||||
#define TOG 0xc
|
||||
|
||||
#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
|
||||
#define PINID(bank, pin) ((bank) * 32 + (pin))
|
||||
|
||||
/*
|
||||
* pinmux-id bit field definitions
|
||||
*
|
||||
* bank: 15..12 (4)
|
||||
* pin: 11..4 (8)
|
||||
* muxsel: 3..0 (4)
|
||||
*/
|
||||
#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
|
||||
#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
|
||||
|
||||
#define PINID_TO_BANK(p) ((p) >> 5)
|
||||
#define PINID_TO_PIN(p) ((p) % 32)
|
||||
|
||||
/*
|
||||
* pin config bit field definitions
|
||||
*
|
||||
* pull-up: 6..5 (2)
|
||||
* voltage: 4..3 (2)
|
||||
* mA: 2..0 (3)
|
||||
*
|
||||
* MSB of each field is presence bit for the config.
|
||||
*/
|
||||
#define PULL_PRESENT (1 << 6)
|
||||
#define PULL_SHIFT 5
|
||||
#define VOL_PRESENT (1 << 4)
|
||||
#define VOL_SHIFT 3
|
||||
#define MA_PRESENT (1 << 2)
|
||||
#define MA_SHIFT 0
|
||||
#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
|
||||
#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
|
||||
#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
|
||||
|
||||
struct mxs_function {
|
||||
const char *name;
|
||||
const char **groups;
|
||||
unsigned ngroups;
|
||||
};
|
||||
|
||||
struct mxs_group {
|
||||
const char *name;
|
||||
unsigned int *pins;
|
||||
unsigned npins;
|
||||
u8 *muxsel;
|
||||
u8 config;
|
||||
};
|
||||
|
||||
struct mxs_regs {
|
||||
u16 muxsel;
|
||||
u16 drive;
|
||||
u16 pull;
|
||||
};
|
||||
|
||||
struct mxs_pinctrl_soc_data {
|
||||
const struct mxs_regs *regs;
|
||||
const struct pinctrl_pin_desc *pins;
|
||||
unsigned npins;
|
||||
struct mxs_function *functions;
|
||||
unsigned nfunctions;
|
||||
struct mxs_group *groups;
|
||||
unsigned ngroups;
|
||||
};
|
||||
|
||||
int mxs_pinctrl_probe(struct platform_device *pdev,
|
||||
struct mxs_pinctrl_soc_data *soc);
|
||||
int mxs_pinctrl_remove(struct platform_device *pdev);
|
||||
|
||||
#endif /* __PINCTRL_MXS_H */
|
||||
Loading…
Reference in a new issue