mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
MMC core:
- Add new API to set VCCQ voltage - mmc_regulator_set_vqmmc() - Add new ioctl to allow userspace to send multi commands - Wait for card busy signalling before starting SDIO requests - Remove MMC_CLKGATE - Enable tuning for DDR50 mode - Some code clean-up/improvements to mmc pwrseq - Use highest priority for eMMC restart handler - Add DT bindings for eMMC hardware reset support - Extend the mmc_send_tuning() API - Improve ios show for debugfs - A couple of code optimizations MMC host: - Some generic OF improvements - Various code clean-ups - sirf: Add support for DDR50 - sunxi: Add support for card busy detection - mediatek: Use MMC_CAP_RUNTIME_RESUME - mediatek: Add support for eMMC HW-reset - mediatek: Add support for HS400 - dw_mmc: Convert to use the new mmc_regulator_set_vqmmc() API - dw_mmc: Add external DMA interface support - dw_mmc: Some various improvements - dw_mmc-rockchip: MMC tuning with the clock phase framework - sdhci: Properly clear IRQs during resume - sdhci: Enable tuning for DDR50 mode - sdhci-of-esdhc: Use IRQ mode for card detection - sdhci-of-esdhc: Support both BE and LE host controller - sdhci-pci: Build o2micro support in the same module - sdhci-pci: Support for new Intel host controllers - sdhci-acpi: Support for new Intel host controllers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWNyuHAAoJEP4mhCVzWIwpHHUP/38kYyuhHNWEagna2taCnb5r tacx0IEfjvEmkzFNX4qLyBlu8lvDMJPx/GYx1RxE10/ZEsdllBpgtuS2+4SLHdlR naUwPsjjMigf4FavsnMxYe9yqsHsDkzFgJ2zsrRm/5h+0G4Uj3X+ejgGPjAFu3KK 6Ldha83dagR065MT8AIQRkVfjwME2mQC4RbWxmIpEQrzS2mJi3QZ0UikVWs6TWuE +1pxCobspYXK4Q9UC455JvrMJtOjDi1JNBmVyTA2fS+SBeQ1ZqbnNSbK1VAXI43b TKgUN/wp2SGqNCL+dhsebTOdEwKUgxcRRCReZRR0DBvTDvETmXRZ6ji6XUtaSAHL TY4hbNL9bWJN0JoidgdUKcQ5GjZcvDQk3eY6L0FP/C/plDEBIel7Ndf8pQco9NBQ l1CXuhjNZvkmHf9w44FgdeEGM5l/hn8J725mrVU+XNrMKv1RuNQZ56h2i33ktk6c b3+uGLMAqat59yecyaFqZibI+9WQ0pS+zz0IgQxyWxU5i86z3hrk4fbxHpmFZuEz 7awBMjiXldrbUY0fvWK6KlnTz+kqHHKxD5o9Pr9xBo6H28AwL4zGFwcU8dDpaOSk o13lLvWcZYsSMuUwO+y5jQdGejTkD2ZeJY8LqAY+SB124qAngRXLwdyBp5uqnzLS mBJh2R2ztcin5TzaJN3c =gn/m -----END PGP SIGNATURE----- Merge tag 'mmc-v4.4' of git://git.linaro.org/people/ulf.hansson/mmc Pull MMC updates from Ulf Hansson: "MMC core: - Add new API to set VCCQ voltage - mmc_regulator_set_vqmmc() - Add new ioctl to allow userspace to send multi commands - Wait for card busy signalling before starting SDIO requests - Remove MMC_CLKGATE - Enable tuning for DDR50 mode - Some code clean-up/improvements to mmc pwrseq - Use highest priority for eMMC restart handler - Add DT bindings for eMMC hardware reset support - Extend the mmc_send_tuning() API - Improve ios show for debugfs - A couple of code optimizations MMC host: - Some generic OF improvements - Various code clean-ups - sirf: Add support for DDR50 - sunxi: Add support for card busy detection - mediatek: Use MMC_CAP_RUNTIME_RESUME - mediatek: Add support for eMMC HW-reset - mediatek: Add support for HS400 - dw_mmc: Convert to use the new mmc_regulator_set_vqmmc() API - dw_mmc: Add external DMA interface support - dw_mmc: Some various improvements - dw_mmc-rockchip: MMC tuning with the clock phase framework - sdhci: Properly clear IRQs during resume - sdhci: Enable tuning for DDR50 mode - sdhci-of-esdhc: Use IRQ mode for card detection - sdhci-of-esdhc: Support both BE and LE host controller - sdhci-pci: Build o2micro support in the same module - sdhci-pci: Support for new Intel host controllers - sdhci-acpi: Support for new Intel host controllers" * tag 'mmc-v4.4' of git://git.linaro.org/people/ulf.hansson/mmc: (73 commits) mmc: dw_mmc: fix the wrong setting for UHS-DDR50 mode mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl register mmc: dw_mmc: NULL dereference in error message mmc: pwrseq: Use highest priority for eMMC restart handler mmc: mediatek: add HS400 support mmc: mmc: extend the mmc_send_tuning() mmc: mediatek: add implement of ops->hw_reset() mmc: mediatek: fix got GPD checksum error interrupt when data transfer mmc: mediatek: change the argument "ddr" to "timing" mmc: mediatek: make cmd_ints_mask to const mmc: dt-bindings: update Mediatek MMC bindings mmc: core: Add DT bindings for eMMC hardware reset support mmc: omap_hsmmc: Enable omap_hsmmc for Keystone 2 mmc: sdhci-acpi: Add more ACPI HIDs for Intel controllers mmc: sdhci-pci: Add more PCI IDs for Intel controllers arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC ...
This commit is contained in:
Linus Torvalds
commit
17a1359034
67 changed files with 1703 additions and 910 deletions
|
|
@ -90,7 +90,7 @@
|
|||
regulators {
|
||||
vccio_sd: LDO_REG4 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
|
|
@ -116,7 +116,12 @@
|
|||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
|
||||
rockchip,default-sample-phase = <90>;
|
||||
num-slots = <1>;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc33_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -149,7 +149,9 @@
|
|||
broken-cd;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
rockchip,default-sample-phase = <158>;
|
||||
disable-wp;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
||||
|
|
@ -355,6 +357,10 @@
|
|||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc33_sys>;
|
||||
vqmmc-supply = <&vcc18_wl>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -222,8 +222,9 @@
|
|||
sdmmc: dwmmc@ff0c0000 {
|
||||
compatible = "rockchip,rk3288-dw-mshc";
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
|
||||
clock-names = "biu", "ciu";
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
|
||||
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xff0c0000 0x4000>;
|
||||
|
|
@ -233,8 +234,9 @@
|
|||
sdio0: dwmmc@ff0d0000 {
|
||||
compatible = "rockchip,rk3288-dw-mshc";
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
|
||||
clock-names = "biu", "ciu";
|
||||
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
|
||||
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xff0d0000 0x4000>;
|
||||
|
|
@ -244,8 +246,9 @@
|
|||
sdio1: dwmmc@ff0e0000 {
|
||||
compatible = "rockchip,rk3288-dw-mshc";
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
|
||||
clock-names = "biu", "ciu";
|
||||
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
|
||||
<&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xff0e0000 0x4000>;
|
||||
|
|
@ -255,8 +258,9 @@
|
|||
emmc: dwmmc@ff0f0000 {
|
||||
compatible = "rockchip,rk3288-dw-mshc";
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
|
||||
clock-names = "biu", "ciu";
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
||||
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xff0f0000 0x4000>;
|
||||
|
|
|
|||
|
|
@ -166,7 +166,6 @@ CONFIG_MMC_SDHCI=y
|
|||
CONFIG_MMC_SDHCI_S3C=y
|
||||
CONFIG_MMC_SDHCI_S3C_DMA=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_IDMAC=y
|
||||
CONFIG_MMC_DW_EXYNOS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_MAX77686=y
|
||||
|
|
|
|||
|
|
@ -69,7 +69,6 @@ CONFIG_NOP_USB_XCEIV=y
|
|||
CONFIG_MMC=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_IDMAC=y
|
||||
CONFIG_MMC_DW_PLTFM=y
|
||||
CONFIG_RTC_DRV_PL031=y
|
||||
CONFIG_DMADEVICES=y
|
||||
|
|
|
|||
|
|
@ -119,7 +119,6 @@ CONFIG_USB_EHCI_HCD=y
|
|||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_IDMAC=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_PCA9532=y
|
||||
|
|
|
|||
Loading…
Reference in a new issue