From 940410fd6af13edd42cb4bf57619eb16ebecc9fa Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 26 Aug 2020 15:07:37 +0530 Subject: [PATCH 1/4] ARM: dts: msm: add interconnect devices for sm6150 Add interconnect devices for sm6150. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I22a398c60f5d43fbc014abe9d04697bf01b9ccb7 --- qcom/sm6150.dtsi | 79 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 84627ecdbace..01cad5dff47e 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include / { @@ -760,6 +762,83 @@ , , ; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + }; + }; + + camnoc_virt: interconnect@0 { + compatible = "qcom,sm6150-camnoc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ipa_virt: interconnect@1 { + compatible = "qcom,sm6150-ipa_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@2 { + compatible = "qcom,sm6150-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + dc_noc: interconnect@9160000 { + reg = <0x9160000 0x3200>; + compatible = "qcom,sm6150-dc_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + reg = <0x9680000 0x3E200>; + compatible = "qcom,sm6150-gem_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + reg = <0x1500000 0x5080>; + compatible = "qcom,sm6150-config_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + reg = <0x1620000 0x1F300>; + compatible = "qcom,sm6150-system_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@1700000 { + reg = <0x1700000 0x3F200>; + compatible = "qcom,sm6150-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x1C100>; + compatible = "qcom,sm6150-mmss_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; }; aopcc: qcom,aopcc@0 { From 844bcc5e6b4fdc25904954b01a2147d158a5697d Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 3 Sep 2020 16:53:59 +0530 Subject: [PATCH 2/4] ARM: dts: msm: Enable L3 interconnect driver for SM6150 Enable L3 interconnect driver so that consumers are able to obtain their path handles properly. Change-Id: Ib1cf078b3929f3802c51dfcd17076bc6494b5d2e --- qcom/sm6150.dtsi | 78 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 01cad5dff47e..b8ed48c57741 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -967,6 +968,83 @@ #freq-domain-cells = <2>; }; + camnoc_virt: interconnect@0 { + compatible = "qcom,sm6150-camnoc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ipa_virt: interconnect@1 { + compatible = "qcom,sm6150-ipa_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@2 { + compatible = "qcom,sm6150-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + dc_noc: interconnect@9160000 { + reg = <0x9160000 0x3200>; + compatible = "qcom,sm6150-dc_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + reg = <0x9680000 0x3E200>; + compatible = "qcom,sm6150-gem_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + reg = <0x1500000 0x5080>; + compatible = "qcom,sm6150-config_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + reg = <0x1620000 0x1F300>; + compatible = "qcom,sm6150-system_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@1700000 { + reg = <0x1700000 0x3F200>; + compatible = "qcom,sm6150-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x1C100>; + compatible = "qcom,sm6150-mmss_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + osm_l3: interconnect@18321000 { + reg = <0x18321000 0x1400>; + compatible = "qcom,sm6150-osm-l3"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + qmp_aop: qcom,qmp-aop@c300000 { compatible = "qcom,qmp-mbox"; reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; From b433f97c834d5c486dcf3e67aa97ca079b9481e5 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 7 Sep 2020 12:28:48 +0530 Subject: [PATCH 3/4] ARM: dts: msm: Add UFS support for SA6155 Add UFS host controller and UFS PHY (attached to embedded UFS card) for SA6155 platform. Change-Id: Ic75617e3d8eb406f876cc71c8931bcfee545438d --- qcom/sa6155-adp-air.dtsi | 28 +++++++++ qcom/sa6155-adp-star.dtsi | 28 +++++++++ qcom/sm6150.dtsi | 118 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 174 insertions(+) diff --git a/qcom/sa6155-adp-air.dtsi b/qcom/sa6155-adp-air.dtsi index 91c1ac0cdf99..36c1103f0315 100644 --- a/qcom/sa6155-adp-air.dtsi +++ b/qcom/sa6155-adp-air.dtsi @@ -1 +1,29 @@ #include "sa6155-adp-common.dtsi" + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */ + vdda-pll-supply = <&pm6155_1_l12>; + vdda-phy-max-microamp = <30000>; + vdda-pll-max-microamp = <12000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6155_1_l17>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6155_1_s4>; + vcc-max-microamp = <800000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6155_1_l11>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1260000>; + + status = "ok"; +}; diff --git a/qcom/sa6155-adp-star.dtsi b/qcom/sa6155-adp-star.dtsi index 91c1ac0cdf99..36c1103f0315 100644 --- a/qcom/sa6155-adp-star.dtsi +++ b/qcom/sa6155-adp-star.dtsi @@ -1 +1,29 @@ #include "sa6155-adp-common.dtsi" + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */ + vdda-pll-supply = <&pm6155_1_l12>; + vdda-phy-max-microamp = <30000>; + vdda-pll-max-microamp = <12000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6155_1_l17>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6155_1_s4>; + vcc-max-microamp = <800000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6155_1_l11>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1260000>; + + status = "ok"; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b8ed48c57741..8e8abca5d5e6 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ memory { device_type = "memory"; reg = <0 0 0 0>; }; aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ serial0 = &qupv3_se0_2uart; }; @@ -1045,6 +1047,122 @@ #interconnect-cells = <1>; }; + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe00>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <1>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d90000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <1>; + limit-phy-submode = <0>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + spm-level = <5>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <12>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <2097152 0>, <102400 0>, /* HS G3 RA */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <2097152 0>, <102400 0>, /* HS G3 RB */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + non-removable; + + status = "disabled"; + qos0 { + mask = <0xc0>; + vote = <67>; + }; + + qos1 { + mask = <0x3f>; + vote = <67>; + }; + }; + qmp_aop: qcom,qmp-aop@c300000 { compatible = "qcom,qmp-mbox"; reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; From 3b525e024b84b1972bac63fad8fd8915234e91fa Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 7 Sep 2020 20:18:18 +0530 Subject: [PATCH 4/4] ARM: dts: msm: add PMIC devices for SA6150 Add top level SPMI slave devices for PM6155. Also add some of the peripheral devices within the SPMI slave devices. Change-Id: Ia45d71820a70e7d244a94143a3358c7a5a98fe3b --- qcom/pm6155.dtsi | 171 ++++++++++++++++++++++++++++++++++++++++++ qcom/sa6155-pmic.dtsi | 1 + qcom/sa6155p.dtsi | 6 ++ qcom/sm6150.dtsi | 22 ++++++ 4 files changed, 200 insertions(+) create mode 100644 qcom/pm6155.dtsi diff --git a/qcom/pm6155.dtsi b/qcom/pm6155.dtsi new file mode 100644 index 000000000000..4666f0ad2626 --- /dev/null +++ b/qcom/pm6155.dtsi @@ -0,0 +1,171 @@ +#include +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm6155@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6155_1_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + }; + + pm6155_1_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm6155_1_div_clk1", + "pm6155_1_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm6155_1_rtc: qcom,pm6155_1_rtc { + compatible = "qcom,pm8941-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm6155_1_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm6155_1_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + pm6155_1_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm6155_1_sdam_2: sdam@b100 { + compatible = "qcom,spmi-sdam"; + reg = <0xb100 0x100>; + }; + + }; + + qcom,pm6155@1 { + compatible ="qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* below definitions are for the second instance of pm6155 */ + qcom,pm6155@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pm6155_2_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm6155_2_div_clk1", + "pm6155_2_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm6155_2_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,pm6155@5 { + compatible ="qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&thermal_zones { + pm6155-1-tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6155_1_tz>; + wake-capable-sensor; + + trips { + pm6155_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm6155_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/sa6155-pmic.dtsi b/qcom/sa6155-pmic.dtsi index 0f81ce8d1397..a8824ad1c37c 100644 --- a/qcom/sa6155-pmic.dtsi +++ b/qcom/sa6155-pmic.dtsi @@ -40,3 +40,4 @@ }; #include "sa6155-regulator.dtsi" +#include "pm6155.dtsi" diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index 19bc2b109289..59ff2bc74431 100644 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -7,6 +7,12 @@ qcom,msm-id = <377 0>, <380 0>; }; +/* Delete second instance of pm6155 definitions for APQ version */ +&spmi_bus { + /delete-node/ qcom,pm6155@4; + /delete-node/ qcom,pm6155@5; +}; + &apps_rsc { /delete-node/ rpmh-regulator-modemlvl; /delete-node/ rpmh-regulator-ldoc2; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 8e8abca5d5e6..3d2a49cb91a4 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1047,6 +1047,28 @@ #interconnect-cells = <1>; }; + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + thermal_zones: thermal-zones { + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem";