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EDAC/altera: Add Stratix10 OCRAM ECC support
Use the newer ECC error injection method for Arria10 and Stratix10 OCRAM. If OCRAM has already been initialized during boot and OCRAM ECC is enabled, ensure the Single Bit Error IRQ is enabled. Signed-off-by: Thor Thayer <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Cc: [email protected] Cc: [email protected] Cc: James Morse <[email protected]> Cc: linux-edac <[email protected]> Cc: [email protected] Cc: Mauro Carvalho Chehab <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected]
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1 changed files with 25 additions and 2 deletions
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@ -1223,8 +1223,31 @@ static const struct edac_device_prv_data ocramecc_data = {
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.inject_fops = &altr_edac_device_inject_fops,
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};
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static int __maybe_unused
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altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
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{
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void __iomem *base = device->base;
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int ret;
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ret = altr_check_ecc_deps(device);
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if (ret)
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return ret;
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/* Verify OCRAM has been initialized */
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if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
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(base + ALTR_A10_ECC_INITSTAT_OFST)))
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return -ENODEV;
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/* Enable IRQ on Single Bit Error */
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writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
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/* Ensure all writes complete */
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wmb();
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return 0;
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}
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static const struct edac_device_prv_data a10_ocramecc_data = {
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.setup = altr_check_ecc_deps,
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.setup = altr_check_ocram_deps_init,
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.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
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.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
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.irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
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@ -1234,7 +1257,7 @@ static const struct edac_device_prv_data a10_ocramecc_data = {
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.ue_set_mask = ALTR_A10_ECC_TDERRA,
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.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
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.ecc_irq_handler = altr_edac_a10_ecc_irq,
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.inject_fops = &altr_edac_a10_device_inject_fops,
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.inject_fops = &altr_edac_a10_device_inject2_fops,
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/*
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* OCRAM panic on uncorrectable error because sleep/resume
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* functions and FPGA contents are stored in OCRAM. Prefer
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