mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
ARM: Device-tree updates
Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
New machines:
- The new Action Semi S500 platform is added along with initial
support for the LeMaker Guitar board.
- STM32 gains support for three new boards: stm32h743-disco,
stm32f746-disco, and stm32f769-disco, along with new device
support for the existing stm32f429 boards.
- Renesas adds two new boards, the tiny GR-Peach based on RZ/A1H
with 10MB on-chip SRAM, and the iWave G20D-Q7 System-on-Module
plus board.
- On Marvell "mvebu", we gain support for the Linksys WRT3200ACM
wireless router.
- For NXP i.MX, we gain support for the Gateworks Ventana GW5600
and the Technexion Pico i.MX7D single-board computers.
- The BeagleBone Blue is added for OMAP, it's the latest variation
of the popular Beaglebone Black single-board computer.
- The Allwinner based Lichee Pi Zero and NanoPi M1 Plus boards
are added, these are the latest variations of a seemingly endless
supply of similar single-board computers.
Other updates:
- Linus Walleij improves support for the "Faraday" based SoC platforms
from various SoC makers (Moxart, Aspeed, Gemini)
- The ARM Mali GPU is now describe on Rockchips SoCs
- Mediatek MT7623 is extended significantly, making it much
more useful.
- Lots of individual updates on Renesas, OMAP, Rockchips, Broadcom,
Allwinner, Qualcomm, iMX
- For Amlogic, the clock support is extended a lot on meson8b.
- We now build the devicetree file for the Raspberry Pi 3 on 32-bit
ARM, in addition to the existing ARM64 support, to help users
wanting to run a 32-bit system on it.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM device-tree updates from Arnd Bergmann:
"Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
New machines:
- The new Action Semi S500 platform is added along with initial
support for the LeMaker Guitar board.
- STM32 gains support for three new boards: stm32h743-disco,
stm32f746-disco, and stm32f769-disco, along with new device support
for the existing stm32f429 boards.
- Renesas adds two new boards, the tiny GR-Peach based on RZ/A1H with
10MB on-chip SRAM, and the iWave G20D-Q7 System-on-Module plus
board.
- On Marvell "mvebu", we gain support for the Linksys WRT3200ACM
wireless router.
- For NXP i.MX, we gain support for the Gateworks Ventana GW5600 and
the Technexion Pico i.MX7D single-board computers.
- The BeagleBone Blue is added for OMAP, it's the latest variation of
the popular Beaglebone Black single-board computer.
- The Allwinner based Lichee Pi Zero and NanoPi M1 Plus boards are
added, these are the latest variations of a seemingly endless
supply of similar single-board computers.
Other updates:
- Linus Walleij improves support for the "Faraday" based SoC
platforms from various SoC makers (Moxart, Aspeed, Gemini)
- The ARM Mali GPU is now describe on Rockchips SoCs
- Mediatek MT7623 is extended significantly, making it much more
useful.
- Lots of individual updates on Renesas, OMAP, Rockchips, Broadcom,
Allwinner, Qualcomm, iMX
- For Amlogic, the clock support is extended a lot on meson8b.
- We now build the devicetree file for the Raspberry Pi 3 on 32-bit
ARM, in addition to the existing ARM64 support, to help users
wanting to run a 32-bit system on it"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (345 commits)
ARM: dts: socfpga: set the i2c frequency
ARM: dts: socfpga: Add second ethernet alias to VINING FPGA
ARM: dts: socfpga: Drop LED node from VINING FPGA
ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGA
ARM: dts: socfpga: Enable QSPI support on VINING FPGA
ARM: dts: socfpga: Fix the ethernet clock phandle
ARM: pxa: Use - instead of @ for DT OPP entries
ARM: dts: owl-s500: Add SPS node
ARM: dts: owl-s500: Set CPU enable-method
dt-bindings: arm: cpus: Add S500 enable-method
ARM: dts: Add Actions Semi S500 and LeMaker Guitar
dt-bindings: arm: Document Actions Semi S900
dt-bindings: timer: Document Owl timer
ARM: dts: imx6q-cm-fx6: add sdio wifi/bt nodes
dt-bindings: arm: Document Actions Semi S500
dt-bindings: Add vendor prefix for Actions Semi
ARM: dts: turris-omnia: Add generic compatible string for I2C EEPROM
ARM: dts: mvebu: add support for Linksys WRT3200ACM (Rango)
ARM: dts: armada-385-linksys: fixup button node names
ARM: dts: armada-385-linksys: group pins in pinctrl
...
This commit is contained in:
Linus Torvalds
commit
1849f800fb
424 changed files with 11527 additions and 4106 deletions
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@ -5,7 +5,6 @@
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#ifndef __GXBB_CLKC_H
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#define __GXBB_CLKC_H
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#define CLKID_CPUCLK 1
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#define CLKID_HDMI_PLL 2
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#define CLKID_FCLK_DIV2 4
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#define CLKID_FCLK_DIV3 5
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@ -13,24 +12,30 @@
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#define CLKID_GP0_PLL 9
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#define CLKID_CLK81 12
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#define CLKID_MPLL2 15
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#define CLKID_SPICC 21
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#define CLKID_I2C 22
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#define CLKID_SAR_ADC 23
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#define CLKID_RNG0 25
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#define CLKID_UART0 26
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#define CLKID_SPI 34
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#define CLKID_ETH 36
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#define CLKID_AIU_GLUE 38
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#define CLKID_IEC958 39
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#define CLKID_I2S_OUT 40
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#define CLKID_MIXER_IFACE 44
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#define CLKID_AIU 47
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#define CLKID_UART1 48
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_USB 55
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#define CLKID_HDMI_PCLK 63
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_UART2 68
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#define CLKID_SANA 69
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#define CLKID_GCLK_VENCI_INT0 77
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#define CLKID_AOCLK_GATE 80
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#define CLKID_IEC958_GATE 81
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#define CLKID_AO_I2C 93
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#define CLKID_SD_EMMC_A 94
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#define CLKID_SD_EMMC_B 95
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@ -42,5 +47,8 @@
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#define CLKID_MALI_1_SEL 103
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#define CLKID_MALI_1 105
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#define CLKID_MALI 106
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#define CLKID_CTS_AMCLK 107
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#define CLKID_CTS_MCLK_I958 110
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#define CLKID_CTS_I958 113
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#endif /* __GXBB_CLKC_H */
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@ -21,5 +21,15 @@
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#define CLKID_ZERO 13
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#define CLKID_MPEG_SEL 14
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#define CLKID_MPEG_DIV 15
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#define CLKID_SAR_ADC 23
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#define CLKID_RNG0 25
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#define CLKID_SDIO 30
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#define CLKID_ETH 36
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_USB 55
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_SANA 69
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#endif /* __MESON8B_CLKC_H */
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@ -12,8 +12,18 @@
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#define R7S72100_CLK_PLL 0
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/* MSTP2 */
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#define R7S72100_CLK_CORESIGHT 0
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/* MSTP3 */
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#define R7S72100_CLK_IEBUS 7
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#define R7S72100_CLK_IRDA 6
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#define R7S72100_CLK_LIN0 5
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#define R7S72100_CLK_LIN1 4
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#define R7S72100_CLK_MTU2 3
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#define R7S72100_CLK_CAN 2
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#define R7S72100_CLK_ADCPWR 1
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#define R7S72100_CLK_PWM 0
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/* MSTP4 */
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#define R7S72100_CLK_SCIF0 7
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@ -26,23 +36,51 @@
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#define R7S72100_CLK_SCIF7 0
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/* MSTP5 */
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#define R7S72100_CLK_SCI0 7
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#define R7S72100_CLK_SCI1 6
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#define R7S72100_CLK_SG0 5
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#define R7S72100_CLK_SG1 4
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#define R7S72100_CLK_SG2 3
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#define R7S72100_CLK_SG3 2
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#define R7S72100_CLK_OSTM0 1
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#define R7S72100_CLK_OSTM1 0
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/* MSTP6 */
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#define R7S72100_CLK_ADC 7
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#define R7S72100_CLK_CEU 6
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#define R7S72100_CLK_DOC0 5
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#define R7S72100_CLK_DOC1 4
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#define R7S72100_CLK_DRC0 3
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#define R7S72100_CLK_DRC1 2
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#define R7S72100_CLK_JCU 1
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#define R7S72100_CLK_RTC 0
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/* MSTP7 */
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#define R7S72100_CLK_VDEC0 7
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#define R7S72100_CLK_VDEC1 6
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#define R7S72100_CLK_ETHER 4
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#define R7S72100_CLK_NAND 3
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#define R7S72100_CLK_USB0 1
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#define R7S72100_CLK_USB1 0
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/* MSTP8 */
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#define R7S72100_CLK_IMR0 7
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#define R7S72100_CLK_IMR1 6
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#define R7S72100_CLK_IMRDISP 5
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#define R7S72100_CLK_MMCIF 4
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#define R7S72100_CLK_MLB 3
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#define R7S72100_CLK_ETHAVB 2
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#define R7S72100_CLK_SCUX 1
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/* MSTP9 */
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#define R7S72100_CLK_I2C0 7
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#define R7S72100_CLK_I2C1 6
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#define R7S72100_CLK_I2C2 5
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#define R7S72100_CLK_I2C3 4
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#define R7S72100_CLK_SPIBSC0 3
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#define R7S72100_CLK_SPIBSC1 2
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#define R7S72100_CLK_VDC50 1 /* and LVDS */
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#define R7S72100_CLK_VDC51 0
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/* MSTP10 */
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#define R7S72100_CLK_SPI0 7
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#define R7S72100_CLK_SPI2 5
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#define R7S72100_CLK_SPI3 4
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#define R7S72100_CLK_SPI4 3
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#define R7S72100_CLK_CDROM 2
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#define R7S72100_CLK_SPDIF 1
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#define R7S72100_CLK_RGPVG2 0
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/* MSTP11 */
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#define R7S72100_CLK_SSI0 5
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#define R7S72100_CLK_SSI1 4
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#define R7S72100_CLK_SSI2 3
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#define R7S72100_CLK_SSI3 2
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#define R7S72100_CLK_SSI4 1
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#define R7S72100_CLK_SSI5 0
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/* MSTP12 */
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#define R7S72100_CLK_SDHI00 3
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@ -57,4 +106,8 @@
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#define R7S72100_CLK_SDHI10 1
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#define R7S72100_CLK_SDHI11 0
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/* MSTP13 */
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#define R7S72100_CLK_PIX1 2
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#define R7S72100_CLK_PIX0 1
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#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
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@ -109,6 +109,7 @@
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#define R8A7791_CLK_SATA0 15
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/* MSTP9 */
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#define R8A7791_CLK_GYROADC 1
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#define R8A7791_CLK_GPIO7 4
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#define R8A7791_CLK_GPIO6 5
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#define R8A7791_CLK_GPIO5 7
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@ -61,6 +61,17 @@
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#define SCLK_MAC_TX 130
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#define SCLK_MAC_PHY 131
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#define SCLK_MAC_OUT 132
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#define SCLK_VDEC_CABAC 133
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#define SCLK_VDEC_CORE 134
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#define SCLK_RGA 135
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#define SCLK_HDCP 136
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#define SCLK_HDMI_CEC 137
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#define SCLK_CRYPTO 138
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#define SCLK_TSP 139
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#define SCLK_HSADC 140
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#define SCLK_WIFI 141
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#define SCLK_OTGPHY0 142
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#define SCLK_OTGPHY1 143
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/* dclk gates */
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#define DCLK_VOP 190
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@ -68,15 +79,32 @@
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/* aclk gates */
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#define ACLK_DMAC 194
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#define ACLK_CPU 195
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#define ACLK_VPU_PRE 196
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#define ACLK_RKVDEC_PRE 197
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#define ACLK_RGA_PRE 198
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#define ACLK_IEP_PRE 199
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#define ACLK_HDCP_PRE 200
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#define ACLK_VOP_PRE 201
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#define ACLK_VPU 202
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#define ACLK_RKVDEC 203
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#define ACLK_IEP 204
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#define ACLK_RGA 205
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#define ACLK_HDCP 206
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#define ACLK_PERI 210
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#define ACLK_VOP 211
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#define ACLK_GMAC 212
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#define ACLK_GPU 213
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/* pclk gates */
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#define PCLK_GPIO0 320
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#define PCLK_GPIO1 321
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#define PCLK_GPIO2 322
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#define PCLK_GPIO3 323
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#define PCLK_VIO_H2P 324
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#define PCLK_HDCP 325
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#define PCLK_EFUSE_1024 326
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#define PCLK_EFUSE_256 327
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#define PCLK_GRF 329
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#define PCLK_I2C0 332
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#define PCLK_I2C1 333
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@ -89,6 +117,7 @@
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#define PCLK_TSADC 344
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#define PCLK_PWM 350
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#define PCLK_TIMER 353
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#define PCLK_CPU 354
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#define PCLK_PERI 363
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#define PCLK_HDMI_CTRL 364
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#define PCLK_HDMI_PHY 365
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@ -104,6 +133,24 @@
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#define HCLK_SDMMC 456
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#define HCLK_SDIO 457
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#define HCLK_EMMC 459
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#define HCLK_CPU 460
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#define HCLK_VPU_PRE 461
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#define HCLK_RKVDEC_PRE 462
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#define HCLK_VIO_PRE 463
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#define HCLK_VPU 464
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#define HCLK_RKVDEC 465
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#define HCLK_VIO 466
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#define HCLK_RGA 467
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#define HCLK_IEP 468
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#define HCLK_VIO_H2P 469
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#define HCLK_HDCP_MMU 470
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#define HCLK_HOST0 471
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#define HCLK_HOST1 472
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#define HCLK_HOST2 473
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#define HCLK_OTG 474
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#define HCLK_TSP 475
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#define HCLK_M_CRYPTO 476
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#define HCLK_S_CRYPTO 477
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#define HCLK_PERI 478
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#define CLK_NR_CLKS (HCLK_PERI + 1)
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@ -132,6 +132,8 @@
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#define SCLK_RMII_SRC 166
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#define SCLK_PCIEPHY_REF100M 167
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#define SCLK_DDRC 168
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#define SCLK_TESTCLKOUT1 169
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#define SCLK_TESTCLKOUT2 170
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#define DCLK_VOP0 180
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#define DCLK_VOP1 181
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16
include/dt-bindings/pinctrl/r7s72100-pinctrl.h
Normal file
16
include/dt-bindings/pinctrl/r7s72100-pinctrl.h
Normal file
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@ -0,0 +1,16 @@
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/*
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* Defines macros and constants for Renesas RZ/A1 pin controller pin
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* muxing functions.
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*/
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#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
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#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
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#define RZA1_PINS_PER_PORT 16
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/*
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* Create the pin index from its bank and position numbers and store in
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* the upper 16 bits the alternate function identifier
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*/
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#define RZA1_PINMUX(b, p, f) ((b) * RZA1_PINS_PER_PORT + (p) | (f << 16))
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#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */
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Reference in a new issue