mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: SoC driver updates
These are changes for drivers that are intimately tied to some SoC and for some reason could not get merged through the respective subsystem maintainer tree. This time around, much of this is for at91, with the bulk of it being syscon and udc drivers. Also, there's: - coupled cpuidle support for Samsung Exynos4210 - Renesas 73A0 common-clk work - of/platform changes to tear down DMA mappings on device destruction - a few updates to the TI Keystone knav code -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJU4upSAAoJEIwa5zzehBx3HkUP/Rc4B1yZChNIFNfVq4dbei6w dT9WdFmxOIj2JLeXEypFBiNf1nSHmsxrZe9/IDACz2fYQOnaZZ6/786utUJP/PtC 2GDJy9cjL2Xh03We3nQp5z6J33XvpEni1t82cOpCl8wLBOQNnkjEks8UvLgi1LHW CNLcMm8JtDQ2aB/gRTjzetp9liZluESY5+Mig+loE2F/rzbMbNQDcWDDgUPyIQIS 1onL+Bad3BnGFdo/+qnkurGc81pxoKiQJty06VWFftzvIwxXhsNjrqls2+KzstAx 0lLvW1tqaDhXvUBImRM8GgfbldZslsgoFVmgESS9MpPMBNENYrkAiQNvJUnM7kd9 qHDQNq+zRNsz/k4fVvp/YUp7xEiAo4rLcFmp/dBr535jS2LNyiZnB94q+kXsin/m tiyEMx+RWxEHTEHN9WdKE61Ty1RbzOa5UTLSzOKFAkF+m2nvuQsJvb97n19coAq9 SSsj/wJgesfqrDEegphCDh1fyVxUzlAjjhTAyvPS155WvPzkbxZxuBbSqRuriRKA 2aCfVne2ELimHAr3LEPgPW2kFBcONHckOGe6MvrTX4zPHU8bb9WIeg+iGdQChnr3 nclT9jq+ZnQro5XTgUtPtadq100oEXlJbqpAzhd+cJbvgzSNbcWfcgE6kOWqd9uK oeWQWFLCdXLmXf9zCwmk =T7R2 -----END PGP SIGNATURE----- Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "These are changes for drivers that are intimately tied to some SoC and for some reason could not get merged through the respective subsystem maintainer tree. This time around, much of this is for at91, with the bulk of it being syscon and udc drivers. Also, there's: - coupled cpuidle support for Samsung Exynos4210 - Renesas 73A0 common-clk work - of/platform changes to tear down DMA mappings on device destruction - a few updates to the TI Keystone knav code" * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits) cpuidle: exynos: add coupled cpuidle support for exynos4210 ARM: EXYNOS: apply S5P_CENTRAL_SEQ_OPTION fix only when necessary soc: ti: knav_qmss_queue: change knav_range_setup_acc_irq to static soc: ti: knav_qmss_queue: makefile tweak to build as dynamic module pcmcia: at91_cf: depend on !ARCH_MULTIPLATFORM soc: ti: knav_qmss_queue: export API calls for use by user driver of/platform: teardown DMA mappings on device destruction usb: gadget: at91_udc: Allocate udc instance usb: gadget: at91_udc: Update DT binding documentation usb: gadget: at91_udc: Rework for multi-platform kernel support usb: gadget: at91_udc: Simplify probe and remove functions usb: gadget: at91_udc: Remove non-DT handling code usb: gadget: at91_udc: Document DT clocks and clock-names property usb: gadget: at91_udc: Drop uclk clock usb: gadget: at91_udc: Fix clock names mfd: syscon: Add Atmel SMC binding doc mfd: syscon: Add atmel-smc registers definition mfd: syscon: Add Atmel Matrix bus DT binding documentation mfd: syscon: Add atmel-matrix registers definition clk: shmobile: fix sparse NULL pointer warning ...
This commit is contained in:
Linus Torvalds
commit
18656782a8
28 changed files with 1570 additions and 268 deletions
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@ -5,5 +5,6 @@ obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
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obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
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obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o
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obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o
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obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o
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obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o
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218
drivers/clk/shmobile/clk-sh73a0.c
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218
drivers/clk/shmobile/clk-sh73a0.c
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@ -0,0 +1,218 @@
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/*
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* sh73a0 Core CPG Clocks
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*
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* Copyright (C) 2014 Ulrich Hecht
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/shmobile.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/spinlock.h>
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struct sh73a0_cpg {
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struct clk_onecell_data data;
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spinlock_t lock;
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void __iomem *reg;
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};
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#define CPG_FRQCRA 0x00
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#define CPG_FRQCRB 0x04
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#define CPG_SD0CKCR 0x74
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#define CPG_SD1CKCR 0x78
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#define CPG_SD2CKCR 0x7c
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#define CPG_PLLECR 0xd0
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#define CPG_PLL0CR 0xd8
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#define CPG_PLL1CR 0x28
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#define CPG_PLL2CR 0x2c
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#define CPG_PLL3CR 0xdc
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#define CPG_CKSCR 0xc0
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#define CPG_DSI0PHYCR 0x6c
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#define CPG_DSI1PHYCR 0x70
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#define CLK_ENABLE_ON_INIT BIT(0)
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struct div4_clk {
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const char *name;
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const char *parent;
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unsigned int reg;
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unsigned int shift;
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};
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static struct div4_clk div4_clks[] = {
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{ "zg", "pll0", CPG_FRQCRA, 16 },
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{ "m3", "pll1", CPG_FRQCRA, 12 },
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{ "b", "pll1", CPG_FRQCRA, 8 },
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{ "m1", "pll1", CPG_FRQCRA, 4 },
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{ "m2", "pll1", CPG_FRQCRA, 0 },
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{ "zx", "pll1", CPG_FRQCRB, 12 },
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{ "hp", "pll1", CPG_FRQCRB, 4 },
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{ NULL, NULL, 0, 0 },
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};
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static const struct clk_div_table div4_div_table[] = {
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{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
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{ 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
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{ 12, 7 }, { 0, 0 }
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};
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static const struct clk_div_table z_div_table[] = {
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/* ZSEL == 0 */
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{ 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 },
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{ 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 },
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{ 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 },
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/* ZSEL == 1 */
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{ 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 },
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{ 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 }
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};
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static struct clk * __init
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sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
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const char *name)
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{
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const struct clk_div_table *table = NULL;
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unsigned int shift, reg, width;
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const char *parent_name;
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unsigned int mult = 1;
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unsigned int div = 1;
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if (!strcmp(name, "main")) {
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/* extal1, extal1_div2, extal2, extal2_div2 */
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u32 parent_idx = (clk_readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
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parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
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div = (parent_idx & 1) + 1;
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} else if (!strncmp(name, "pll", 3)) {
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void __iomem *enable_reg = cpg->reg;
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u32 enable_bit = name[3] - '0';
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parent_name = "main";
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switch (enable_bit) {
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case 0:
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enable_reg += CPG_PLL0CR;
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break;
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case 1:
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enable_reg += CPG_PLL1CR;
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break;
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case 2:
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enable_reg += CPG_PLL2CR;
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break;
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case 3:
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enable_reg += CPG_PLL3CR;
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break;
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default:
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return ERR_PTR(-EINVAL);
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}
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if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
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mult = ((clk_readl(enable_reg) >> 24) & 0x3f) + 1;
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/* handle CFG bit for PLL1 and PLL2 */
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if (enable_bit == 1 || enable_bit == 2)
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if (clk_readl(enable_reg) & BIT(20))
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mult *= 2;
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}
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} else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
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u32 phy_no = name[3] - '0';
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void __iomem *dsi_reg = cpg->reg +
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(phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
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parent_name = phy_no ? "dsi1pck" : "dsi0pck";
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mult = __raw_readl(dsi_reg);
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if (!(mult & 0x8000))
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mult = 1;
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else
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mult = (mult & 0x3f) + 1;
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} else if (!strcmp(name, "z")) {
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parent_name = "pll0";
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table = z_div_table;
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reg = CPG_FRQCRB;
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shift = 24;
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width = 5;
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} else {
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struct div4_clk *c;
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for (c = div4_clks; c->name; c++) {
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if (!strcmp(name, c->name)) {
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parent_name = c->parent;
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table = div4_div_table;
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reg = c->reg;
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shift = c->shift;
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width = 4;
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break;
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}
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}
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if (!c->name)
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return ERR_PTR(-EINVAL);
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}
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if (!table) {
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return clk_register_fixed_factor(NULL, name, parent_name, 0,
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mult, div);
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} else {
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return clk_register_divider_table(NULL, name, parent_name, 0,
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cpg->reg + reg, shift, width, 0,
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table, &cpg->lock);
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}
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}
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static void __init sh73a0_cpg_clocks_init(struct device_node *np)
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{
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struct sh73a0_cpg *cpg;
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struct clk **clks;
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unsigned int i;
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int num_clks;
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num_clks = of_property_count_strings(np, "clock-output-names");
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if (num_clks < 0) {
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pr_err("%s: failed to count clocks\n", __func__);
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return;
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}
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cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
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clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
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if (cpg == NULL || clks == NULL) {
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/* We're leaking memory on purpose, there's no point in cleaning
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* up as the system won't boot anyway.
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*/
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return;
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}
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spin_lock_init(&cpg->lock);
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cpg->data.clks = clks;
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cpg->data.clk_num = num_clks;
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cpg->reg = of_iomap(np, 0);
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if (WARN_ON(cpg->reg == NULL))
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return;
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/* Set SDHI clocks to a known state */
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clk_writel(0x108, cpg->reg + CPG_SD0CKCR);
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clk_writel(0x108, cpg->reg + CPG_SD1CKCR);
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clk_writel(0x108, cpg->reg + CPG_SD2CKCR);
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for (i = 0; i < num_clks; ++i) {
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const char *name;
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struct clk *clk;
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of_property_read_string_index(np, "clock-output-names", i,
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&name);
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clk = sh73a0_cpg_register_clock(np, cpg, name);
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if (IS_ERR(clk))
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pr_err("%s: failed to register %s %s clock (%ld)\n",
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__func__, np->name, name, PTR_ERR(clk));
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else
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cpg->data.clks[i] = clk;
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}
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
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}
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CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",
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sh73a0_cpg_clocks_init);
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