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Merge tag 'LA.UM.9.14.r1-19500-LAHAINA.QSSI12.0' of https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/fw-api into android12-5.4-lahaina

Browse source 
"LA.UM.9.14.r1-19500-LAHAINA.QSSI12.0"

* tag 'LA.UM.9.14.r1-19500-LAHAINA.QSSI12.0' of https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/fw-api:
  fw-api: CL 17453007 - update fw common interface files
  fw-api: CL 17402406 - update fw common interface files
  fw-api: CL 17390237 - update fw common interface files
  fw-api: CL 17377924 - update fw common interface files
  fw-api: CL 17375848 - update fw common interface files
  fw-api:  Add hw headers for wkk monitor
  fw-api: CL 17350518 - update fw common interface files
  fw-api: CL 17346132 - update fw common interface files
  fw-api: CL 17328421 - update fw common interface files
  fw-api: CL 17323774 - update fw common interface files
  fw-api: CL 17313419 - update fw common interface files
  fw-api: CL 17281689 - update fw common interface files
  fw-api: CL 17270680 - update fw common interface files
  fw-api: CL 17267055 - update fw common interface files
  fw-api: CL 17265976 - update fw common interface files
  fw-api: CL 17259959 - update fw common interface files
  fw-api: CL 17257656 - update fw common interface files
  fw-api: Add Big endian support in headers
  fw-api: Add HWIO_WBM_R0_WBM_CFG_2 related macros
  fw-api: Add missing qcn9224 hdrs
  fw-api: CL 17248910 - update fw common interface files
  fw-api: CL 17246272 - update fw common interface files
  fw-api: CL 17233205 - update fw common interface files
  fw-api: CL 17220375 - update fw common interface files
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  fw-api: CL 17207899 - update fw common interface files
  fw-api: CL 17204425 - update fw common interface files
  fw-api: CL 17183819 - update fw common interface files
  fw-api: CL 17180216 - update fw common interface files
  fw-api: Add rx_reo_queue_1k.h header for qcn9224
  fw-api: kiwi: Get V2 HW header files for kiwi
  fw-api: CL 17178398 - update fw common interface files
  fw-api: CL 17148867 - update fw common interface files
  fw-api: CL 17146895 - update fw common interface files
  fw-api: CL 17114670 - update fw common interface files
  fw-api: CL 17053323 - update fw common interface files
  fw-api: CL 17052075 - update fw common interface files
  fw-api: CL 17040921 - update fw common interface files
  fw-api: Add headers for qcn9224
  fw-api: CL 17023988 - update fw common interface files
  fw-api: CL 17004158 - update fw common interface files
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  fw-api: CL 16461719 - update fw common interface files
  fw-api: kiwi: Get E3.R38 HW header files for kiwi
  fw-api: CL 16433800 - update fw common interface files
  fw-api: CL 16422098 - update fw common interface files
  fw-api: CL 16377032 - update fw common interface files
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Change-Id: I0e5fdfd6dd225cc49c81907fc8dcf17de8228dab
This commit is contained in:
Michael Bestas 2022-05-19 00:33:45 +03:00
commit 189950059d
No known key found for this signature in database
GPG key ID: CC95044519BE6669
395 changed files with 165589 additions and 1204 deletions
Download patch file Download diff file Expand all files Collapse all files

74
drivers/staging/fw-api/fw/enet.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2014, 2017, 2021 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@ -52,13 +52,13 @@ struct ethernet_hdr_t {
#define ETHERNET_MTU (ETHERNET_MAX_LEN - (ETHERNET_HDR_LEN + ETHERNET_CRC_LEN))
struct llc_snap_hdr_t {
typedef struct llc_snap_hdr_t {
A_UINT8 dsap;
A_UINT8 ssap;
A_UINT8 cntl;
A_UINT8 org_code[3];
A_UINT8 ethertype[2];
};
} LLC_SNAP_HDR;
#define LLC_SNAP_HDR_LEN (sizeof(struct llc_snap_hdr_t))
#define LLC_SNAP_HDR_OFFSET_ETHERTYPE \
@ -74,6 +74,23 @@ struct ethernet_vlan_hdr_t {
A_UINT8 ethertype[2];
};
typedef PREPACK struct _wai_hdr {
A_UINT8 version[2];
A_UINT8 type;
A_UINT8 stype;
A_UINT8 reserve[2];
A_UINT8 length[2];
A_UINT8 rxseq[2];
A_UINT8 frag_sc;
A_UINT8 more_frag;
/* followed octets of data */
} POSTPACK wai_hdr;
typedef PREPACK struct {
A_UINT16 vlan_tci;
A_UINT16 vlan_encap_p;
} POSTPACK vlan_hdr_t;
#define ETHERTYPE_IS_EAPOL_WAPI(typeorlen) \
((typeorlen) == ETHERTYPE_PAE || \
(typeorlen) == ETHERTYPE_WAI)
@ -136,16 +153,49 @@ struct ethernet_vlan_hdr_t {
#define BTEP_SNAP_ORGCODE_2 0xf8
#define IS_SNAP(_llc) ((_llc)->dsap == LLC_SNAP_LSAP && \
(_llc)->ssap == LLC_SNAP_LSAP && \
(_llc)->cntl == LLC_UI)
#define WAI_FRAME_TYPE 0X01
#define WAPI_M4_TYPE 0x0c
#define WAPI_M2_TYPE 0x09
#define IS_RFC1042(_llc) ((_llc)->org_code[0] == RFC1042_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == RFC1042_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == RFC1042_SNAP_ORGCODE_2)
#define IS_BTEP(_llc) ((_llc)->org_code[0] == BTEP_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == BTEP_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == BTEP_SNAP_ORGCODE_2)
#define ICMP_PROTOCOL 1
#define TCP_PROTOCOL 6
#define UDP_PROTOCOL 17
#define IGMP_PROTOCOL 2
#define ICMPV6_PROTOCOL 58
#define BOOTP_SERVER_PORT 67
#define BOOTP_CLIENT_PORT 68
#define MLD_QUERY 130
#define MLD_DONE 132
#define IS_EAPOL(typeorlen) \
((typeorlen) == ETHERTYPE_PAE || \
(typeorlen) == ETHERTYPE_WAI)
#define IS_SNAP(_llc) \
((_llc)->dsap == LLC_SNAP_LSAP && \
(_llc)->ssap == LLC_SNAP_LSAP && \
(_llc)->cntl == LLC_UI)
#define IS_RFC1042(_llc) \
((_llc)->org_code[0] == RFC1042_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == RFC1042_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == RFC1042_SNAP_ORGCODE_2)
#define IS_BTEP(_llc) \
((_llc)->org_code[0] == BTEP_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == BTEP_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == BTEP_SNAP_ORGCODE_2)
#define IS_MULTICAST(_hdr) (*(A_UINT8 *)(_hdr) & 0x1)
#define IS_BROADCAST(_hdr) \
((*((A_UINT8 *)(_hdr) + 0) == 0xff) && \
(*((A_UINT8 *)(_hdr) + 1) == 0xff) && \
(*((A_UINT8 *)(_hdr) + 2) == 0xff) && \
(*((A_UINT8 *)(_hdr) + 3) == 0xff) && \
(*((A_UINT8 *)(_hdr) + 4) == 0xff) && \
(*((A_UINT8 *)(_hdr) + 5) == 0xff))
#endif /* _ENET__H_ */

2027
drivers/staging/fw-api/fw/htt.h
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File diff suppressed because it is too large Load diff

64
drivers/staging/fw-api/fw/htt_ppdu_stats.h
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@ -210,10 +210,13 @@ PREPACK struct htt_tx_ppdu_stats_info {
A_UINT32 tx_ratecode: 8,
is_ampdu: 1,
ba_ack_failed: 2,
/* 0: 20 MHz
1: 40 MHz
2: 80 MHz
3: 160 MHz or 80+80 MHz */
/* bw
* 0: 20 MHz
* 1: 40 MHz
* 2: 80 MHz
* 3: 160 MHz or 80+80 MHz
* 4: 320 MHz
*/
bw: 3,
sgi: 1,
skipped_rate_ctrl: 1,
@ -424,6 +427,7 @@ enum HTT_PPDU_STATS_BW {
HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
HTT_PPDU_STATS_BANDWIDTH_DYN = 6,
HTT_PPDU_STATS_BANDWIDTH_DYN_PATTERNS = 7,
HTT_PPDU_STATS_BANDWIDTH_320MHZ = 8,
};
typedef enum HTT_PPDU_STATS_BW HTT_PPDU_STATS_BW;
@ -441,16 +445,23 @@ typedef enum HTT_PPDU_STATS_BW HTT_PPDU_STATS_BW;
} while (0)
enum HTT_PPDU_STATS_SEQ_TYPE {
HTT_SEQTYPE_UNSPECIFIED = 0,
HTT_SEQTYPE_SU = 1,
HTT_SEQTYPE_AC_MU_MIMO = 2,
HTT_SEQTYPE_AX_MU_MIMO = 3,
HTT_SEQTYPE_MU_OFDMA = 4,
HTT_SEQTYPE_UL_TRIG = 5,
HTT_SEQTYPE_BURST_BCN = 6,
HTT_SEQTYPE_UL_BSR_RESP = 7,
HTT_SEQTYPE_UL_BSR_TRIG = 8,
HTT_SEQTYPE_UL_RESP = 9,
HTT_SEQTYPE_UNSPECIFIED = 0,
HTT_SEQTYPE_SU = 1,
HTT_SEQTYPE_AC_MU_MIMO = 2,
HTT_SEQTYPE_AX_MU_MIMO = 3,
HTT_SEQTYPE_MU_OFDMA = 4,
HTT_SEQTYPE_UL_MU_OFDMA_TRIG = 5, /* new name - use this */
HTT_SEQTYPE_UL_TRIG = 5, /* deprecated old name */
HTT_SEQTYPE_BURST_BCN = 6,
HTT_SEQTYPE_UL_BSR_RESP = 7,
HTT_SEQTYPE_UL_BSR_TRIG = 8,
HTT_SEQTYPE_UL_RESP = 9,
HTT_SEQTYPE_UL_MU_MIMO_TRIG = 10,
HTT_SEQTYPE_BE_MU_MIMO = 11,
HTT_SEQTYPE_BE_MU_OFDMA = 12,
HTT_SEQTYPE_BE_UL_MU_OFDMA_TRIG = 13,
HTT_SEQTYPE_BE_UL_MU_MIMO_TRIG = 14,
HTT_SEQTYPE_BE_UL_BSR_TRIG = 15,
};
typedef enum HTT_PPDU_STATS_SEQ_TYPE HTT_PPDU_STATS_SEQ_TYPE;
@ -605,6 +616,11 @@ typedef enum HTT_PPDU_STATS_SPATIAL_REUSE HTT_PPDU_STATS_SPATIAL_REUSE;
(((_val) & HTT_PPDU_STATS_COMMON_TRIG_COOKIE_M) >> \
HTT_PPDU_STATS_COMMON_TRIG_COOKIE_S)
enum HTT_SEQ_TYPE {
WAL_PPDU_SEQ_TYPE = 0,
HTT_PPDU_SEQ_TYPE = 1,
};
typedef struct {
htt_tlv_hdr_t tlv_hdr;
@ -766,6 +782,26 @@ typedef struct {
trig_cookie_valid: 1;
};
};
/*
* htt_seq_type field is added for backward compatibility with
* pktlog decoder, host driver or any third party tool interpreting
* ppdu sequence type. If field 'htt_seq_type'is not present or is
* present but set to WAL_PPDU_SEQ_TYPE, decoder should interpret
* the seq type as WAL_TXSEND_PPDU_SEQUENCE.
* If the new field htt_seq_type is present and is set to
* HTT_PPDU_SEQ_TYPE then decoder should interpret the seq type as
* HTT_PPDU_STATS_SEQ_TYPE. htt_seq_type field will be set to
* HTT_PPDU_SEQ_TYPE in firmware versions where this field is
* defined.
*/
union {
A_UINT32 reserved__htt_seq_type;
struct {
A_UINT32 htt_seq_type: 1,
reserved3: 31;
};
};
} htt_ppdu_stats_common_tlv;
#define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff

2945
drivers/staging/fw-api/fw/htt_stats.h
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File diff suppressed because it is too large Load diff

70
drivers/staging/fw-api/fw/wlan_defs.h
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@ -1279,15 +1279,18 @@ struct wlan_dbg_tidq_stats {
};
typedef enum {
WLAN_DBG_DATA_STALL_NONE = 0,
WLAN_DBG_DATA_STALL_VDEV_PAUSE, /* 1 */
WLAN_DBG_DATA_STALL_HWSCHED_CMD_FILTER, /* 2 */
WLAN_DBG_DATA_STALL_HWSCHED_CMD_FLUSH, /* 3 */
WLAN_DBG_DATA_STALL_RX_REFILL_FAILED, /* 4 */
WLAN_DBG_DATA_STALL_RX_FCS_LEN_ERROR, /* 5 */
WLAN_DBG_DATA_STALL_MAC_WDOG_ERRORS, /* 6 */ /* Mac watch dog */
WLAN_DBG_DATA_STALL_PHY_BB_WDOG_ERROR, /* 7 */ /* PHY watch dog */
WLAN_DBG_DATA_STALL_POST_TIM_NO_TXRX_ERROR, /* 8 */
WLAN_DBG_DATA_STALL_NONE = 0,
WLAN_DBG_DATA_STALL_VDEV_PAUSE = 1,
WLAN_DBG_DATA_STALL_HWSCHED_CMD_FILTER = 2,
WLAN_DBG_DATA_STALL_HWSCHED_CMD_FLUSH = 3,
WLAN_DBG_DATA_STALL_RX_REFILL_FAILED = 4,
WLAN_DBG_DATA_STALL_RX_FCS_LEN_ERROR = 5,
WLAN_DBG_DATA_STALL_MAC_WDOG_ERRORS = 6, /* Mac watch dog */
WLAN_DBG_DATA_STALL_PHY_BB_WDOG_ERROR = 7, /* PHY watch dog */
WLAN_DBG_DATA_STALL_POST_TIM_NO_TXRX_ERROR = 8,
WLAN_DBG_DATA_STALL_CONSECUTIVE_NON_FLUSH = 9,
WLAN_DBG_DATA_STALL_CONSECUTIVE_NOACK = 10,
WLAN_DBG_DATA_STALL_CONSECUTIVE_LT_EXPIRY = 11,
WLAN_DBG_DATA_STALL_MAX,
} wlan_dbg_data_stall_type_e;
@ -1363,6 +1366,8 @@ typedef enum {
MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK,
MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO,
MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM,
MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO,
MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO,
} MLO_SHMEM_TLV_TAG_ID;
/** Helper macro for params GET/SET of mgmt_rx_reo_snapshot */
@ -1539,6 +1544,52 @@ typedef struct {
A_COMPILE_TIME_ASSERT(check_mlo_glb_link_info_8byte_size_quantum,
(((sizeof(mlo_glb_link_info) % sizeof(A_UINT64) == 0x0))));
typedef enum {
MLO_SHMEM_CRASH_PARTNER_CHIPS = 1,
} MLO_SHMEM_CHIP_CRASH_REASON;
/* glb link info structures used for scratchpad memory (crash and recovery) */
typedef struct {
/* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO */
A_UINT32 tlv_header;
/**
* crash reason, takes value in enum MLO_SHMEM_CHIP_CRASH_REASON
*/
A_UINT32 crash_reason;
} mlo_glb_per_chip_crash_info;
A_COMPILE_TIME_ASSERT(check_mlo_glb_per_chip_crash_info,
(((sizeof(mlo_glb_per_chip_crash_info) % sizeof(A_UINT64) == 0x0))));
/** Helper macro for params GET/SET of mlo_glb_chip_crash_info */
#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 0, 2)
#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 0, 2, value)
#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 2, 3)
#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 2, 3, value)
typedef struct {
/* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO */
A_UINT32 tlv_header;
/**
* chip_info
*
* [1:0]: no_of_chips
* [4:2]: valid_chip_bmap
* [31:6]: reserved
*/
A_UINT32 chip_info;
/* This TLV is followed by array of mlo_glb_per_chip_crash_info:
* mlo_glb_per_chip_crash_info will have mutiple instances equal to num of partner chips
* received by no_of_chips
* mlo_glb_per_chip_crash_info per_chip_crash_info[];
*/
} mlo_glb_chip_crash_info;
A_COMPILE_TIME_ASSERT(check_mlo_glb_chip_crash_info,
(((sizeof(mlo_glb_chip_crash_info) % sizeof(A_UINT64) == 0x0))));
/** Helper macro for params GET/SET of mlo_glb_h_shmem */
#define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_GET(major_minor_version) MLO_SHMEM_GET_BITS(major_minor_version, 0, 16)
#define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_SET(major_minor_version, value) MLO_SHMEM_SET_BITS(major_minor_version, 0, 16, value)
@ -1560,6 +1611,7 @@ typedef struct {
/* This TLV is followed by TLVs
* mlo_glb_rx_reo_snapshot_info reo_snapshot;
* mlo_glb_link_info glb_info;
* mlo_glb_chip_crash_info crash_info;
*/
} mlo_glb_h_shmem;

2
drivers/staging/fw-api/fw/wlan_module_ids.h
View file

@ -121,6 +121,8 @@ typedef enum {
WLAN_MODULE_MLO_MGR, /* 0x57 */ /* MLO manager */
WLAN_MODULE_PEER_INIT, /* 0x58 */ /* peer init connection handling */
WLAN_MODULE_STA_MLO_PS, /* 0x59 */ /* MLO PS manager */
WLAN_MODULE_MLO_SYNC_SEQ_NUM, /* 0x5a */ /* sync seq num after rm MPDU */
WLAN_MODULE_PLCMGR, /* 0x5b */ /* Policy Manager */
WLAN_MODULE_ID_MAX,

1
drivers/staging/fw-api/fw/wmi.h
View file

@ -145,6 +145,7 @@ typedef enum {
GROUP_USAGE = 0x01,
TX_USAGE = 0x02, /* default Tx Key - Static WEP only */
PMK_USAGE = 0x04, /* PMK cache */
LTF_USAGE = 0x08, /* LTF key seed */
} KEY_USAGE;
/*
* List of Events (target to host)

34
drivers/staging/fw-api/fw/wmi_services.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2011-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@ -548,7 +549,38 @@ typedef enum {
WMI_SERVICE_DYN_NSS_MASK_SUPPORT = 303, /* Indicates FW support for DYN NSS feature */
WMI_SERVICE_HW_MODE_POLICY_OFFLOAD_SUPPORT = 304, /* FW supports HW mode selection offload */
WMI_SERVICE_THERMAL_THROT_STATS_TEMP_RANGE_SUPPORT = 305, /* FW supports thermal throttling temperature range stats based on wmi_thermal_stats_action */
/*
* Indicates FW support for spatial reuse enhancements.
* Below commands are added for the enhancements:
* WMI_PDEV_PARAM_OBSS_MIN_DURATION_CHECK_FOR_SR,
* WMI_PDEV_PARAM_TRUNCATE_SR,
* WMI_PDEV_PARAM_CTRL_FRAME_OBSS_PD_THRESHOLD
*/
WMI_SERVICE_SPATIAL_REUSE_ENHANCEMENT_SUPPORT = 306,
WMI_SERVICE_MU_SNIF = 307, /* FW support MU sniffer */
WMI_SERVICE_ICMP_OFFLOAD = 308, /* FW supports ping offload during APPS suspend */
WMI_SERVICE_RTSCTS_FOR_UNICAST_MGMT_SUPPORT = 309, /* Indicates FW support RTSCTS for unicast management */
WMI_SERVICE_DYNAMIC_VDEV_MAC_ADDR_UPDATE_SUPPORT = 310, /* FW supports dynamic vdev mac address updating */
WMI_SERVICE_SAWF_LEVEL0 = 311, /* FW supports WMI_SAWF_SVC_CLASS CFG_CMD + DISABLE_CMD msgs */
WMI_SERVICE_RTT_11AZ_NTB_SUPPORT = 312, /* FW support for 11AZ non trigger based ranging */
WMI_SERVICE_RTT_11AZ_TB_SUPPORT = 313, /* FW support for 11AZ trigger based ranging */
WMI_SERVICE_RTT_11AZ_MAC_SEC_SUPPORT = 314, /* FW support for 11AZ secure FTM */
WMI_SERVICE_RTT_11AZ_MAC_PHY_SEC_SUPPORT = 315, /* FW support for 11AZ secure LTF + FTM */
WMI_SERVICE_SPECTRAL_SESSION_INFO_SUPPORT = 316, /* Information corresponding to each Spectral scan session will be sent by the FW before the reports corresponding to that session are sent */
WMI_SERVICE_PDEV_RATE_CONFIG_SUPPORT = 317, /* Support rate configurations per PDEV */
WMI_SERVICE_MLO_STA_NAN_NDI_SUPPORT = 318, /* FW support for NAN and NDP support with MLO STA */
WMI_SERVICE_PROBE_ALL_BW_SUPPORT = 319, /* FW support to probe on higher BW even if the probe fails on lower BW - IOT issue */
WMI_SERVICE_PKTLOG_DECODE_INFO_SUPPORT = 320, /* FW supports embedding Pktlog decode info in the Pktlog trace file level header */
WMI_SERVICE_PNO_SCAN_CONFIG_PER_CHANNEL = 321, /* Indicates that FW supports per channel configuration support in the PNO scan start command */
WMI_SERVICE_MULTIPLE_PEER_GROUP_CMD_SUPPORT = 322, /* FW support for multiple peer group command */
WMI_SERVICE_AFC_RESET_SUPPORT = 323, /* Indicates FW supports AFC reset */
WMI_SERVICE_FP_PHY_ERR_FILTER_SUPPORT = 324, /* FW supports monitor ring configurations for filtering in PHY error packets */
WMI_IS_RADAR_FOUND_CHAN_FREQ_IS_CENTER_FREQ = 325, /* FW Supporting radar event on the actual center frequency radar was detected */
WMI_SERVICE_BIOS_SAR_SUPPORT = 326, /* FW support for SAR parameter stored in BIOS */
WMI_SERVICE_REO_QREF_SUPPORT = 327, /* FW supports REO QREF */
WMI_SERVICE_DELETE_ALL_PEER_BITMAP_SUPPORT = 328, /* target supports cmd to delete all specific peer type within a vdev */
WMI_SERVICE_PN_REPLAY_CHECK_SUPPORT = 329, /* FW support to check RX mgmt frames has invalid PN in packets */
WMI_SERVICE_COMBINED_SET_PARAM_SUPPORT = 330, /* FW Supporting set param cmd combined for multiple params */
WMI_MAX_EXT2_SERVICE

299
drivers/staging/fw-api/fw/wmi_tlv_defs.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2010-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@ -1198,6 +1199,61 @@ typedef enum {
WMITLV_TAG_STRUC_wmi_thermal_stats_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_thermal_throt_temp_range_stats,
WMITLV_TAG_STRUC_wmi_ctrl_path_awgn_stats_struct,
WMITLV_TAG_STRUC_wmi_htt_msdu_idx_to_htt_msdu_qtype,
WMITLV_TAG_STRUC_wmi_pdev_set_bios_interface_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_vdev_set_mu_snif_cmd_param,
WMITLV_TAG_STRUC_wmi_ctrl_path_btcoex_stats_struct,
WMITLV_TAG_STRUC_wmi_icmp_offload_fixed_param,
WMITLV_TAG_STRUC_WMI_IPV6_ADDR,
WMITLV_TAG_STRUC_wmi_dbs_or_sbs_cap_ext,
WMITLV_TAG_STRUC_wmi_roam_set_param_cmd_fixed_param,
WMITLV_TAG_STRUC_cust_bdf_version_capabilities,
WMITLV_TAG_STRUC_wmi_pdev_fips_extend_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_fips_extend_cmd_init_params,
WMITLV_TAG_STRUC_wmi_pdev_fips_extend_event_fixed_param,
WMITLV_TAG_STRUC_wmi_pdev_fips_mode_set_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_vdev_update_mac_addr_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_vdev_update_mac_addr_conf_event_fixed_param,
WMITLV_TAG_STRUC_wmi_mlo_set_active_link_number_param,
WMITLV_TAG_STRUC_wmi_sawf_svc_class_cfg_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_sawf_svc_class_disable_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_roam_frame_event_fixed_param,
WMITLV_TAG_STRUC_wmi_debug_mesg_fw_cal_failure_param,
WMITLV_TAG_STRUC_wmi_quiet_event_fixed_param,
WMITLV_TAG_STRUC_wmi_ctrl_path_bmiss_stats_struct,
WMITLV_TAG_STRUC_wmi_resmgr_chan_time_quota_changed_event_fixed_param,
WMITLV_TAG_STRUC_wmi_resmgr_chan_time_quota_tlv,
WMITLV_TAG_STRUC_wmi_sw_cal_ver_cap,
WMITLV_TAG_STRUC_wmi_soc_tqm_reset_enable_disable_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_pdev_pktlog_decode_info_evt_fixed_param,
WMITLV_TAG_STRUC_wmi_spectral_scan_bw_capabilities,
WMITLV_TAG_STRUC_wmi_spectral_fft_size_capabilities,
WMITLV_TAG_STRUC_wmi_pdev_sscan_chan_info,
WMITLV_TAG_STRUC_wmi_pdev_sscan_per_detector_info,
WMITLV_TAG_STRUC_wmi_ctrl_path_odd_addr_read_struct,
WMITLV_TAG_STRUC_wmi_vdev_multiple_peer_group_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_vdev_set_ltf_key_seed_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_create_req_event_fixed_param,
WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_create_req_param,
WMITLV_TAG_STRUC_wmi_rtt_pasn_auth_status_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_rtt_pasn_auth_status_param,
WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_delete_event_fixed_param,
WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_delete_param,
WMITLV_TAG_STRUC_wmi_rtt_pasn_deauth_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_tx_send_params_ext,
WMITLV_TAG_STRUC_wmi_mgmt_rx_params_ext,
WMITLV_TAG_STRUC_wmi_partner_link_stats,
WMITLV_TAG_STRUC_wmi_regulatory_chan_priority_struct,
WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_fixed_param,
WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_params_info,
WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_temp_offset_info,
WMITLV_TAG_STRUC_wmi_ctrl_path_afc_stats_struct,
WMITLV_TAG_STRUC_wmi_frame_pn_params,
WMITLV_TAG_STRUC_wmi_peer_rx_pn_request_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_peer_rx_pn_response_event_fixed_param,
WMITLV_TAG_STRUC_wmi_vdev_pn_mgmt_rx_filter_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_set_multiple_pdev_vdev_param_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_set_param_info,
} WMITLV_TAG_ID;
/*
@ -1672,6 +1728,23 @@ typedef enum {
OP(WMI_VDEV_ENABLE_DISABLE_INTRA_BSS_CMDID) \
OP(WMI_PEER_ENABLE_DISABLE_INTRA_BSS_CMDID) \
OP(WMI_REQUEST_THERMAL_STATS_CMDID) \
OP(WMI_PDEV_SET_BIOS_INTERFACE_CMDID) \
OP(WMI_VDEV_SET_MU_SNIF_CMDID) \
OP(WMI_VDEV_ICMP_OFFLOAD_CMDID) \
OP(WMI_ROAM_SET_PARAM_CMDID) \
OP(WMI_PDEV_FIPS_EXTEND_CMDID) \
OP(WMI_PDEV_FIPS_MODE_SET_CMDID) \
OP(WMI_VDEV_UPDATE_MAC_ADDR_CMDID) \
OP(WMI_SAWF_SVC_CLASS_CFG_CMDID) \
OP(WMI_SAWF_SVC_CLASS_DISABLE_CMDID) \
OP(WMI_SOC_TQM_RESET_ENABLE_DISABLE_CMDID) \
OP(WMI_VDEV_MULTIPLE_PEER_GROUP_CMDID) \
OP(WMI_VDEV_SET_LTF_KEY_SEED_CMDID) \
OP(WMI_RTT_PASN_AUTH_STATUS_CMD) \
OP(WMI_RTT_PASN_DEAUTH_CMD) \
OP(WMI_PEER_RX_PN_REQUEST_CMDID) \
OP(WMI_VDEV_PN_MGMT_RX_FILTER_CMDID) \
OP(WMI_SET_MULTIPLE_PDEV_VDEV_PARAM_CMDID) \
/* add new CMD_LIST elements above this line */
@ -1944,6 +2017,17 @@ typedef enum {
OP(WMI_AFC_EVENTID) \
OP(WMI_TWT_ACK_EVENTID) \
OP(WMI_PDEV_AOA_PHASEDELTA_EVENTID) \
OP(WMI_PDEV_FIPS_EXTEND_EVENTID) \
OP(WMI_VDEV_UPDATE_MAC_ADDR_CONF_EVENTID) \
OP(WMI_ROAM_FRAME_EVENTID) \
OP(WMI_QUIET_HANDLING_EVENTID) \
OP(WMI_RESMGR_CHAN_TIME_QUOTA_CHANGED_EVENTID) \
OP(WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID) \
OP(WMI_SPECTRAL_CAPABILITIES_EVENTID) \
OP(WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID) \
OP(WMI_RTT_PASN_PEER_DELETE_EVENTID) \
OP(WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID) \
OP(WMI_PEER_RX_PN_RESPONSE_EVENTID) \
/* add new EVT_LIST elements above this line */
@ -1955,7 +2039,8 @@ typedef enum {
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_resource_config, wmi_resource_config, resource_config, WMITLV_SIZE_FIX)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wlan_host_memory_chunk, host_mem_chunks, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_cmd_fixed_param, wmi_pdev_set_hw_mode_cmd_fixed_param, hw_mode, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_band_to_mac, band_to_mac, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_band_to_mac, band_to_mac, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_htt_msdu_idx_to_htt_msdu_qtype, htt_msdu_idx_to_qtype_map, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_INIT_CMDID);
@ -2402,6 +2487,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_FD_TMPL_CMDID);
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_INSTALL_KEY_CMDID);
/* VDEV set LTF key seed Cmd */
#define WMITLV_TABLE_WMI_VDEV_SET_LTF_KEY_SEED_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_ltf_key_seed_cmd_fixed_param, wmi_vdev_set_ltf_key_seed_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_seed, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_LTF_KEY_SEED_CMDID);
/* VDEV WNM SLEEP MODE Cmd */
#define WMITLV_TABLE_WMI_VDEV_WNM_SLEEPMODE_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param, WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@ -2580,6 +2671,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_STATS_CMDID);
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TX_PN_REQUEST_CMDID);
/* PN Request Cmd */
#define WMITLV_TABLE_WMI_PEER_RX_PN_REQUEST_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_rx_pn_request_cmd_fixed_param, wmi_peer_rx_pn_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_RX_PN_REQUEST_CMDID);
/* Request for memory dump stats Cmd */
#define WMITLV_TABLE_WMI_GET_FW_MEM_DUMP_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_fw_mem_dump_fixed_param, wmi_get_fw_mem_dump_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@ -2799,7 +2896,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_TX_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_tx_send_cmd_fixed_param, wmi_mgmt_tx_send_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tx_send_params, wmi_tx_send_params, tx_send_params, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_tx_send_params, mlo_tx_send_params, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_tx_send_params, mlo_tx_send_params, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tx_send_params_ext, tx_send_params_ext, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_TX_SEND_CMDID);
@ -2969,7 +3067,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_MCAST_GROUP_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_score_delta_param, roam_score_delta_param_list, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_cnd_min_rssi_param, roam_cnd_min_rssi_param_list, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_cnd_vendor_scoring_param, roam_cnd_vendor_scoring_param, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_owe_ap_profile, owe_ap_profile, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_owe_ap_profile, owe_ap_profile, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, authmode_list, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_AP_PROFILE);
@ -3172,6 +3271,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DOWN_CMDID);
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_PARAM_CMDID);
/* Update vdev mac address */
#define WMITLV_TABLE_WMI_VDEV_UPDATE_MAC_ADDR_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_update_mac_addr_cmd_fixed_param, wmi_vdev_update_mac_addr_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UPDATE_MAC_ADDR_CMDID);
/* Pdev suspend Cmd */
#define WMITLV_TABLE_WMI_PDEV_SUSPEND_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_suspend_cmd_fixed_param, wmi_pdev_suspend_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@ -4035,6 +4139,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, geo_offset, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID);
/* Set bios interface table */
#define WMITLV_TABLE_WMI_PDEV_SET_BIOS_INTERFACE_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_bios_interface_cmd_fixed_param, wmi_pdev_set_bios_interface_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, parameters, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_BIOS_INTERFACE_CMDID);
/* Override the array gain table */
#define WMITLV_TABLE_WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_mimogain_table_cmd_fixed_param, wmi_pdev_set_mimogain_table_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@ -4047,6 +4157,18 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FIPS_CMDID);
/* FIPS extended cmd */
#define WMITLV_TABLE_WMI_PDEV_FIPS_EXTEND_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_fips_extend_cmd_fixed_param, wmi_pdev_fips_extend_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_fips_extend_cmd_init_params, cmd_params, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FIPS_EXTEND_CMDID);
/* FIPS mode set cmd */
#define WMITLV_TABLE_WMI_PDEV_FIPS_MODE_SET_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_fips_mode_set_cmd_fixed_param, wmi_pdev_fips_mode_set_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FIPS_MODE_SET_CMDID);
/* get CCK ANI level */
#define WMITLV_TABLE_WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_ani_cck_config_cmd_fixed_param, wmi_pdev_get_ani_cck_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@ -4081,6 +4203,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_DSCP_TID_MAP_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_filter_nrp_config_cmd_fixed_param, wmi_vdev_filter_nrp_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID);
/* Configure filter for PN Rx Pkt indication which pkts need to be forwarded to host */
#define WMITLV_TABLE_WMI_VDEV_PN_MGMT_RX_FILTER_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_pn_mgmt_rx_filter_cmd_fixed_param, wmi_vdev_pn_mgmt_rx_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PN_MGMT_RX_FILTER_CMDID);
/* update a wds (4 address) entry */
#define WMITLV_TABLE_WMI_PEER_UPDATE_WDS_ENTRY_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_update_wds_entry_cmd_fixed_param, wmi_peer_update_wds_entry_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@ -4239,7 +4366,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_PEER_STATS_INFO_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, pdev_ids, WMITLV_SIZE_VAR)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids, WMITLV_SIZE_VAR)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, mac_addr_list, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, twt_dialog_ids, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, twt_dialog_ids, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_addr_read_args, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_CTRL_PATH_STATS_CMDID);
/* Host sets the current country code */
@ -4765,12 +4893,22 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_IGMP_OFFLOAD_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_rx_reo_filter_configuration_cmd_fixed_param, wmi_mgmt_rx_reo_filter_configuration_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_REO_FILTER_CONFIGURATION_CMDID);
/* Multiple vdev set param cmd */
/* Multiple vdev set param cmd:
* Set one parameter for multiple vdevs at once.
*/
#define WMITLV_TABLE_WMI_PDEV_MULTIPLE_VDEV_SET_PARAM_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_multiple_vdev_set_param_cmd_fixed_param, wmi_pdev_multiple_vdev_set_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTIPLE_VDEV_SET_PARAM_CMDID);
/* Vdev/Pdev set Param:
* Set multiple parameters at once for one pdev or vdev.
*/
#define WMITLV_TABLE_WMI_SET_MULTIPLE_PDEV_VDEV_PARAM_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_multiple_pdev_vdev_param_cmd_fixed_param, wmi_set_multiple_pdev_vdev_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_set_param_info, param_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_SET_MULTIPLE_PDEV_VDEV_PARAM_CMDID);
/* Configure MEC AGING TIMER */
#define WMITLV_TABLE_WMI_PDEV_MEC_AGING_TIMER_CONFIG_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_mec_aging_timer_config_cmd_fixed_param, wmi_pdev_mec_aging_timer_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@ -4795,6 +4933,53 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ENABLE_DISABLE_INTRA_BSS_CMDID);
WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_thermal_stats_cmd_fixed_param, wmi_thermal_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_THERMAL_STATS_CMDID);
/** WMI cmd used to set mu sniffer param */
#define WMITLV_TABLE_WMI_VDEV_SET_MU_SNIF_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_mu_snif_cmd_param, wmi_vdev_set_mu_snif_cmd_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, aids, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_MU_SNIF_CMDID);
/* WMI CMD used to offload ICMP ping packets */
#define WMITLV_TABLE_WMI_VDEV_ICMP_OFFLOAD_CMDID(id,op,buf,len) \
WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_icmp_offload_fixed_param, wmi_icmp_offload_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, WMI_IPV6_ADDR, ipv6_addr, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ICMP_OFFLOAD_CMDID);
/* Roam set param Cmd */
#define WMITLV_TABLE_WMI_ROAM_SET_PARAM_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_set_param_cmd_fixed_param, wmi_roam_set_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SET_PARAM_CMDID);
#define WMITLV_TABLE_WMI_SAWF_SVC_CLASS_CFG_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sawf_svc_class_cfg_cmd_fixed_param, wmi_sawf_svc_class_cfg_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_SAWF_SVC_CLASS_CFG_CMDID);
#define WMITLV_TABLE_WMI_SAWF_SVC_CLASS_DISABLE_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sawf_svc_class_disable_cmd_fixed_param, wmi_sawf_svc_class_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_SAWF_SVC_CLASS_DISABLE_CMDID);
/* WMI CMD used to Enable/Disable Cmd for TQM reset feature */
#define WMITLV_TABLE_WMI_SOC_TQM_RESET_ENABLE_DISABLE_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_tqm_reset_enable_disable_cmd_fixed_param, wmi_soc_tqm_reset_enable_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_SOC_TQM_RESET_ENABLE_DISABLE_CMDID);
/* WMI CMD used to operate command on multiple peers */
#define WMITLV_TABLE_WMI_VDEV_MULTIPLE_PEER_GROUP_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_multiple_peer_group_cmd_fixed_param, wmi_vdev_multiple_peer_group_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, wds_macaddr, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_MULTIPLE_PEER_GROUP_CMDID);
/* RTT 11az PASN authentication status cmd */
#define WMITLV_TABLE_WMI_RTT_PASN_AUTH_STATUS_CMD(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_pasn_auth_status_cmd_fixed_param, wmi_rtt_pasn_auth_status_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_pasn_auth_status_param, pasn_auth_status_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PASN_AUTH_STATUS_CMD);
/* RTT 11az PASN deauthentication cmd */
#define WMITLV_TABLE_WMI_RTT_PASN_DEAUTH_CMD(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_pasn_deauth_cmd_fixed_param, wmi_rtt_pasn_deauth_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PASN_DEAUTH_CMD);
/************************** TLV definitions of WMI events *******************************/
@ -4844,9 +5029,18 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_HAL_REG_CAPABILITIES_EXT2, hal_reg_caps, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_capabilities, wmi_nan_capabilities, nan_cap, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_SCAN_RADIO_CAPABILITIES_EXT2, wmi_scan_radio_caps, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_twt_caps_params, twt_caps, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_twt_caps_params, twt_caps, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_htt_msdu_idx_to_htt_msdu_qtype, htt_msdu_idx_to_qtype_map, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbs_or_sbs_cap_ext, dbs_or_sbs_cap_ext, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cust_bdf_version_capabilities, cust_bdf_version_capabilities, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sw_cal_ver_cap, sw_cal_ver_cap, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
#define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_spectral_scan_bw_capabilities, sscan_bw_caps, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_spectral_fft_size_capabilities, fft_size_caps, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_SPECTRAL_CAPABILITIES_EVENTID);
#define WMITLV_TABLE_WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_rf_characterization_info_event_fixed_param, wmi_chan_rf_characterization_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_CHAN_RF_CHARACTERIZATION_INFO, wmi_chan_rf_characterization_info, WMITLV_SIZE_VAR)
@ -4963,10 +5157,17 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UPDATE_CTLTABLE_EVENTID);
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_TX_POWER_EVENTID);
/* Channel Info Event */
#define WMITLV_TABLE_WMI_CHAN_INFO_EVENTID(id,op,buf,len) \
#define WMITLV_TABLE_WMI_CHAN_INFO_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, wmi_chan_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_CHAN_INFO_EVENTID);
/* RSSI dB to dBm conversion params info event to host */
#define WMITLV_TABLE_WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rssi_dbm_conversion_fixed_param, wmi_rssi_dbm_conversion_params_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rssi_dbm_conversion_params_info, rssi_dbm_conversion_params, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rssi_dbm_conversion_temp_offset_info, rssi_temp_offset, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID);
/* Phy Error Event */
#define WMITLV_TABLE_WMI_PHYERR_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_comb_phyerr_rx_hdr, wmi_comb_phyerr_rx_hdr, hdr, WMITLV_SIZE_FIX) \
@ -5040,7 +5241,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STA_KICKOUT_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_rx_hdr, wmi_mgmt_rx_hdr, hdr, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rssi_ctl_ext, rssi_ctl_ext, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_rx_reo_params, wmi_mgmt_rx_reo_params, reo_params, WMITLV_SIZE_FIX)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_rx_reo_params, wmi_mgmt_rx_reo_params, reo_params, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mgmt_rx_params_ext, mgmt_rx_params_ext, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_frame_pn_params, pn_params, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID);
/* Management Rx FW Consumed Event */
@ -5119,9 +5322,15 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, reassoc_req_frame, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_FRAME_EVENTID);
/* Roam frame Event */
#define WMITLV_TABLE_WMI_ROAM_FRAME_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_frame_event_fixed_param, wmi_roam_frame_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, frame, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_FRAME_EVENTID);
/* WOW Wakeup Host Event */
/* NOTE: Make sure wow_bitmap_info can be zero or one elements only */
#define WMITLV_TABLE_WMI_WOW_WAKEUP_HOST_EVENTID(id,op,buf,len) \
#define WMITLV_TABLE_WMI_WOW_WAKEUP_HOST_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WOW_EVENT_INFO_fixed_param, WOW_EVENT_INFO_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_EVENT_INFO_SECTION_BITMAP, wow_bitmap_info, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, wow_packet_buffer, WMITLV_SIZE_VAR) \
@ -5195,7 +5404,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DEBUG_MESG_EVENTID);
#define WMITLV_TABLE_WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID(id,op,buf,len)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_debug_mesg_flush_complete_fixed_param, wmi_debug_mesg_flush_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_debug_mesg_fw_data_stall_param, data_stall, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_debug_mesg_fw_data_stall_param, data_stall, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_debug_mesg_fw_cal_failure_param, cal_failure, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID);
#define WMITLV_TABLE_WMI_RSSI_BREACH_EVENTID(id,op,buf,len)\
@ -5333,6 +5543,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_UPDATE_STATS_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tx_pn_response_event_fixed_param, wmi_peer_tx_pn_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TX_PN_RESPONSE_EVENTID);
#define WMITLV_TABLE_WMI_PEER_RX_PN_RESPONSE_EVENTID(id,op,buf,len)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_rx_pn_response_event_fixed_param, wmi_peer_rx_pn_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_RX_PN_RESPONSE_EVENTID);
/* For vdev based ht/vht info upload*/
#define WMITLV_TABLE_WMI_UPDATE_VDEV_RATE_STATS_EVENTID(id,op,buf,len)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_rate_stats_event_fixed_param, wmi_vdev_rate_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@ -5602,7 +5816,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NDP_END_RSP_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_scid, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_transport_ip_param, wmi_ndp_transport_ip_param, ndp_transport_ip_param, WMITLV_SIZE_FIX)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_transport_ip_param, wmi_ndp_transport_ip_param, ndp_transport_ip_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, service_id, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_NDP_INDICATION_EVENTID);
/** NDP confirm event
@ -5672,10 +5887,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_DATA_CONTAINER_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_estimated_linkspeed_event_fixed_param, wmi_peer_estimated_linkspeed_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ESTIMATED_LINKSPEED_EVENTID);
/* NAN Response/Indication Event */
#define WMITLV_TABLE_WMI_STATS_EXT_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_stats_ext_event_fixed_param, wmi_stats_ext_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_stats, partner_link_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, partner_link_data, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_STATS_EXT_EVENTID);
#define WMITLV_TABLE_WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID(id,op,buf,len) \
@ -5885,7 +6101,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REG_CHAN_LIST_CC_EVENTID);
/* Ext regulatory channel list of current country code */
#define WMITLV_TABLE_WMI_REG_CHAN_LIST_CC_EXT_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_reg_chan_list_cc_event_ext_fixed_param, wmi_reg_chan_list_cc_event_ext_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_rule_ext_struct, reg_rule_array, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_rule_ext_struct, reg_rule_array, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_chan_priority_struct, reg_chan_priority, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_REG_CHAN_LIST_CC_EXT_EVENTID);
/* WMI AFC info event */
@ -5904,6 +6121,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AFC_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FIPS_EVENTID);
/* FIPS event */
#define WMITLV_TABLE_WMI_PDEV_FIPS_EXTEND_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_fips_extend_event_fixed_param, wmi_pdev_fips_extend_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FIPS_EXTEND_EVENTID);
#define WMITLV_TABLE_WMI_PDEV_CHANNEL_HOPPING_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_channel_hopping_event_fixed_param, wmi_pdev_channel_hopping_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CHANNEL_HOPPING_EVENTID);
@ -6156,7 +6379,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_twt_stats_struct, ctrl_path_twt_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_calibration_stats_struct, ctrl_path_calibration_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_dfs_channel_stats_struct, ctrl_path_dfs_channel_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_awgn_stats_struct, ctrl_path_awgn_stats, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_awgn_stats_struct, ctrl_path_awgn_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_btcoex_stats_struct, ctrl_path_btcoex_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_bmiss_stats_struct, ctrl_path_bmiss_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_odd_addr_read_struct, ctrl_path_odd_addr_read, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_afc_stats_struct, ctrl_path_afc_stats, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID);
#define WMITLV_TABLE_WMI_RADIO_CHAN_STATS_EVENTID(id, op, buf, len) \
@ -6392,7 +6619,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AUDIO_AGGR_SCHED_METHOD_EVENTID);
/* Send sscan fw params to host */
#define WMITLV_TABLE_WMI_PDEV_SSCAN_FW_PARAM_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_sscan_fw_cmd_fixed_param, wmi_pdev_sscan_fw_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_sscan_fft_bin_index, fft_bin_index, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_sscan_fft_bin_index, fft_bin_index, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_sscan_chan_info, wmi_pdev_sscan_chan_info,chan_info, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_sscan_per_detector_info, det_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SSCAN_FW_PARAM_EVENTID);
/* Send sscan related event start/stop trigger to host */
@ -6470,6 +6699,44 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_halphy_cal_bmap_evt_fixed_param, wmi_pdev_set_halphy_cal_bmap_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_HALPHY_CAL_BMAP_EVENTID);
/* Update vdev mac address conf event to host */
#define WMITLV_TABLE_WMI_VDEV_UPDATE_MAC_ADDR_CONF_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_update_mac_addr_conf_event_fixed_param, wmi_vdev_update_mac_addr_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UPDATE_MAC_ADDR_CONF_EVENTID);
/* Set the WMI Quiet handling EventID */
#define WMITLV_TABLE_WMI_QUIET_HANDLING_EVENTID(id,op,buf,len)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_quiet_event_fixed_param, wmi_quiet_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_QUIET_HANDLING_EVENTID);
/* Resmgr Channel Time Quota changed event */
#define WMITLV_TABLE_WMI_RESMGR_CHAN_TIME_QUOTA_CHANGED_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, \
WMITLV_TAG_STRUC_wmi_resmgr_chan_time_quota_changed_event_fixed_param, \
wmi_resmgr_chan_time_quota_changed_event_fixed_param, \
fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_resmgr_chan_time_quota_tlv, chan_quota, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_RESMGR_CHAN_TIME_QUOTA_CHANGED_EVENTID);
/* PDev Packet Log Decode Info Event */
#define WMITLV_TABLE_WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_pktlog_decode_info_evt_fixed_param, wmi_pdev_pktlog_decode_info_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID);
/* RTT 11az PASN peer create request event */
#define WMITLV_TABLE_WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_create_req_event_fixed_param, \
wmi_rtt_pasn_peer_create_req_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_pasn_peer_create_req_param, rtt_pasn_peer_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID);
/* RTT 11az PASN peer delete event */
#define WMITLV_TABLE_WMI_RTT_PASN_PEER_DELETE_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_delete_event_fixed_param, \
wmi_rtt_pasn_peer_delete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_pasn_peer_delete_param, rtt_pasn_peer_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PASN_PEER_DELETE_EVENTID);
#ifdef __cplusplus
}

2191
drivers/staging/fw-api/fw/wmi_unified.h
View file

File diff suppressed because it is too large Load diff

3
drivers/staging/fw-api/fw/wmi_version.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2012-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@ -36,7 +37,7 @@
#define __WMI_VER_MINOR_ 0
/** WMI revision number has to be incremented when there is a
* change that may or may not break compatibility. */
#define __WMI_REVISION_ 1050
#define __WMI_REVISION_ 1127
/** The Version Namespace should not be normally changed. Only
* host and firmware of the same WMI namespace will work

66
drivers/staging/fw-api/hw/kiwi/v1/HALcomdef.h Normal file
View file

@ -0,0 +1,66 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef HAL_COMDEF_H
#define HAL_COMDEF_H
#ifndef _ARM_ASM_
#ifdef __cplusplus
extern "C" {
#endif
#include "com_dtypes.h"
#ifndef _BOOL32_DEFINED
typedef unsigned long int bool32;
#define _BOOL32_DEFINED
#endif
#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
#define inp(port) (*((volatile byte *) (port)))
#define inpw(port) (*((volatile word *) (port)))
#define inpdw(port) (*((volatile dword *)(port)))
#define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val)))
#define outpw(port, val) (*((volatile word *) (port)) = ((word) (val)))
#define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
#ifdef __cplusplus
}
#endif
#endif
#endif

355
drivers/staging/fw-api/hw/kiwi/v1/HALhwio.h Normal file
View file

@ -0,0 +1,355 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef HAL_HWIO_H
#define HAL_HWIO_H
#include "HALcomdef.h"
#define HWIO_BASE_PTR(base) base##_BASE_PTR
#ifdef __ARMCC_VERSION
#define DECLARE_HWIO_BASE_PTR(base) __weak uint8 * HWIO_BASE_PTR(base)
#else
#define DECLARE_HWIO_BASE_PTR(base) uint8 * HWIO_BASE_PTR(base)
#endif
#ifdef CONFIG_WHAL_MM
#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET
#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET
#endif
#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym)
#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index)
#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2)
#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3)
#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym)
#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index)
#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2)
#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym)
#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index)
#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2)
#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3)
#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym)
#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index)
#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2)
#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym)
#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index)
#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2)
#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3)
#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym)
#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index)
#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2)
#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3)
#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask)
#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask)
#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask)
#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym)
#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index)
#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2)
#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask)
#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask)
#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val)
#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val)
#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val)
#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val)
#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val)
#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val)
#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val)
#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val)
#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val)
#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val)
#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3))
#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4))
#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym)
#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index)
#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym)
#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym)
#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val)
#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym)
#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index)
#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN
#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index)
#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2)
#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3)
#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask)
#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask)
#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask)
#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val)
#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index, val)
#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val)
#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val)
#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR
#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index)
#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2)
#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS
#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index)
#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2)
#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS
#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index)
#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2)
#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK
#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index)
#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK
#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT
#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT
#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow
#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index)
#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base)
#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index)
#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2)
#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3)
#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask)
#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask)
#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val)
#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index, val)
#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val)
#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
}
#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
}
#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
HWIO_##hwiosym##_OUTM(base, mask4, val4); \
}
#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val)
#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base)
#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index)
#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2)
#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base)
#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index)
#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2)
#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
#define HWIO_INTLOCK()
#define HWIO_INTFREE()
#define __inp(port) (*((volatile uint8 *) (port)))
#define __inpw(port) (*((volatile uint16 *) (port)))
#define __inpdw(port) (*((volatile uint32 *) (port)))
#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val)))
#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val)))
#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
#ifdef HAL_HWIO_EXTERNAL
#undef __inp
#undef __inpw
#undef __inpdw
#undef __outp
#undef __outpw
#undef __outpdw
#define __inp(port) __inp_extern(port)
#define __inpw(port) __inpw_extern(port)
#define __inpdw(port) __inpdw_extern(port)
#define __outp(port, val) __outp_extern(port, val)
#define __outpw(port, val) __outpw_extern(port, val)
#define __outpdw(port, val) __outpdw_extern(port, val)
extern uint8 __inp_extern(uint32 nAddr);
extern uint16 __inpw_extern(uint32 nAddr);
extern uint32 __inpdw_extern(uint32 nAddr);
extern void __outp_extern(uint32 nAddr, uint8 nData);
extern void __outpw_extern(uint32 nAddr, uint16 nData);
extern void __outpdw_extern(uint32 nAddr, uint32 nData);
#endif
#define in_byte(addr) (__inp(addr))
#define in_byte_masked(addr, mask) (__inp(addr) & (mask))
#define out_byte(addr, val) __outp(addr, val)
#define out_byte_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
out_byte(io, shadow); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
HWIO_INTFREE()
#define out_byte_masked_ns(io, mask, val, current_reg_content) \
out_byte(io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))))
#define in_word(addr) (__inpw(addr))
#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
#define out_word(addr, val) __outpw(addr, val)
#define out_word_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
out_word(io, shadow); \
HWIO_INTFREE()
#define out_word_masked_ns(io, mask, val, current_reg_content) \
out_word(io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))))
#define in_dword(addr) (__inpdw(addr))
#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
#define out_dword(addr, val) __outpdw(addr, val)
#define out_dword_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
out_dword(io, shadow); \
HWIO_INTFREE()
#define out_dword_masked_ns(io, mask, val, current_reg_content) \
out_dword(io, ((current_reg_content & (uint32)(~(mask))) | \
((uint32)((val) & (mask)))))
#endif

29
drivers/staging/fw-api/hw/kiwi/v1/beryllium_top_reg.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef BERYLLIUM_TOP_REG_H
#define BERYLLIUM_TOP_REG_H
#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C)
#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050)
#endif

79
drivers/staging/fw-api/hw/kiwi/v1/buffer_addr_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BUFFER_ADDR_INFO_H_
#define _BUFFER_ADDR_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
struct buffer_addr_info {
uint32_t buffer_addr_31_0 : 32;
uint32_t buffer_addr_39_32 : 8,
return_buffer_manager : 4,
sw_buffer_cookie : 20;
};
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#endif

160
drivers/staging/fw-api/hw/kiwi/v1/ce_src_desc.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _CE_SRC_DESC_H_
#define _CE_SRC_DESC_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_CE_SRC_DESC 4
struct ce_src_desc {
uint32_t src_buffer_low : 32;
uint32_t src_buffer_high : 8,
toeplitz_en : 1,
src_swap : 1,
dest_swap : 1,
gather : 1,
ce_res_0 : 4,
length : 16;
uint32_t fw_metadata : 16,
ce_res_1 : 16;
uint32_t ce_res_2 : 20,
ring_id : 8,
looping_count : 4;
};
#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000
#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0
#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31
#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff
#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004
#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0
#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7
#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff
#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004
#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8
#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8
#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100
#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_SRC_SWAP_LSB 9
#define CE_SRC_DESC_SRC_SWAP_MSB 9
#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200
#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_DEST_SWAP_LSB 10
#define CE_SRC_DESC_DEST_SWAP_MSB 10
#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400
#define CE_SRC_DESC_GATHER_OFFSET 0x00000004
#define CE_SRC_DESC_GATHER_LSB 11
#define CE_SRC_DESC_GATHER_MSB 11
#define CE_SRC_DESC_GATHER_MASK 0x00000800
#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004
#define CE_SRC_DESC_CE_RES_0_LSB 12
#define CE_SRC_DESC_CE_RES_0_MSB 15
#define CE_SRC_DESC_CE_RES_0_MASK 0x0000f000
#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004
#define CE_SRC_DESC_LENGTH_LSB 16
#define CE_SRC_DESC_LENGTH_MSB 31
#define CE_SRC_DESC_LENGTH_MASK 0xffff0000
#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008
#define CE_SRC_DESC_FW_METADATA_LSB 0
#define CE_SRC_DESC_FW_METADATA_MSB 15
#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff
#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000008
#define CE_SRC_DESC_CE_RES_1_LSB 16
#define CE_SRC_DESC_CE_RES_1_MSB 31
#define CE_SRC_DESC_CE_RES_1_MASK 0xffff0000
#define CE_SRC_DESC_CE_RES_2_OFFSET 0x0000000c
#define CE_SRC_DESC_CE_RES_2_LSB 0
#define CE_SRC_DESC_CE_RES_2_MSB 19
#define CE_SRC_DESC_CE_RES_2_MASK 0x000fffff
#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c
#define CE_SRC_DESC_RING_ID_LSB 20
#define CE_SRC_DESC_RING_ID_MSB 27
#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000
#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_SRC_DESC_LOOPING_COUNT_LSB 28
#define CE_SRC_DESC_LOOPING_COUNT_MSB 31
#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000
#endif

160
drivers/staging/fw-api/hw/kiwi/v1/ce_stat_desc.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _CE_STAT_DESC_H_
#define _CE_STAT_DESC_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_CE_STAT_DESC 4
struct ce_stat_desc {
uint32_t ce_res_5 : 8,
toeplitz_en : 1,
src_swap : 1,
dest_swap : 1,
gather : 1,
ce_res_6 : 4,
length : 16;
uint32_t toeplitz_hash_0 : 32;
uint32_t toeplitz_hash_1 : 32;
uint32_t fw_metadata : 16,
ce_res_7 : 4,
ring_id : 8,
looping_count : 4;
};
#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000
#define CE_STAT_DESC_CE_RES_5_LSB 0
#define CE_STAT_DESC_CE_RES_5_MSB 7
#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff
#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000
#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8
#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8
#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100
#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_SRC_SWAP_LSB 9
#define CE_STAT_DESC_SRC_SWAP_MSB 9
#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200
#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_DEST_SWAP_LSB 10
#define CE_STAT_DESC_DEST_SWAP_MSB 10
#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400
#define CE_STAT_DESC_GATHER_OFFSET 0x00000000
#define CE_STAT_DESC_GATHER_LSB 11
#define CE_STAT_DESC_GATHER_MSB 11
#define CE_STAT_DESC_GATHER_MASK 0x00000800
#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000
#define CE_STAT_DESC_CE_RES_6_LSB 12
#define CE_STAT_DESC_CE_RES_6_MSB 15
#define CE_STAT_DESC_CE_RES_6_MASK 0x0000f000
#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000
#define CE_STAT_DESC_LENGTH_LSB 16
#define CE_STAT_DESC_LENGTH_MSB 31
#define CE_STAT_DESC_LENGTH_MASK 0xffff0000
#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004
#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0
#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31
#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff
#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008
#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0
#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31
#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff
#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c
#define CE_STAT_DESC_FW_METADATA_LSB 0
#define CE_STAT_DESC_FW_METADATA_MSB 15
#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff
#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c
#define CE_STAT_DESC_CE_RES_7_LSB 16
#define CE_STAT_DESC_CE_RES_7_MSB 19
#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000
#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c
#define CE_STAT_DESC_RING_ID_LSB 20
#define CE_STAT_DESC_RING_ID_MSB 27
#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000
#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_STAT_DESC_LOOPING_COUNT_LSB 28
#define CE_STAT_DESC_LOOPING_COUNT_MSB 31
#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000
#endif

217
drivers/staging/fw-api/hw/kiwi/v1/com_dtypes.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef COM_DTYPES_H
#define COM_DTYPES_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef T_WINNT
#ifndef WIN32
#define WIN32
#endif
#include <stdlib.h>
#endif
#ifdef TRUE
#undef TRUE
#endif
#ifdef FALSE
#undef FALSE
#endif
#define TRUE 1
#define FALSE 0
#define ON 1
#define OFF 0
#ifndef NULL
#define NULL 0
#endif
#ifndef _ARM_ASM_
#ifndef _BOOLEAN_DEFINED
typedef unsigned char boolean;
#define _BOOLEAN_DEFINED
#endif
#if defined(DALSTDDEF_H)
#define _BOOLEAN_DEFINED
#define _UINT32_DEFINED
#define _UINT16_DEFINED
#define _UINT8_DEFINED
#define _INT32_DEFINED
#define _INT16_DEFINED
#define _INT8_DEFINED
#define _UINT64_DEFINED
#define _INT64_DEFINED
#define _BYTE_DEFINED
#endif
#ifndef _UINT32_DEFINED
typedef unsigned long int uint32;
#define _UINT32_DEFINED
#endif
#ifndef _UINT16_DEFINED
typedef unsigned short uint16;
#define _UINT16_DEFINED
#endif
#ifndef _UINT8_DEFINED
typedef unsigned char uint8;
#define _UINT8_DEFINED
#endif
#ifndef _INT32_DEFINED
typedef signed long int int32;
#define _INT32_DEFINED
#endif
#ifndef _INT16_DEFINED
typedef signed short int16;
#define _INT16_DEFINED
#endif
#ifndef _INT8_DEFINED
typedef signed char int8;
#define _INT8_DEFINED
#endif
#ifndef _BYTE_DEFINED
typedef unsigned char byte;
#define _BYTE_DEFINED
#endif
typedef unsigned short word;
typedef unsigned long dword;
typedef unsigned char uint1;
typedef unsigned short uint2;
typedef unsigned long uint4;
typedef signed char int1;
typedef signed short int2;
typedef long int int4;
typedef signed long sint31;
typedef signed short sint15;
typedef signed char sint7;
typedef uint16 UWord16;
typedef uint32 UWord32;
typedef int32 Word32;
typedef int16 Word16;
typedef uint8 UWord8;
typedef int8 Word8;
typedef int32 Vect32;
#if (!defined T_WINNT) && (!defined __GNUC__)
#ifndef _INT64_DEFINED
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else
#if (defined __GNUC__)
#ifndef _INT64_DEFINED
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else
typedef __int64 int64;
#ifndef _UINT64_DEFINED
typedef unsigned __int64 uint64;
#define _UINT64_DEFINED
#endif
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

241
drivers/staging/fw-api/hw/kiwi/v1/he_sig_a_mu_dl_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_A_MU_DL_INFO_H_
#define _HE_SIG_A_MU_DL_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
struct he_sig_a_mu_dl_info {
uint32_t dl_ul_flag : 1,
mcs_of_sig_b : 3,
dcm_of_sig_b : 1,
bss_color_id : 6,
spatial_reuse : 4,
transmit_bw : 3,
num_sig_b_symbols : 4,
comp_mode_sig_b : 1,
cp_ltf_size : 2,
doppler_indication : 1,
reserved_0a : 6;
uint32_t txop_duration : 7,
reserved_1a : 1,
num_ltf_symbols : 3,
ldpc_extra_symbol : 1,
stbc : 1,
packet_extension_a_factor : 2,
packet_extension_pe_disambiguity : 1,
crc : 4,
tail : 6,
reserved_1b : 5,
rx_integrity_check_passed : 1;
};
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800
#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12
#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12
#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16
#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19
#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000
#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20
#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25
#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

151
drivers/staging/fw-api/hw/kiwi/v1/he_sig_a_mu_ul_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_A_MU_UL_INFO_H_
#define _HE_SIG_A_MU_UL_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
struct he_sig_a_mu_ul_info {
uint32_t format_indication : 1,
bss_color_id : 6,
spatial_reuse : 16,
reserved_0a : 1,
transmit_bw : 2,
reserved_0b : 6;
uint32_t txop_duration : 7,
reserved_1a : 9,
crc : 4,
tail : 6,
reserved_1b : 5,
rx_integrity_check_passed : 1;
};
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80
#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16
#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19
#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000
#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20
#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25
#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

286
drivers/staging/fw-api/hw/kiwi/v1/he_sig_a_su_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_A_SU_INFO_H_
#define _HE_SIG_A_SU_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
struct he_sig_a_su_info {
uint32_t format_indication : 1,
beam_change : 1,
dl_ul_flag : 1,
transmit_mcs : 4,
dcm : 1,
bss_color_id : 6,
reserved_0a : 1,
spatial_reuse : 4,
transmit_bw : 2,
cp_ltf_size : 2,
nsts : 3,
reserved_0b : 6;
uint32_t txop_duration : 7,
coding : 1,
ldpc_extra_symbol : 1,
stbc : 1,
txbf : 1,
packet_extension_a_factor : 2,
packet_extension_pe_disambiguity : 1,
reserved_1a : 1,
doppler_indication : 1,
crc : 4,
tail : 6,
dot11ax_su_extended : 1,
dot11ax_ext_ru_size : 3,
rx_ndp : 1,
rx_integrity_check_passed : 1;
};
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078
#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_DCM_LSB 7
#define HE_SIG_A_SU_INFO_DCM_MSB 7
#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00
#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14
#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14
#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000
#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_NSTS_LSB 23
#define HE_SIG_A_SU_INFO_NSTS_MSB 25
#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000
#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000
#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26
#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31
#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000
#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0
#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6
#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f
#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_CODING_LSB 7
#define HE_SIG_A_SU_INFO_CODING_MSB 7
#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100
#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_STBC_LSB 9
#define HE_SIG_A_SU_INFO_STBC_MSB 9
#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200
#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_TXBF_LSB 10
#define HE_SIG_A_SU_INFO_TXBF_MSB 10
#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14
#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14
#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000
#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_CRC_LSB 16
#define HE_SIG_A_SU_INFO_CRC_MSB 19
#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000
#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_TAIL_LSB 20
#define HE_SIG_A_SU_INFO_TAIL_MSB 25
#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000
#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30
#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30
#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

70
drivers/staging/fw-api/hw/kiwi/v1/he_sig_b1_mu_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_B1_MU_INFO_H_
#define _HE_SIG_B1_MU_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
struct he_sig_b1_mu_info {
uint32_t ru_allocation : 8,
reserved_0 : 23,
rx_integrity_check_passed : 1;
};
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff
#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000
#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8
#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30
#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

133
drivers/staging/fw-api/hw/kiwi/v1/he_sig_b2_mu_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_B2_MU_INFO_H_
#define _HE_SIG_B2_MU_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
struct he_sig_b2_mu_info {
uint32_t sta_id : 11,
sta_spatial_config : 4,
sta_mcs : 4,
reserved_set_to_1 : 1,
sta_coding : 1,
reserved_0a : 7,
nsts : 3,
rx_integrity_check_passed : 1;
uint32_t user_order : 8,
reserved_1a : 24;
};
#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0
#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10
#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800
#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15
#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18
#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000
#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20
#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20
#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000
#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21
#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27
#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000
#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_NSTS_LSB 28
#define HE_SIG_B2_MU_INFO_NSTS_MSB 30
#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004
#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0
#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7
#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff
#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 8
#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31
#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffffff00
#endif

133
drivers/staging/fw-api/hw/kiwi/v1/he_sig_b2_ofdma_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HE_SIG_B2_OFDMA_INFO_H_
#define _HE_SIG_B2_OFDMA_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2
struct he_sig_b2_ofdma_info {
uint32_t sta_id : 11,
nsts : 3,
txbf : 1,
sta_mcs : 4,
sta_dcm : 1,
sta_coding : 1,
reserved_0 : 10,
rx_integrity_check_passed : 1;
uint32_t user_order : 8,
reserved_1a : 24;
};
#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0
#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10
#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff
#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11
#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13
#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800
#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14
#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14
#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 8
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffffff00
#endif

187
drivers/staging/fw-api/hw/kiwi/v1/ht_sig_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HT_SIG_INFO_H_
#define _HT_SIG_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_HT_SIG_INFO 2
struct ht_sig_info {
uint32_t mcs : 7,
cbw : 1,
length : 16,
reserved_0 : 8;
uint32_t smoothing : 1,
not_sounding : 1,
ht_reserved : 1,
aggregation : 1,
stbc : 2,
fec_coding : 1,
short_gi : 1,
num_ext_sp_str : 2,
crc : 8,
signal_tail : 6,
reserved_1 : 7,
rx_integrity_check_passed : 1;
};
#define HT_SIG_INFO_MCS_OFFSET 0x00000000
#define HT_SIG_INFO_MCS_LSB 0
#define HT_SIG_INFO_MCS_MSB 6
#define HT_SIG_INFO_MCS_MASK 0x0000007f
#define HT_SIG_INFO_CBW_OFFSET 0x00000000
#define HT_SIG_INFO_CBW_LSB 7
#define HT_SIG_INFO_CBW_MSB 7
#define HT_SIG_INFO_CBW_MASK 0x00000080
#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000
#define HT_SIG_INFO_LENGTH_LSB 8
#define HT_SIG_INFO_LENGTH_MSB 23
#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00
#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000
#define HT_SIG_INFO_RESERVED_0_LSB 24
#define HT_SIG_INFO_RESERVED_0_MSB 31
#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000
#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004
#define HT_SIG_INFO_SMOOTHING_LSB 0
#define HT_SIG_INFO_SMOOTHING_MSB 0
#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001
#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004
#define HT_SIG_INFO_NOT_SOUNDING_LSB 1
#define HT_SIG_INFO_NOT_SOUNDING_MSB 1
#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002
#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004
#define HT_SIG_INFO_HT_RESERVED_LSB 2
#define HT_SIG_INFO_HT_RESERVED_MSB 2
#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004
#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004
#define HT_SIG_INFO_AGGREGATION_LSB 3
#define HT_SIG_INFO_AGGREGATION_MSB 3
#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008
#define HT_SIG_INFO_STBC_OFFSET 0x00000004
#define HT_SIG_INFO_STBC_LSB 4
#define HT_SIG_INFO_STBC_MSB 5
#define HT_SIG_INFO_STBC_MASK 0x00000030
#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004
#define HT_SIG_INFO_FEC_CODING_LSB 6
#define HT_SIG_INFO_FEC_CODING_MSB 6
#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040
#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004
#define HT_SIG_INFO_SHORT_GI_LSB 7
#define HT_SIG_INFO_SHORT_GI_MSB 7
#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080
#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004
#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8
#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9
#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300
#define HT_SIG_INFO_CRC_OFFSET 0x00000004
#define HT_SIG_INFO_CRC_LSB 10
#define HT_SIG_INFO_CRC_MSB 17
#define HT_SIG_INFO_CRC_MASK 0x0003fc00
#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004
#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18
#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23
#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000
#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004
#define HT_SIG_INFO_RESERVED_1_LSB 24
#define HT_SIG_INFO_RESERVED_1_MSB 30
#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

124
drivers/staging/fw-api/hw/kiwi/v1/l_sig_a_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _L_SIG_A_INFO_H_
#define _L_SIG_A_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_L_SIG_A_INFO 1
struct l_sig_a_info {
uint32_t rate : 4,
lsig_reserved : 1,
length : 12,
parity : 1,
tail : 6,
pkt_type : 4,
captured_implicit_sounding : 1,
reserved : 2,
rx_integrity_check_passed : 1;
};
#define L_SIG_A_INFO_RATE_OFFSET 0x00000000
#define L_SIG_A_INFO_RATE_LSB 0
#define L_SIG_A_INFO_RATE_MSB 3
#define L_SIG_A_INFO_RATE_MASK 0x0000000f
#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000
#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4
#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4
#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010
#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000
#define L_SIG_A_INFO_LENGTH_LSB 5
#define L_SIG_A_INFO_LENGTH_MSB 16
#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0
#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000
#define L_SIG_A_INFO_PARITY_LSB 17
#define L_SIG_A_INFO_PARITY_MSB 17
#define L_SIG_A_INFO_PARITY_MASK 0x00020000
#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000
#define L_SIG_A_INFO_TAIL_LSB 18
#define L_SIG_A_INFO_TAIL_MSB 23
#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000
#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000
#define L_SIG_A_INFO_PKT_TYPE_LSB 24
#define L_SIG_A_INFO_PKT_TYPE_MSB 27
#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000
#define L_SIG_A_INFO_RESERVED_LSB 29
#define L_SIG_A_INFO_RESERVED_MSB 30
#define L_SIG_A_INFO_RESERVED_MASK 0x60000000
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

79
drivers/staging/fw-api/hw/kiwi/v1/l_sig_b_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _L_SIG_B_INFO_H_
#define _L_SIG_B_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_L_SIG_B_INFO 1
struct l_sig_b_info {
uint32_t rate : 4,
length : 12,
reserved : 15,
rx_integrity_check_passed : 1;
};
#define L_SIG_B_INFO_RATE_OFFSET 0x00000000
#define L_SIG_B_INFO_RATE_LSB 0
#define L_SIG_B_INFO_RATE_MSB 3
#define L_SIG_B_INFO_RATE_MASK 0x0000000f
#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000
#define L_SIG_B_INFO_LENGTH_LSB 4
#define L_SIG_B_INFO_LENGTH_MSB 15
#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0
#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000
#define L_SIG_B_INFO_RESERVED_LSB 16
#define L_SIG_B_INFO_RESERVED_MSB 30
#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
#endif

61
drivers/staging/fw-api/hw/kiwi/v1/macrx_abort_request_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACRX_ABORT_REQUEST_INFO_H_
#define _MACRX_ABORT_REQUEST_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
struct macrx_abort_request_info {
uint16_t macrx_abort_reason : 8,
reserved_0 : 8;
};
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00
#endif

281
drivers/staging/fw-api/hw/kiwi/v1/msmhwiobase.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __MSMHWIOBASE_H__
#define __MSMHWIOBASE_H__
#define WCSS_WCSS_BASE 0x00000000
#define WCSS_WCSS_BASE_SIZE 0x01000000
#define WCSS_WCSS_BASE_PHYS 0x00000000
#define QDSS_STM_SIZE_BASE 0x00100000
#define QDSS_STM_SIZE_BASE_SIZE 0x100000000
#define QDSS_STM_SIZE_BASE_PHYS 0x00100000
#define BOOT_ROM_SIZE_BASE 0x00200000
#define BOOT_ROM_SIZE_BASE_SIZE 0x100000000
#define BOOT_ROM_SIZE_BASE_PHYS 0x00200000
#define SYSTEM_IRAM_SIZE_BASE 0x00400000
#define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000
#define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000
#define BOOT_ROM_START_ADDRESS_BASE 0x01200000
#define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000
#define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000
#define BOOT_ROM_END_ADDRESS_BASE 0x013fffff
#define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000
#define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff
#define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000
#define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000
#define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000
#define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff
#define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000
#define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff
#define QDSS_STM_BASE 0x01800000
#define QDSS_STM_BASE_SIZE 0x100000000
#define QDSS_STM_BASE_PHYS 0x01800000
#define QDSS_STM_END_BASE 0x018fffff
#define QDSS_STM_END_BASE_SIZE 0x100000000
#define QDSS_STM_END_BASE_PHYS 0x018fffff
#define TLMM_BASE 0x01900000
#define TLMM_BASE_SIZE 0x00200000
#define TLMM_BASE_PHYS 0x01900000
#define CORE_TOP_CSR_BASE 0x01b00000
#define CORE_TOP_CSR_BASE_SIZE 0x00040000
#define CORE_TOP_CSR_BASE_PHYS 0x01b00000
#define BLSP1_BLSP_BASE 0x01b40000
#define BLSP1_BLSP_BASE_SIZE 0x00040000
#define BLSP1_BLSP_BASE_PHYS 0x01b40000
#define SOC_WFSS_CE_REG_BASE 0x01b80000
#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000
#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000
#define WL_TLMM_BASE 0x01bc0000
#define WL_TLMM_BASE_SIZE 0x00020000
#define WL_TLMM_BASE_PHYS 0x01bc0000
#define MEMSS_CSR_BASE 0x01be0000
#define MEMSS_CSR_BASE_SIZE 0x0000001c
#define MEMSS_CSR_BASE_PHYS 0x01be0000
#define TSENS_SROT_BASE 0x01bf0000
#define TSENS_SROT_BASE_SIZE 0x00001000
#define TSENS_SROT_BASE_PHYS 0x01bf0000
#define TSENS_TM_BASE 0x01bf1000
#define TSENS_TM_BASE_SIZE 0x00001000
#define TSENS_TM_BASE_PHYS 0x01bf1000
#define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000
#define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000
#define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000
#define QDSS_WRAPPER_TOP_BASE 0x01c80000
#define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd
#define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000
#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000
#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000
#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000
#define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000
#define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000
#define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000
#define SECURITY_CONTROL_WLAN_BASE 0x01e20000
#define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000
#define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000
#define EDPD_CAL_ACC_BASE 0x01e28000
#define EDPD_CAL_ACC_BASE_SIZE 0x00003000
#define EDPD_CAL_ACC_BASE_PHYS 0x01e28000
#define CPR_CX_CPR3_BASE 0x01e30000
#define CPR_CX_CPR3_BASE_SIZE 0x00004000
#define CPR_CX_CPR3_BASE_PHYS 0x01e30000
#define CPR_MX_CPR3_BASE 0x01e34000
#define CPR_MX_CPR3_BASE_SIZE 0x00004000
#define CPR_MX_CPR3_BASE_PHYS 0x01e34000
#define GCC_GCC_BASE 0x01e40000
#define GCC_GCC_BASE_SIZE 0x000003e8
#define GCC_GCC_BASE_PHYS 0x01e40000
#define PRNG_PRNG_TOP_BASE 0x01e50000
#define PRNG_PRNG_TOP_BASE_SIZE 0x00010000
#define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000
#define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000
#define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000
#define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000
#define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000
#define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000
#define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000
#define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000
#define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000
#define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000
#define RRI_PREFETCH_REG_BASE 0x01e70000
#define RRI_PREFETCH_REG_BASE_SIZE 0x00010000
#define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000
#define SYSTEM_NOC_BASE 0x01e80000
#define SYSTEM_NOC_BASE_SIZE 0x0000a000
#define SYSTEM_NOC_BASE_PHYS 0x01e80000
#define PC_NOC_BASE 0x01f00000
#define PC_NOC_BASE_SIZE 0x00003880
#define PC_NOC_BASE_PHYS 0x01f00000
#define WLAON_WL_AON_REG_BASE 0x01f80000
#define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8
#define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000
#define SYSPM_SYSPM_REG_BASE 0x01f82000
#define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000
#define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000
#define PMU_WLAN_PMU_TOP_BASE 0x01f88000
#define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340
#define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000
#define PMU_NOC_BASE 0x01f8a000
#define PMU_NOC_BASE_SIZE 0x00000080
#define PMU_NOC_BASE_PHYS 0x01f8a000
#define PCIE_ATU_REGION_BASE 0x04000000
#define PCIE_ATU_REGION_BASE_SIZE 0x100000000
#define PCIE_ATU_REGION_BASE_PHYS 0x04000000
#define PCIE_ATU_REGION_SIZE_BASE 0x40000000
#define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000
#define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000
#define PCIE_ATU_REGION_END_BASE 0x43ffffff
#define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000
#define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff
#endif

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drivers/staging/fw-api/hw/kiwi/v1/msmhwioreg.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __MSMHWIOREG_H__
#define __MSMHWIOREG_H__
#include "msmhwiobase.h"
#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc
#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2
#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m, v, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, v)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m, v, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \
out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m, v, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \
out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, v)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m, v, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400)
#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m, v, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \
out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, v)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m, v) \
out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m, v, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400)
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058)
#endif

88
drivers/staging/fw-api/hw/kiwi/v1/phyrx_abort_request_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
#define _PHYRX_ABORT_REQUEST_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
struct phyrx_abort_request_info {
uint32_t phyrx_abort_reason : 8,
phy_enters_nap_state : 1,
phy_enters_defer_state : 1,
reserved_0 : 6,
receive_duration : 16;
};
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 10
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000fc00
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000
#endif

216
drivers/staging/fw-api/hw/kiwi/v1/phyrx_common_user_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_COMMON_USER_INFO_H_
#define _PHYRX_COMMON_USER_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4
#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2
struct phyrx_common_user_info {
uint32_t receive_duration : 16,
reserved_0a : 16;
uint32_t u_sig_puncture_pattern_encoding : 6,
reserved_1a : 26;
uint32_t eht_ppdu_type : 2,
bss_color_id : 6,
dl_ul_flag : 1,
txop_duration : 7,
cp_setting : 2,
ltf_size : 2,
spatial_reuse : 4,
rx_ndp : 1,
dot11be_su_extended : 1,
reserved_2a : 6;
uint32_t eht_duplicate : 2,
eht_sig_cmn_field_type : 2,
doppler_indication : 1,
sta_id : 11,
puncture_bitmap : 16;
};
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 38
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 63
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0xffffffc000000000
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB 0
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB 1
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK 0x0000000000000003
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00
#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16
#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17
#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000
#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24
#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24
#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB 25
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB 25
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK 0x0000000002000000
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0x00000000fc000000
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB 34
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB 35
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000
#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37
#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47
#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000
#endif

226
drivers/staging/fw-api/hw/kiwi/v1/phyrx_he_sig_a_mu_dl.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
#define _PHYRX_HE_SIG_A_MU_DL_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_a_mu_dl_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1
struct phyrx_he_sig_a_mu_dl {
struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
};
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

146
drivers/staging/fw-api/hw/kiwi/v1/phyrx_he_sig_a_mu_ul.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
#define _PHYRX_HE_SIG_A_MU_UL_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_a_mu_ul_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1
struct phyrx_he_sig_a_mu_ul {
struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
};
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

266
drivers/staging/fw-api/hw/kiwi/v1/phyrx_he_sig_a_su.h Normal file
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@ -0,0 +1,266 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_A_SU_H_
#define _PHYRX_HE_SIG_A_SU_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_a_su_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1
struct phyrx_he_sig_a_su {
struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
};
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

83
drivers/staging/fw-api/hw/kiwi/v1/phyrx_he_sig_b1_mu.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_B1_MU_H_
#define _PHYRX_HE_SIG_B1_MU_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_b1_mu_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1
struct phyrx_he_sig_b1_mu {
struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
uint32_t tlv64_padding : 32;
};
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000
#endif

130
drivers/staging/fw-api/hw/kiwi/v1/phyrx_he_sig_b2_mu.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_B2_MU_H_
#define _PHYRX_HE_SIG_B2_MU_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_b2_mu_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1
struct phyrx_he_sig_b2_mu {
struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
};
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 40
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffffff0000000000
#endif

130
drivers/staging/fw-api/hw/kiwi/v1/phyrx_he_sig_b2_ofdma.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
#define _PHYRX_HE_SIG_B2_OFDMA_H_
#if !defined(__ASSEMBLER__)
#endif
#include "he_sig_b2_ofdma_info.h"
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1
struct phyrx_he_sig_b2_ofdma {
struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
};
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 40
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffffff0000000000
#endif

178
drivers/staging/fw-api/hw/kiwi/v1/phyrx_ht_sig.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_HT_SIG_H_
#define _PHYRX_HT_SIG_H_
#if !defined(__ASSEMBLER__)
#endif
#include "ht_sig_info.h"
#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
#define NUM_OF_QWORDS_PHYRX_HT_SIG 1
struct phyrx_ht_sig {
struct ht_sig_info phyrx_ht_sig_info_details;
};
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

131
drivers/staging/fw-api/hw/kiwi/v1/phyrx_l_sig_a.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_L_SIG_A_H_
#define _PHYRX_L_SIG_A_H_
#if !defined(__ASSEMBLER__)
#endif
#include "l_sig_a_info.h"
#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2
#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1
struct phyrx_l_sig_a {
struct l_sig_a_info phyrx_l_sig_a_info_details;
uint32_t tlv64_padding : 32;
};
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32
#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63
#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000
#endif

91
drivers/staging/fw-api/hw/kiwi/v1/phyrx_l_sig_b.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_L_SIG_B_H_
#define _PHYRX_L_SIG_B_H_
#if !defined(__ASSEMBLER__)
#endif
#include "l_sig_b_info.h"
#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2
#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1
struct phyrx_l_sig_b {
struct l_sig_b_info phyrx_l_sig_b_info_details;
uint32_t tlv64_padding : 32;
};
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000
#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32
#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63
#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000
#endif

554
drivers/staging/fw-api/hw/kiwi/v1/phyrx_location.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_LOCATION_H_
#define _PHYRX_LOCATION_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_location_info.h"
#define NUM_OF_DWORDS_PHYRX_LOCATION 28
#define NUM_OF_QWORDS_PHYRX_LOCATION 14
struct phyrx_location {
struct rx_location_info rx_location_info_details;
};
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x000000000000000c
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000
#endif

81
drivers/staging/fw-api/hw/kiwi/v1/phyrx_other_receive_info_ru_details.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4
#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2
struct phyrx_other_receive_info_ru_details {
uint32_t ru_details_channel_0 : 32;
uint32_t ru_details_channel_1 : 32;
uint32_t spare : 32;
uint32_t tlv64_padding : 32;
};
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000
#endif

704
drivers/staging/fw-api/hw/kiwi/v1/phyrx_pkt_end.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_PKT_END_H_
#define _PHYRX_PKT_END_H_
#if !defined(__ASSEMBLER__)
#endif
#include "phyrx_pkt_end_info.h"
#define NUM_OF_DWORDS_PHYRX_PKT_END 24
#define NUM_OF_QWORDS_PHYRX_PKT_END 12
struct phyrx_pkt_end {
struct phyrx_pkt_end_info rx_pkt_end_details;
};
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MASK 0x0000000000000001
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 44
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff00000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000
#endif

716
drivers/staging/fw-api/hw/kiwi/v1/phyrx_pkt_end_info.h Normal file
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@ -0,0 +1,716 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_PKT_END_INFO_H_
#define _PHYRX_PKT_END_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#include "receive_rssi_info.h"
#include "rx_timing_offset_info.h"
#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24
struct phyrx_pkt_end_info {
uint32_t phy_internal_nap : 1,
location_info_valid : 1,
timing_info_valid : 1,
rssi_info_valid : 1,
reserved_0a : 1,
frameless_frame_received : 1,
reserved_0b : 2,
rssi_comb : 8,
reserved_0c : 16;
uint32_t phy_timestamp_1_lower_32 : 32;
uint32_t phy_timestamp_1_upper_32 : 32;
uint32_t phy_timestamp_2_lower_32 : 32;
uint32_t phy_timestamp_2_upper_32 : 32;
struct rx_timing_offset_info rx_timing_offset_info_details;
struct receive_rssi_info post_rssi_info_details;
uint32_t phy_sw_status_31_0 : 32;
uint32_t phy_sw_status_63_32 : 32;
};
#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_LSB 0
#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MSB 0
#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MASK 0x00000001
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008
#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4
#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4
#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6
#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7
#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0
#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8
#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15
#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000
#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16
#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31
#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31
#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000014
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 31
#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff
#endif

1267
drivers/staging/fw-api/hw/kiwi/v1/phyrx_rssi_legacy.h Normal file
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354
drivers/staging/fw-api/hw/kiwi/v1/phyrx_user_info.h Normal file
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@ -0,0 +1,354 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_USER_INFO_H_
#define _PHYRX_USER_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#include "receive_user_info.h"
#define NUM_OF_DWORDS_PHYRX_USER_INFO 12
#define NUM_OF_QWORDS_PHYRX_USER_INFO 6
struct phyrx_user_info {
struct receive_user_info receive_user_info_details;
};
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 35
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 36
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 37
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000003000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 38
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 39
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x000000c000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x00000000000000fe
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_OFFSET 0x0000000000000010
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_MASK 0x00000000ffffffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_OFFSET 0x0000000000000010
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_MASK 0xffffffff00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_OFFSET 0x0000000000000018
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_MASK 0x00000000ffffffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_OFFSET 0x0000000000000018
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_MASK 0xffffffff00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_OFFSET 0x0000000000000020
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_MASK 0x00000000ffffffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_OFFSET 0x0000000000000020
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_MASK 0xffffffff00000000
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_OFFSET 0x0000000000000028
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_LSB 0
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_MSB 31
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_MASK 0x00000000ffffffff
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_OFFSET 0x0000000000000028
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_LSB 32
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_MSB 63
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_MASK 0xffffffff00000000
#endif

194
drivers/staging/fw-api/hw/kiwi/v1/phyrx_vht_sig_a.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PHYRX_VHT_SIG_A_H_
#define _PHYRX_VHT_SIG_A_H_
#if !defined(__ASSEMBLER__)
#endif
#include "vht_sig_a_info.h"
#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1
struct phyrx_vht_sig_a {
struct vht_sig_a_info phyrx_vht_sig_a_info_details;
};
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
#endif

619
drivers/staging/fw-api/hw/kiwi/v1/receive_rssi_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RECEIVE_RSSI_INFO_H_
#define _RECEIVE_RSSI_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
struct receive_rssi_info {
uint32_t rssi_pri20_chain0 : 8,
rssi_ext20_chain0 : 8,
rssi_ext40_low20_chain0 : 8,
rssi_ext40_high20_chain0 : 8;
uint32_t rssi_ext80_low20_chain0 : 8,
rssi_ext80_low_high20_chain0 : 8,
rssi_ext80_high_low20_chain0 : 8,
rssi_ext80_high20_chain0 : 8;
uint32_t rssi_ext160_0_chain0 : 8,
rssi_ext160_1_chain0 : 8,
rssi_ext160_2_chain0 : 8,
rssi_ext160_3_chain0 : 8;
uint32_t rssi_ext160_4_chain0 : 8,
rssi_ext160_5_chain0 : 8,
rssi_ext160_6_chain0 : 8,
rssi_ext160_7_chain0 : 8;
uint32_t rssi_pri20_chain1 : 8,
rssi_ext20_chain1 : 8,
rssi_ext40_low20_chain1 : 8,
rssi_ext40_high20_chain1 : 8;
uint32_t rssi_ext80_low20_chain1 : 8,
rssi_ext80_low_high20_chain1 : 8,
rssi_ext80_high_low20_chain1 : 8,
rssi_ext80_high20_chain1 : 8;
uint32_t rssi_ext160_0_chain1 : 8,
rssi_ext160_1_chain1 : 8,
rssi_ext160_2_chain1 : 8,
rssi_ext160_3_chain1 : 8;
uint32_t rssi_ext160_4_chain1 : 8,
rssi_ext160_5_chain1 : 8,
rssi_ext160_6_chain1 : 8,
rssi_ext160_7_chain1 : 8;
uint32_t rssi_pri20_chain2 : 8,
rssi_ext20_chain2 : 8,
rssi_ext40_low20_chain2 : 8,
rssi_ext40_high20_chain2 : 8;
uint32_t rssi_ext80_low20_chain2 : 8,
rssi_ext80_low_high20_chain2 : 8,
rssi_ext80_high_low20_chain2 : 8,
rssi_ext80_high20_chain2 : 8;
uint32_t rssi_ext160_0_chain2 : 8,
rssi_ext160_1_chain2 : 8,
rssi_ext160_2_chain2 : 8,
rssi_ext160_3_chain2 : 8;
uint32_t rssi_ext160_4_chain2 : 8,
rssi_ext160_5_chain2 : 8,
rssi_ext160_6_chain2 : 8,
rssi_ext160_7_chain2 : 8;
uint32_t rssi_pri20_chain3 : 8,
rssi_ext20_chain3 : 8,
rssi_ext40_low20_chain3 : 8,
rssi_ext40_high20_chain3 : 8;
uint32_t rssi_ext80_low20_chain3 : 8,
rssi_ext80_low_high20_chain3 : 8,
rssi_ext80_high_low20_chain3 : 8,
rssi_ext80_high20_chain3 : 8;
uint32_t rssi_ext160_0_chain3 : 8,
rssi_ext160_1_chain3 : 8,
rssi_ext160_2_chain3 : 8,
rssi_ext160_3_chain3 : 8;
uint32_t rssi_ext160_4_chain3 : 8,
rssi_ext160_5_chain3 : 8,
rssi_ext160_6_chain3 : 8,
rssi_ext160_7_chain3 : 8;
};
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
#endif

385
drivers/staging/fw-api/hw/kiwi/v1/receive_user_info.h Normal file
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@ -0,0 +1,385 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RECEIVE_USER_INFO_H_
#define _RECEIVE_USER_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RECEIVE_USER_INFO 12
struct receive_user_info {
uint32_t phy_ppdu_id : 16,
user_rssi : 8,
pkt_type : 4,
stbc : 1,
reception_type : 3;
uint32_t rate_mcs : 4,
sgi : 2,
reserved_1a : 2,
mimo_ss_bitmap : 8,
receive_bandwidth : 3,
reserved_1b : 5,
dl_ofdma_user_index : 8;
uint32_t dl_ofdma_content_channel : 1,
reserved_2a : 7,
nss : 3,
stream_offset : 3,
sta_dcm : 1,
ldpc : 1,
ru_type_80_0 : 4,
ru_type_80_1 : 4,
ru_type_80_2 : 4,
ru_type_80_3 : 4;
uint32_t ru_start_index_80_0 : 6,
reserved_3a : 2,
ru_start_index_80_1 : 6,
reserved_3b : 2,
ru_start_index_80_2 : 6,
reserved_3c : 2,
ru_start_index_80_3 : 6,
reserved_3d : 2;
uint32_t user_fd_rssi_ss0 : 32;
uint32_t user_fd_rssi_ss1 : 32;
uint32_t user_fd_rssi_ss2 : 32;
uint32_t user_fd_rssi_ss3 : 32;
uint32_t user_fd_rssi_ss4 : 32;
uint32_t user_fd_rssi_ss5 : 32;
uint32_t user_fd_rssi_ss6 : 32;
uint32_t user_fd_rssi_ss7 : 32;
};
#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000
#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0
#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15
#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff
#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000
#define RECEIVE_USER_INFO_USER_RSSI_LSB 16
#define RECEIVE_USER_INFO_USER_RSSI_MSB 23
#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000
#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000
#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24
#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27
#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000
#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000
#define RECEIVE_USER_INFO_STBC_LSB 28
#define RECEIVE_USER_INFO_STBC_MSB 28
#define RECEIVE_USER_INFO_STBC_MASK 0x10000000
#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000
#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29
#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31
#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000
#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004
#define RECEIVE_USER_INFO_RATE_MCS_LSB 0
#define RECEIVE_USER_INFO_RATE_MCS_MSB 3
#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f
#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004
#define RECEIVE_USER_INFO_SGI_LSB 4
#define RECEIVE_USER_INFO_SGI_MSB 5
#define RECEIVE_USER_INFO_SGI_MASK 0x00000030
#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004
#define RECEIVE_USER_INFO_RESERVED_1A_LSB 6
#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7
#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x000000c0
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000
#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004
#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19
#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23
#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001
#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1
#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7
#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe
#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008
#define RECEIVE_USER_INFO_NSS_LSB 8
#define RECEIVE_USER_INFO_NSS_MSB 10
#define RECEIVE_USER_INFO_NSS_MASK 0x00000700
#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008
#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11
#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13
#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800
#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008
#define RECEIVE_USER_INFO_STA_DCM_LSB 14
#define RECEIVE_USER_INFO_STA_DCM_MSB 14
#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000
#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008
#define RECEIVE_USER_INFO_LDPC_LSB 15
#define RECEIVE_USER_INFO_LDPC_MSB 15
#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000
#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16
#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19
#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000
#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20
#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23
#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000
#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24
#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27
#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000
#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008
#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28
#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31
#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f
#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6
#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7
#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00
#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14
#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15
#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000
#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22
#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23
#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000
#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c
#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30
#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31
#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_OFFSET 0x00000010
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_OFFSET 0x00000014
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_OFFSET 0x00000018
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_OFFSET 0x0000001c
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_OFFSET 0x00000020
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_OFFSET 0x00000024
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_OFFSET 0x00000028
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_MASK 0xffffffff
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_OFFSET 0x0000002c
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_LSB 0
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_MSB 31
#define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_MASK 0xffffffff
#endif

360
drivers/staging/fw-api/hw/kiwi/v1/reo_descriptor_threshold_reached_status.h Normal file
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@ -0,0 +1,360 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26
#define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13
struct reo_descriptor_threshold_reached_status {
struct uniform_reo_status_header status_header;
uint32_t threshold_index : 2,
reserved_2 : 30;
uint32_t link_descriptor_counter0 : 24,
reserved_3 : 8;
uint32_t link_descriptor_counter1 : 24,
reserved_4 : 8;
uint32_t link_descriptor_counter2 : 24,
reserved_5 : 8;
uint32_t link_descriptor_counter_sum : 26,
reserved_6 : 6;
uint32_t reserved_7 : 32;
uint32_t reserved_8 : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x0000000000000003
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0x00000000fffffffc
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 55
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 56
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff00000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x0000000000ffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0x00000000ff000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 55
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 56
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff00000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000000000000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x0000000003ffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000000000000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0x00000000fc000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x0000000000000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x0000000000000020
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 59
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 60
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

421
drivers/staging/fw-api/hw/kiwi/v1/reo_destination_ring.h Normal file
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@ -0,0 +1,421 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_DESTINATION_RING_H_
#define _REO_DESTINATION_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_msdu_desc_info.h"
#include "rx_mpdu_desc_info.h"
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_REO_DESTINATION_RING 8
struct reo_destination_ring {
struct buffer_addr_info buf_or_link_desc_addr_info;
struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
uint32_t buffer_virt_addr_31_0 : 32;
uint32_t buffer_virt_addr_63_32 : 32;
uint32_t reo_dest_buffer_type : 1,
reo_push_reason : 2,
reo_error_code : 5,
captured_msdu_data_size : 4,
sw_exception : 1,
src_link_id : 3,
reo_destination_struct_signature : 4,
ring_id : 8,
looping_count : 4;
};
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_LSB 15
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MSB 22
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MASK 0x007f8000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 23
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 26
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x07800000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000010
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001
#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1
#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2
#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006
#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3
#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7
#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00
#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c
#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12
#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12
#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000
#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13
#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15
#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000
#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_RING_ID_LSB 20
#define REO_DESTINATION_RING_RING_ID_MSB 27
#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000
#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c
#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28
#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31
#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000
#endif

339
drivers/staging/fw-api/hw/kiwi/v1/reo_destination_ring_with_pn.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_DESTINATION_RING_WITH_PN_H_
#define _REO_DESTINATION_RING_WITH_PN_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_msdu_desc_info.h"
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8
struct reo_destination_ring_with_pn {
struct buffer_addr_info buf_or_link_desc_addr_info;
uint32_t msdu_count : 8,
prev_pn_23_0 : 24;
uint32_t prev_pn_55_24 : 32;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
uint32_t buffer_virt_addr_31_0 : 32;
uint32_t buffer_virt_addr_63_32 : 32;
uint32_t reo_dest_buffer_type : 1,
reo_push_reason : 2,
reo_error_code : 5,
captured_msdu_data_size : 4,
sw_exception : 1,
src_link_id : 3,
reo_destination_struct_signature : 4,
ring_id : 8,
looping_count : 4;
};
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7
#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_OFFSET 0x0000000c
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_LSB 0
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MSB 31
#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MASK 0xffffffff
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000010
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MSB 31
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_LSB 0
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MSB 31
#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0
#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2
#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7
#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11
#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12
#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15
#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19
#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000
#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20
#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27
#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31
#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000
#endif

370
drivers/staging/fw-api/hw/kiwi/v1/reo_entrance_ring.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_ENTRANCE_RING_H_
#define _REO_ENTRANCE_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_mpdu_details.h"
#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
struct reo_entrance_ring {
struct rx_mpdu_details reo_level_mpdu_frame_info;
uint32_t rx_reo_queue_desc_addr_31_0 : 32;
uint32_t rx_reo_queue_desc_addr_39_32 : 8,
rounded_mpdu_byte_count : 14,
reo_destination_indication : 5,
frameless_bar : 1,
reserved_5a : 4;
uint32_t rxdma_push_reason : 2,
rxdma_error_code : 5,
mpdu_fragment_number : 4,
sw_exception : 1,
sw_exception_mpdu_delink : 1,
sw_exception_destination_ring_valid : 1,
sw_exception_destination_ring : 5,
mpdu_sequence_number : 12,
reserved_6a : 1;
uint32_t phy_ppdu_id : 16,
src_link_id : 3,
reserved_7a : 1,
ring_id : 8,
looping_count : 4;
};
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_LSB 15
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MSB 22
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MASK 0x007f8000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 23
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 26
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x07800000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000
#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014
#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27
#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27
#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000
#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014
#define REO_ENTRANCE_RING_RESERVED_5A_LSB 28
#define REO_ENTRANCE_RING_RESERVED_5A_MSB 31
#define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780
#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018
#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11
#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11
#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000
#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018
#define REO_ENTRANCE_RING_RESERVED_6A_LSB 31
#define REO_ENTRANCE_RING_RESERVED_6A_MSB 31
#define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000
#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0
#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15
#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff
#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16
#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18
#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000
#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_RESERVED_7A_LSB 19
#define REO_ENTRANCE_RING_RESERVED_7A_MSB 19
#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000
#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_RING_ID_LSB 20
#define REO_ENTRANCE_RING_RING_ID_MSB 27
#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000
#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28
#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31
#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000
#endif

227
drivers/staging/fw-api/hw/kiwi/v1/reo_flush_cache.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_CACHE_H_
#define _REO_FLUSH_CACHE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_CACHE 10
#define NUM_OF_QWORDS_REO_FLUSH_CACHE 5
struct reo_flush_cache {
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_addr_31_0 : 32;
uint32_t flush_addr_39_32 : 8,
forward_all_mpdus_in_queue : 1,
release_cache_block_index : 1,
cache_block_resource_index : 2,
flush_without_invalidate : 1,
block_cache_usage_after_flush : 1,
flush_entire_cache : 1,
flush_queue_1k_desc : 1,
reserved_2b : 16;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
};
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000
#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16
#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31
#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000
#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_RESERVED_3A_LSB 32
#define REO_FLUSH_CACHE_RESERVED_3A_MSB 63
#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0
#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31
#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_RESERVED_5A_LSB 32
#define REO_FLUSH_CACHE_RESERVED_5A_MSB 63
#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0
#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31
#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_RESERVED_7A_LSB 32
#define REO_FLUSH_CACHE_RESERVED_7A_MSB 63
#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0
#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31
#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32
#define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63
#define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

396
drivers/staging/fw-api/hw/kiwi/v1/reo_flush_cache_status.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_CACHE_STATUS_H_
#define _REO_FLUSH_CACHE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26
#define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13
struct reo_flush_cache_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
block_error_details : 2,
reserved_2a : 5,
cache_controller_flush_status_hit : 1,
cache_controller_flush_status_desc_type : 3,
cache_controller_flush_status_client_id : 4,
cache_controller_flush_status_error : 2,
cache_controller_flush_count : 8,
flush_queue_1k_desc : 1,
reserved_2b : 5;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

191
drivers/staging/fw-api/hw/kiwi/v1/reo_flush_queue.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_QUEUE_H_
#define _REO_FLUSH_QUEUE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10
#define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5
struct reo_flush_queue {
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_desc_addr_31_0 : 32;
uint32_t flush_desc_addr_39_32 : 8,
block_desc_addr_usage_after_flush : 1,
block_resource_index : 2,
invalidate_queue_and_flush : 1,
reserved_2a : 20;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
};
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600
#define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_LSB 11
#define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_MSB 11
#define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x0000000000000800
#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 12
#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff000
#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32
#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63
#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0
#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32
#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63
#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0
#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32
#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63
#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0
#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32
#define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63
#define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

324
drivers/staging/fw-api/hw/kiwi/v1/reo_flush_queue_status.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_QUEUE_STATUS_H_
#define _REO_FLUSH_QUEUE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26
#define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13
struct reo_flush_queue_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
reserved_2a : 31;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

173
drivers/staging/fw-api/hw/kiwi/v1/reo_flush_timeout_list.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
#define _REO_FLUSH_TIMEOUT_LIST_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10
#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5
struct reo_flush_timeout_list {
struct uniform_reo_cmd_header cmd_header;
uint32_t ac_timout_list : 2,
reserved_1 : 30;
uint32_t minimum_release_desc_count : 16,
minimum_forward_buf_count : 16;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
};
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 33
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x0000000300000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 34
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc00000000
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x000000000000ffff
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0x00000000ffff0000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK 0xffffffff00000000
#endif

342
drivers/staging/fw-api/hw/kiwi/v1/reo_flush_timeout_list_status.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26
#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13
struct reo_flush_timeout_list_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
timout_list_empty : 1,
reserved_2a : 30;
uint32_t release_desc_count : 16,
forward_buf_count : 16;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

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drivers/staging/fw-api/hw/kiwi/v1/reo_get_queue_stats.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_GET_QUEUE_STATS_H_
#define _REO_GET_QUEUE_STATS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10
#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5
struct reo_get_queue_stats {
struct uniform_reo_cmd_header cmd_header;
uint32_t rx_reo_queue_desc_addr_31_0 : 32;
uint32_t rx_reo_queue_desc_addr_39_32 : 8,
clear_stats : 1,
reserved_2a : 23;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
};
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff
#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8
#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8
#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x0000000000000100
#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9
#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0x00000000fffffe00
#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 32
#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 63
#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0
#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 32
#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 63
#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0
#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 32
#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 63
#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0
#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB 32
#define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB 63
#define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK 0xffffffff00000000
#endif

405
drivers/staging/fw-api/hw/kiwi/v1/reo_get_queue_stats_status.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
#define _REO_GET_QUEUE_STATS_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 26
#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS_STATUS 13
struct reo_get_queue_stats_status {
struct uniform_reo_status_header status_header;
uint32_t ssn : 12,
current_index : 10,
reserved_2 : 10;
uint32_t pn_31_0 : 32;
uint32_t pn_63_32 : 32;
uint32_t pn_95_64 : 32;
uint32_t pn_127_96 : 32;
uint32_t last_rx_enqueue_timestamp : 32;
uint32_t last_rx_dequeue_timestamp : 32;
uint32_t rx_bitmap_31_0 : 32;
uint32_t rx_bitmap_63_32 : 32;
uint32_t rx_bitmap_95_64 : 32;
uint32_t rx_bitmap_127_96 : 32;
uint32_t rx_bitmap_159_128 : 32;
uint32_t rx_bitmap_191_160 : 32;
uint32_t rx_bitmap_223_192 : 32;
uint32_t rx_bitmap_255_224 : 32;
uint32_t rx_bitmap_287_256 : 32;
uint32_t current_mpdu_count : 7,
current_msdu_count : 25;
uint32_t window_jump_2k : 4,
timeout_count : 6,
forward_due_to_bar_count : 6,
duplicate_count : 16;
uint32_t frames_in_order_count : 24,
bar_received_count : 8;
uint32_t mpdu_frames_processed_count : 32;
uint32_t msdu_frames_processed_count : 32;
uint32_t total_processed_byte_count : 32;
uint32_t late_receive_mpdu_count : 12,
hole_count : 16,
get_queue_1k_stats_status_to_follow : 1,
reserved_24a : 3;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB 11
#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK 0x0000000000000fff
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB 12
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB 21
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK 0x00000000003ff000
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB 22
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK 0x00000000ffc00000
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET 0x0000000000000028
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET 0x0000000000000028
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET 0x0000000000000030
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET 0x0000000000000030
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET 0x0000000000000038
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET 0x0000000000000038
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET 0x0000000000000040
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET 0x0000000000000040
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB 6
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK 0x000000000000007f
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB 7
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK 0x00000000ffffff80
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB 35
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK 0x0000000f00000000
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB 36
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB 41
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK 0x000003f000000000
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB 42
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB 47
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc0000000000
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB 48
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK 0xffff000000000000
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000000000000050
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB 23
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK 0x0000000000ffffff
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET 0x0000000000000050
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB 24
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK 0x00000000ff000000
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000050
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000058
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000000000000058
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB 11
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK 0x0000000000000fff
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB 12
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB 27
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK 0x000000000ffff000
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB 28
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB 28
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK 0x0000000010000000
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB 29
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK 0x00000000e0000000
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB 59
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB 60
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

173
drivers/staging/fw-api/hw/kiwi/v1/reo_unblock_cache.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_UNBLOCK_CACHE_H_
#define _REO_UNBLOCK_CACHE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10
#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5
struct reo_unblock_cache {
struct uniform_reo_cmd_header cmd_header;
uint32_t unblock_type : 1,
cache_block_resource_index : 2,
reserved_1a : 29;
uint32_t reserved_2a : 32;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
};
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 32
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 32
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x0000000100000000
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 33
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 34
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000600000000
#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 35
#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff800000000
#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 32
#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 32
#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 32
#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB 32
#define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB 63
#define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

333
drivers/staging/fw-api/hw/kiwi/v1/reo_unblock_cache_status.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
#define _REO_UNBLOCK_CACHE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26
#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13
struct reo_unblock_cache_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
unblock_type : 1,
reserved_2a : 30;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x0000000000000002
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0x00000000fffffffc
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 59
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 60
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

569
drivers/staging/fw-api/hw/kiwi/v1/reo_update_rx_reo_queue.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
#define _REO_UPDATE_RX_REO_QUEUE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10
#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5
struct reo_update_rx_reo_queue {
struct uniform_reo_cmd_header cmd_header;
uint32_t rx_reo_queue_desc_addr_31_0 : 32;
uint32_t rx_reo_queue_desc_addr_39_32 : 8,
update_receive_queue_number : 1,
update_vld : 1,
update_associated_link_descriptor_counter : 1,
update_disable_duplicate_detection : 1,
update_soft_reorder_enable : 1,
update_ac : 1,
update_bar : 1,
update_rty : 1,
update_chk_2k_mode : 1,
update_oor_mode : 1,
update_ba_window_size : 1,
update_pn_check_needed : 1,
update_pn_shall_be_even : 1,
update_pn_shall_be_uneven : 1,
update_pn_handling_enable : 1,
update_pn_size : 1,
update_ignore_ampdu_flag : 1,
update_svld : 1,
update_ssn : 1,
update_seq_2k_error_detected_flag : 1,
update_pn_error_detected_flag : 1,
update_pn_valid : 1,
update_pn : 1,
clear_stat_counters : 1;
uint32_t receive_queue_number : 16,
vld : 1,
associated_link_descriptor_counter : 2,
disable_duplicate_detection : 1,
soft_reorder_enable : 1,
ac : 2,
bar : 1,
rty : 1,
chk_2k_mode : 1,
oor_mode : 1,
pn_check_needed : 1,
pn_shall_be_even : 1,
pn_shall_be_uneven : 1,
pn_handling_enable : 1,
ignore_ampdu_flag : 1;
uint32_t ba_window_size : 10,
pn_size : 2,
svld : 1,
ssn : 12,
seq_2k_error_detected_flag : 1,
pn_error_detected_flag : 1,
pn_valid : 1,
flush_from_cache : 1,
reserved_4a : 3;
uint32_t pn_31_0 : 32;
uint32_t pn_63_32 : 32;
uint32_t pn_95_64 : 32;
uint32_t pn_127_96 : 32;
uint32_t tlv64_padding : 32;
};
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000
#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48
#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48
#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000
#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53
#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54
#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000
#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55
#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55
#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000
#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56
#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56
#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00
#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12
#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12
#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000
#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13
#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24
#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

315
drivers/staging/fw-api/hw/kiwi/v1/reo_update_rx_reo_queue_status.h Normal file
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@ -0,0 +1,315 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26
#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13
struct reo_update_rx_reo_queue_status {
struct uniform_reo_status_header status_header;
uint32_t reserved_2a : 32;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
};
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 59
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 60
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

504
drivers/staging/fw-api/hw/kiwi/v1/rx_attention.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_ATTENTION_H_
#define _RX_ATTENTION_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_ATTENTION 4
#define NUM_OF_QWORDS_RX_ATTENTION 2
struct rx_attention {
uint32_t rxpcu_mpdu_filter_in_category : 2,
sw_frame_group_id : 7,
reserved_0 : 7,
phy_ppdu_id : 16;
uint32_t first_mpdu : 1,
reserved_1a : 1,
mcast_bcast : 1,
ast_index_not_found : 1,
ast_index_timeout : 1,
power_mgmt : 1,
non_qos : 1,
null_data : 1,
mgmt_type : 1,
ctrl_type : 1,
more_data : 1,
eosp : 1,
a_msdu_error : 1,
fragment_flag : 1,
order : 1,
cce_match : 1,
overflow_err : 1,
msdu_length_err : 1,
tcp_udp_chksum_fail : 1,
ip_chksum_fail : 1,
sa_idx_invalid : 1,
da_idx_invalid : 1,
reserved_1b : 1,
rx_in_tx_decrypt_byp : 1,
encrypt_required : 1,
directed : 1,
buffer_fragment : 1,
mpdu_length_err : 1,
tkip_mic_err : 1,
decrypt_err : 1,
unencrypted_frame_err : 1,
fcs_err : 1;
uint32_t flow_idx_timeout : 1,
flow_idx_invalid : 1,
wifi_parser_error : 1,
amsdu_parser_error : 1,
sa_idx_timeout : 1,
da_idx_timeout : 1,
msdu_limit_error : 1,
da_is_valid : 1,
da_is_mcbc : 1,
sa_is_valid : 1,
decrypt_status_code : 3,
rx_bitmap_not_updated : 1,
reserved_2 : 17,
msdu_done : 1;
uint32_t tlv64_padding : 32;
};
#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000
#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003
#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000
#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2
#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8
#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc
#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000
#define RX_ATTENTION_RESERVED_0_LSB 9
#define RX_ATTENTION_RESERVED_0_MSB 15
#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00
#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define RX_ATTENTION_PHY_PPDU_ID_LSB 16
#define RX_ATTENTION_PHY_PPDU_ID_MSB 31
#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000
#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000
#define RX_ATTENTION_FIRST_MPDU_LSB 32
#define RX_ATTENTION_FIRST_MPDU_MSB 32
#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000
#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000
#define RX_ATTENTION_RESERVED_1A_LSB 33
#define RX_ATTENTION_RESERVED_1A_MSB 33
#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000
#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000
#define RX_ATTENTION_MCAST_BCAST_LSB 34
#define RX_ATTENTION_MCAST_BCAST_MSB 34
#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000
#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000
#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35
#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35
#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000
#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000
#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36
#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36
#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000
#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000
#define RX_ATTENTION_POWER_MGMT_LSB 37
#define RX_ATTENTION_POWER_MGMT_MSB 37
#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000
#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000
#define RX_ATTENTION_NON_QOS_LSB 38
#define RX_ATTENTION_NON_QOS_MSB 38
#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000
#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000
#define RX_ATTENTION_NULL_DATA_LSB 39
#define RX_ATTENTION_NULL_DATA_MSB 39
#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000
#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000
#define RX_ATTENTION_MGMT_TYPE_LSB 40
#define RX_ATTENTION_MGMT_TYPE_MSB 40
#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000
#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000
#define RX_ATTENTION_CTRL_TYPE_LSB 41
#define RX_ATTENTION_CTRL_TYPE_MSB 41
#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000
#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000
#define RX_ATTENTION_MORE_DATA_LSB 42
#define RX_ATTENTION_MORE_DATA_MSB 42
#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000
#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000
#define RX_ATTENTION_EOSP_LSB 43
#define RX_ATTENTION_EOSP_MSB 43
#define RX_ATTENTION_EOSP_MASK 0x0000080000000000
#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000
#define RX_ATTENTION_A_MSDU_ERROR_LSB 44
#define RX_ATTENTION_A_MSDU_ERROR_MSB 44
#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000
#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000
#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45
#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45
#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000
#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000
#define RX_ATTENTION_ORDER_LSB 46
#define RX_ATTENTION_ORDER_MSB 46
#define RX_ATTENTION_ORDER_MASK 0x0000400000000000
#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000
#define RX_ATTENTION_CCE_MATCH_LSB 47
#define RX_ATTENTION_CCE_MATCH_MSB 47
#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000
#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_OVERFLOW_ERR_LSB 48
#define RX_ATTENTION_OVERFLOW_ERR_MSB 48
#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000
#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49
#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49
#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000
#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000
#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50
#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50
#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000
#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000
#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51
#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51
#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000
#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000
#define RX_ATTENTION_SA_IDX_INVALID_LSB 52
#define RX_ATTENTION_SA_IDX_INVALID_MSB 52
#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000
#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000
#define RX_ATTENTION_DA_IDX_INVALID_LSB 53
#define RX_ATTENTION_DA_IDX_INVALID_MSB 53
#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000
#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000
#define RX_ATTENTION_RESERVED_1B_LSB 54
#define RX_ATTENTION_RESERVED_1B_MSB 54
#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000
#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000
#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55
#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55
#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000
#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000
#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56
#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56
#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000
#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000
#define RX_ATTENTION_DIRECTED_LSB 57
#define RX_ATTENTION_DIRECTED_MSB 57
#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000
#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000
#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58
#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58
#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000
#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59
#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59
#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000
#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60
#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60
#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000
#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_DECRYPT_ERR_LSB 61
#define RX_ATTENTION_DECRYPT_ERR_MSB 61
#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000
#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62
#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62
#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000
#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000
#define RX_ATTENTION_FCS_ERR_LSB 63
#define RX_ATTENTION_FCS_ERR_MSB 63
#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000
#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008
#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0
#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0
#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001
#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008
#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1
#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1
#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002
#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008
#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2
#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2
#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004
#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008
#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3
#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3
#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008
#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008
#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4
#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4
#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010
#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008
#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5
#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5
#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020
#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008
#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6
#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6
#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040
#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008
#define RX_ATTENTION_DA_IS_VALID_LSB 7
#define RX_ATTENTION_DA_IS_VALID_MSB 7
#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080
#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008
#define RX_ATTENTION_DA_IS_MCBC_LSB 8
#define RX_ATTENTION_DA_IS_MCBC_MSB 8
#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100
#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008
#define RX_ATTENTION_SA_IS_VALID_LSB 9
#define RX_ATTENTION_SA_IS_VALID_MSB 9
#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200
#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008
#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10
#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12
#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00
#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008
#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13
#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13
#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000
#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008
#define RX_ATTENTION_RESERVED_2_LSB 14
#define RX_ATTENTION_RESERVED_2_MSB 30
#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000
#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008
#define RX_ATTENTION_MSDU_DONE_LSB 31
#define RX_ATTENTION_MSDU_DONE_MSB 31
#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000
#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008
#define RX_ATTENTION_TLV64_PADDING_LSB 32
#define RX_ATTENTION_TLV64_PADDING_MSB 63
#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000
#endif

277
drivers/staging/fw-api/hw/kiwi/v1/rx_flow_search_entry.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_FLOW_SEARCH_ENTRY_H_
#define _RX_FLOW_SEARCH_ENTRY_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
struct rx_flow_search_entry {
uint32_t src_ip_127_96 : 32;
uint32_t src_ip_95_64 : 32;
uint32_t src_ip_63_32 : 32;
uint32_t src_ip_31_0 : 32;
uint32_t dest_ip_127_96 : 32;
uint32_t dest_ip_95_64 : 32;
uint32_t dest_ip_63_32 : 32;
uint32_t dest_ip_31_0 : 32;
uint32_t src_port : 16,
dest_port : 16;
uint32_t l4_protocol : 8,
valid : 1,
reserved_9 : 14,
use_ppe : 1,
reo_destination_indication : 5,
msdu_drop : 1,
reo_destination_handler : 2;
uint32_t metadata : 32;
uint32_t aggregation_count : 7,
lro_eligible : 1,
msdu_count : 24;
uint32_t msdu_byte_count : 32;
uint32_t timestamp : 32;
uint32_t cumulative_l4_checksum : 16,
cumulative_ip_length : 16;
uint32_t tcp_sequence_number : 32;
};
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31
#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31
#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020
#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0
#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15
#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff
#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020
#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16
#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31
#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000
#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0
#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7
#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff
#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8
#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8
#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100
#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9
#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 22
#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x007ffe00
#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23
#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23
#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000
#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29
#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29
#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31
#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000
#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028
#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0
#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31
#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c
#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0
#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6
#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f
#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c
#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7
#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7
#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080
#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c
#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8
#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31
#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00
#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030
#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0
#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31
#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034
#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0
#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31
#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_L4_CHECKSUM_LSB 0
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_L4_CHECKSUM_MSB 15
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31
#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c
#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0
#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31
#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff
#endif

610
drivers/staging/fw-api/hw/kiwi/v1/rx_location_info.h Normal file
View file

@ -0,0 +1,610 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_LOCATION_INFO_H_
#define _RX_LOCATION_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_LOCATION_INFO 28
struct rx_location_info {
uint32_t rx_location_info_valid : 1,
rtt_hw_ifft_mode : 1,
rtt_11az_mode : 2,
reserved_0 : 4,
rtt_num_fac : 8,
rtt_rx_chain_mask : 8,
rtt_num_streams : 8;
uint32_t rtt_first_selected_chain : 8,
rtt_second_selected_chain : 8,
rtt_cfr_status : 8,
rtt_cir_status : 8;
uint32_t rtt_che_buffer_pointer_low32 : 32;
uint32_t rtt_che_buffer_pointer_high8 : 8,
reserved_3 : 8,
rtt_pkt_bw_vht : 4,
rtt_pkt_bw_leg : 4,
rtt_mcs_rate : 8;
uint32_t rtt_cfo_measurement : 16,
rtt_preamble_type : 8,
rtt_gi_type : 8;
uint32_t rx_start_ts : 32;
uint32_t rx_start_ts_upper : 32;
uint32_t rx_end_ts : 32;
uint32_t gain_chain0 : 16,
gain_chain1 : 16;
uint32_t gain_chain2 : 16,
gain_chain3 : 16;
uint32_t gain_report_status : 8,
rtt_timing_backoff_sel : 8,
rtt_fac_combined : 16;
uint32_t rtt_fac_0 : 16,
rtt_fac_1 : 16;
uint32_t rtt_fac_2 : 16,
rtt_fac_3 : 16;
uint32_t rtt_fac_4 : 16,
rtt_fac_5 : 16;
uint32_t rtt_fac_6 : 16,
rtt_fac_7 : 16;
uint32_t rtt_fac_8 : 16,
rtt_fac_9 : 16;
uint32_t rtt_fac_10 : 16,
rtt_fac_11 : 16;
uint32_t rtt_fac_12 : 16,
rtt_fac_13 : 16;
uint32_t rtt_fac_14 : 16,
rtt_fac_15 : 16;
uint32_t rtt_fac_16 : 16,
rtt_fac_17 : 16;
uint32_t rtt_fac_18 : 16,
rtt_fac_19 : 16;
uint32_t rtt_fac_20 : 16,
rtt_fac_21 : 16;
uint32_t rtt_fac_22 : 16,
rtt_fac_23 : 16;
uint32_t rtt_fac_24 : 16,
rtt_fac_25 : 16;
uint32_t rtt_fac_26 : 16,
rtt_fac_27 : 16;
uint32_t rtt_fac_28 : 16,
rtt_fac_29 : 16;
uint32_t rtt_fac_30 : 16,
rtt_fac_31 : 16;
uint32_t reserved_27a : 32;
};
#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000
#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0
#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0
#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001
#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000
#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1
#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1
#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002
#define RX_LOCATION_INFO_RTT_11AZ_MODE_OFFSET 0x00000000
#define RX_LOCATION_INFO_RTT_11AZ_MODE_LSB 2
#define RX_LOCATION_INFO_RTT_11AZ_MODE_MSB 3
#define RX_LOCATION_INFO_RTT_11AZ_MODE_MASK 0x0000000c
#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000
#define RX_LOCATION_INFO_RESERVED_0_LSB 4
#define RX_LOCATION_INFO_RESERVED_0_MSB 7
#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0
#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000
#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8
#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15
#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00
#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000
#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16
#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23
#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000
#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000
#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24
#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31
#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000
#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004
#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0
#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7
#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff
#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004
#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8
#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15
#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00
#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004
#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16
#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23
#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000
#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004
#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24
#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31
#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7
#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff
#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c
#define RX_LOCATION_INFO_RESERVED_3_LSB 8
#define RX_LOCATION_INFO_RESERVED_3_MSB 15
#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00
#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c
#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16
#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19
#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000
#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c
#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20
#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23
#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000
#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c
#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24
#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31
#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000
#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010
#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0
#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15
#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010
#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16
#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23
#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000
#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010
#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24
#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31
#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000
#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014
#define RX_LOCATION_INFO_RX_START_TS_LSB 0
#define RX_LOCATION_INFO_RX_START_TS_MSB 31
#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff
#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018
#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0
#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31
#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff
#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c
#define RX_LOCATION_INFO_RX_END_TS_LSB 0
#define RX_LOCATION_INFO_RX_END_TS_MSB 31
#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff
#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020
#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0
#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15
#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff
#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020
#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16
#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31
#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000
#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024
#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0
#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15
#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff
#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024
#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16
#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31
#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000
#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028
#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0
#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7
#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff
#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028
#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8
#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15
#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00
#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028
#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c
#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c
#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030
#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030
#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034
#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034
#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038
#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038
#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c
#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c
#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040
#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040
#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044
#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044
#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048
#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048
#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c
#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c
#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050
#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050
#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054
#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054
#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058
#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058
#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c
#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c
#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060
#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060
#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064
#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064
#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000
#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068
#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0
#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15
#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff
#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068
#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16
#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31
#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000
#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c
#define RX_LOCATION_INFO_RESERVED_27A_LSB 0
#define RX_LOCATION_INFO_RESERVED_27A_MSB 31
#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff
#endif

160
drivers/staging/fw-api/hw/kiwi/v1/rx_mpdu_desc_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MPDU_DESC_INFO_H_
#define _RX_MPDU_DESC_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
struct rx_mpdu_desc_info {
uint32_t msdu_count : 8,
fragment_flag : 1,
mpdu_retry_bit : 1,
ampdu_flag : 1,
bar_frame : 1,
pn_fields_contain_valid_info : 1,
raw_mpdu : 1,
more_fragment_flag : 1,
vdev_id : 8,
reserved_0a : 4,
mpdu_qos_control_valid : 1,
tid : 4;
uint32_t peer_meta_data : 32;
};
#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0
#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7
#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff
#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8
#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8
#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100
#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9
#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9
#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200
#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10
#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10
#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400
#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11
#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11
#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800
#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13
#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13
#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000
#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14
#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14
#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000
#define RX_MPDU_DESC_INFO_VDEV_ID_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_VDEV_ID_LSB 15
#define RX_MPDU_DESC_INFO_VDEV_ID_MSB 22
#define RX_MPDU_DESC_INFO_VDEV_ID_MASK 0x007f8000
#define RX_MPDU_DESC_INFO_RESERVED_0A_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_RESERVED_0A_LSB 23
#define RX_MPDU_DESC_INFO_RESERVED_0A_MSB 26
#define RX_MPDU_DESC_INFO_RESERVED_0A_MASK 0x07800000
#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27
#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27
#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_TID_LSB 28
#define RX_MPDU_DESC_INFO_TID_MSB 31
#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000
#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004
#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0
#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31
#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff
#endif

189
drivers/staging/fw-api/hw/kiwi/v1/rx_mpdu_details.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MPDU_DETAILS_H_
#define _RX_MPDU_DETAILS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_mpdu_desc_info.h"
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4
struct rx_mpdu_details {
struct buffer_addr_info msdu_link_desc_addr_info;
struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
};
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_LSB 15
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MSB 22
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MASK 0x007f8000
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 23
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 26
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x07800000
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
#endif

261
drivers/staging/fw-api/hw/kiwi/v1/rx_mpdu_end.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MPDU_END_H_
#define _RX_MPDU_END_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_MPDU_END 4
#define NUM_OF_QWORDS_RX_MPDU_END 2
struct rx_mpdu_end {
uint32_t rxpcu_mpdu_filter_in_category : 2,
sw_frame_group_id : 7,
reserved_0 : 7,
phy_ppdu_id : 16;
uint32_t reserved_1a : 11,
unsup_ktype_short_frame : 1,
rx_in_tx_decrypt_byp : 1,
overflow_err : 1,
mpdu_length_err : 1,
tkip_mic_err : 1,
decrypt_err : 1,
unencrypted_frame_err : 1,
pn_fields_contain_valid_info : 1,
fcs_err : 1,
msdu_length_err : 1,
rxdma0_destination_ring : 3,
rxdma1_destination_ring : 3,
decrypt_status_code : 3,
rx_bitmap_not_updated : 1,
reserved_1b : 1;
uint32_t reserved_2a : 15,
rxpcu_mgmt_sequence_nr_valid : 1,
rxpcu_mgmt_sequence_nr : 16;
uint32_t rxframe_assert_mlo_timestamp : 32;
};
#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000
#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003
#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000
#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2
#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8
#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc
#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000
#define RX_MPDU_END_RESERVED_0_LSB 9
#define RX_MPDU_END_RESERVED_0_MSB 15
#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00
#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define RX_MPDU_END_PHY_PPDU_ID_LSB 16
#define RX_MPDU_END_PHY_PPDU_ID_MSB 31
#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000
#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000
#define RX_MPDU_END_RESERVED_1A_LSB 32
#define RX_MPDU_END_RESERVED_1A_MSB 42
#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000
#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000
#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43
#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43
#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000
#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000
#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44
#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44
#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000
#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000
#define RX_MPDU_END_OVERFLOW_ERR_LSB 45
#define RX_MPDU_END_OVERFLOW_ERR_MSB 45
#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000
#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000
#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46
#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46
#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000
#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000
#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47
#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47
#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000
#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000
#define RX_MPDU_END_DECRYPT_ERR_LSB 48
#define RX_MPDU_END_DECRYPT_ERR_MSB 48
#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000
#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000
#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49
#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49
#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000
#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000
#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50
#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50
#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000
#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000
#define RX_MPDU_END_FCS_ERR_LSB 51
#define RX_MPDU_END_FCS_ERR_MSB 51
#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000
#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000
#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52
#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52
#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000
#define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000
#define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53
#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55
#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000
#define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000
#define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56
#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58
#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000
#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000
#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59
#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61
#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000
#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000
#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62
#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62
#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000
#define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000
#define RX_MPDU_END_RESERVED_1B_LSB 63
#define RX_MPDU_END_RESERVED_1B_MSB 63
#define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000
#define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008
#define RX_MPDU_END_RESERVED_2A_LSB 0
#define RX_MPDU_END_RESERVED_2A_MSB 14
#define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31
#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000
#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008
#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32
#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63
#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000
#endif

1132
drivers/staging/fw-api/hw/kiwi/v1/rx_mpdu_info.h Normal file
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drivers/staging/fw-api/hw/kiwi/v1/rx_mpdu_link_ptr.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MPDU_LINK_PTR_H_
#define _RX_MPDU_LINK_PTR_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
struct rx_mpdu_link_ptr {
struct buffer_addr_info mpdu_link_desc_addr_info;
};
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#endif

1029
drivers/staging/fw-api/hw/kiwi/v1/rx_mpdu_start.h Normal file
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drivers/staging/fw-api/hw/kiwi/v1/rx_msdu_desc_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MSDU_DESC_INFO_H_
#define _RX_MSDU_DESC_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1
struct rx_msdu_desc_info {
uint32_t first_msdu_in_mpdu_flag : 1,
last_msdu_in_mpdu_flag : 1,
msdu_continuation : 1,
msdu_length : 14,
msdu_drop : 1,
sa_is_valid : 1,
da_is_valid : 1,
da_is_mcbc : 1,
l3_header_padding_msb : 1,
tcp_udp_chksum_fail : 1,
ip_chksum_fail : 1,
fr_ds : 1,
to_ds : 1,
intra_bss : 1,
dest_chip_id : 2,
reserved_0a : 3;
};
#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1
#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1
#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2
#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2
#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004
#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3
#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16
#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8
#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17
#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17
#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000
#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18
#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18
#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000
#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19
#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19
#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000
#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20
#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20
#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000
#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21
#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21
#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000
#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22
#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22
#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23
#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23
#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000
#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_FR_DS_LSB 24
#define RX_MSDU_DESC_INFO_FR_DS_MSB 24
#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000
#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_TO_DS_LSB 25
#define RX_MSDU_DESC_INFO_TO_DS_MSB 25
#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000
#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26
#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26
#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000
#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27
#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28
#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000
#define RX_MSDU_DESC_INFO_RESERVED_0A_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_RESERVED_0A_LSB 29
#define RX_MSDU_DESC_INFO_RESERVED_0A_MSB 31
#define RX_MSDU_DESC_INFO_RESERVED_0A_MASK 0xe0000000
#endif

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drivers/staging/fw-api/hw/kiwi/v1/rx_msdu_details.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MSDU_DETAILS_H_
#define _RX_MSDU_DETAILS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_msdu_desc_info.h"
#include "rx_msdu_ext_desc_info.h"
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
struct rx_msdu_details {
struct buffer_addr_info buffer_addr_info_details;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details;
};
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 27
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf8000000
#endif

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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MSDU_EXT_DESC_INFO_H_
#define _RX_MSDU_EXT_DESC_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1
struct rx_msdu_ext_desc_info {
uint32_t reo_destination_indication : 5,
service_code : 9,
priority_valid : 1,
data_offset : 12,
reserved_0a : 5;
};
#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000
#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0
#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4
#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f
#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000
#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5
#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13
#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0
#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000
#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14
#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14
#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000
#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000
#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15
#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26
#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000
#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000
#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 27
#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31
#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xf8000000
#endif

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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_MSDU_START_H_
#define _RX_MSDU_START_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_MSDU_START 10
#define NUM_OF_QWORDS_RX_MSDU_START 5
struct rx_msdu_start {
uint32_t rxpcu_mpdu_filter_in_category : 2,
sw_frame_group_id : 7,
reserved_0 : 7,
phy_ppdu_id : 16;
uint32_t msdu_length : 14,
stbc : 1,
ipsec_esp : 1,
l3_offset : 7,
ipsec_ah : 1,
l4_offset : 8;
uint32_t msdu_number : 8,
decap_format : 2,
ipv4_proto : 1,
ipv6_proto : 1,
tcp_proto : 1,
udp_proto : 1,
ip_frag : 1,
tcp_only_ack : 1,
da_is_bcast_mcast : 1,
toeplitz_hash_sel : 2,
ip_fixed_header_valid : 1,
ip_extn_header_valid : 1,
tcp_udp_header_valid : 1,
mesh_control_present : 1,
ldpc : 1,
ip4_protocol_ip6_next_header : 8;
uint32_t toeplitz_hash_2_or_4 : 32;
uint32_t flow_id_toeplitz : 32;
uint32_t user_rssi : 8,
pkt_type : 4,
sgi : 2,
rate_mcs : 4,
receive_bandwidth : 3,
reception_type : 3,
mimo_ss_bitmap : 8;
uint32_t ppdu_start_timestamp_31_0 : 32;
uint32_t ppdu_start_timestamp_63_32 : 32;
uint32_t sw_phy_meta_data : 32;
uint32_t vlan_ctag_ci : 16,
vlan_stag_ci : 16;
};
#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000
#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003
#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000
#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2
#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8
#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc
#define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000
#define RX_MSDU_START_RESERVED_0_LSB 9
#define RX_MSDU_START_RESERVED_0_MSB 15
#define RX_MSDU_START_RESERVED_0_MASK 0x000000000000fe00
#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define RX_MSDU_START_PHY_PPDU_ID_LSB 16
#define RX_MSDU_START_PHY_PPDU_ID_MSB 31
#define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000
#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000
#define RX_MSDU_START_MSDU_LENGTH_LSB 32
#define RX_MSDU_START_MSDU_LENGTH_MSB 45
#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000
#define RX_MSDU_START_STBC_OFFSET 0x0000000000000000
#define RX_MSDU_START_STBC_LSB 46
#define RX_MSDU_START_STBC_MSB 46
#define RX_MSDU_START_STBC_MASK 0x0000400000000000
#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000
#define RX_MSDU_START_IPSEC_ESP_LSB 47
#define RX_MSDU_START_IPSEC_ESP_MSB 47
#define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000
#define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000
#define RX_MSDU_START_L3_OFFSET_LSB 48
#define RX_MSDU_START_L3_OFFSET_MSB 54
#define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000
#define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000
#define RX_MSDU_START_IPSEC_AH_LSB 55
#define RX_MSDU_START_IPSEC_AH_MSB 55
#define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000
#define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000
#define RX_MSDU_START_L4_OFFSET_LSB 56
#define RX_MSDU_START_L4_OFFSET_MSB 63
#define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000
#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008
#define RX_MSDU_START_MSDU_NUMBER_LSB 0
#define RX_MSDU_START_MSDU_NUMBER_MSB 7
#define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff
#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008
#define RX_MSDU_START_DECAP_FORMAT_LSB 8
#define RX_MSDU_START_DECAP_FORMAT_MSB 9
#define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300
#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008
#define RX_MSDU_START_IPV4_PROTO_LSB 10
#define RX_MSDU_START_IPV4_PROTO_MSB 10
#define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400
#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008
#define RX_MSDU_START_IPV6_PROTO_LSB 11
#define RX_MSDU_START_IPV6_PROTO_MSB 11
#define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800
#define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008
#define RX_MSDU_START_TCP_PROTO_LSB 12
#define RX_MSDU_START_TCP_PROTO_MSB 12
#define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000
#define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008
#define RX_MSDU_START_UDP_PROTO_LSB 13
#define RX_MSDU_START_UDP_PROTO_MSB 13
#define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000
#define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008
#define RX_MSDU_START_IP_FRAG_LSB 14
#define RX_MSDU_START_IP_FRAG_MSB 14
#define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000
#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008
#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15
#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15
#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000
#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008
#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16
#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16
#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000
#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008
#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17
#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18
#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000
#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008
#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19
#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19
#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000
#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008
#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20
#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20
#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000
#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008
#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21
#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21
#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000
#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008
#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22
#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22
#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000
#define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008
#define RX_MSDU_START_LDPC_LSB 23
#define RX_MSDU_START_LDPC_MSB 23
#define RX_MSDU_START_LDPC_MASK 0x0000000000800000
#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008
#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24
#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31
#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000
#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008
#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32
#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63
#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000
#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010
#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0
#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31
#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff
#define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010
#define RX_MSDU_START_USER_RSSI_LSB 32
#define RX_MSDU_START_USER_RSSI_MSB 39
#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000
#define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010
#define RX_MSDU_START_PKT_TYPE_LSB 40
#define RX_MSDU_START_PKT_TYPE_MSB 43
#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000
#define RX_MSDU_START_SGI_OFFSET 0x0000000000000010
#define RX_MSDU_START_SGI_LSB 44
#define RX_MSDU_START_SGI_MSB 45
#define RX_MSDU_START_SGI_MASK 0x0000300000000000
#define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000010
#define RX_MSDU_START_RATE_MCS_LSB 46
#define RX_MSDU_START_RATE_MCS_MSB 49
#define RX_MSDU_START_RATE_MCS_MASK 0x0003c00000000000
#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010
#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50
#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52
#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000
#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010
#define RX_MSDU_START_RECEPTION_TYPE_LSB 53
#define RX_MSDU_START_RECEPTION_TYPE_MSB 55
#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000
#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010
#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56
#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63
#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000
#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018
#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0
#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31
#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff
#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018
#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32
#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63
#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000
#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020
#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0
#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31
#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff
#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020
#define RX_MSDU_START_VLAN_CTAG_CI_LSB 32
#define RX_MSDU_START_VLAN_CTAG_CI_MSB 47
#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000
#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020
#define RX_MSDU_START_VLAN_STAG_CI_LSB 48
#define RX_MSDU_START_VLAN_STAG_CI_MSB 63
#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000
#endif

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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_PPDU_END_USER_STATS_H_
#define _RX_PPDU_END_USER_STATS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_rxpcu_classification_overview.h"
#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 24
#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 12
struct rx_ppdu_end_user_stats {
struct rx_rxpcu_classification_overview rxpcu_classification_details;
uint32_t sta_full_aid : 13,
mcs : 4,
nss : 3,
reserved_1a : 12;
uint32_t reserved_2a : 16,
mpdu_cnt_fcs_err : 11,
sw2rxdma0_buf_source_used : 1,
fw2rxdma_pmac0_buf_source_used : 1,
sw2rxdma1_buf_source_used : 1,
sw2rxdma_exception_buf_source_used : 1,
fw2rxdma_pmac1_buf_source_used : 1;
uint32_t mpdu_cnt_fcs_ok : 11,
frame_control_info_valid : 1,
qos_control_info_valid : 1,
ht_control_info_valid : 1,
data_sequence_control_info_valid : 1,
ht_control_info_null_valid : 1,
rxdma2fw_pmac1_ring_used : 1,
rxdma2reo_ring_used : 1,
rxdma2fw_pmac0_ring_used : 1,
rxdma2sw_ring_used : 1,
rxdma_release_ring_used : 1,
ht_control_field_pkt_type : 4,
reserved_3b : 7;
uint32_t ast_index : 16,
frame_control_field : 16;
uint32_t first_data_seq_ctrl : 16,
qos_control_field : 16;
uint32_t ht_control_field : 32;
uint32_t fcs_ok_bitmap_31_0 : 32;
uint32_t fcs_ok_bitmap_63_32 : 32;
uint32_t udp_msdu_count : 16,
tcp_msdu_count : 16;
uint32_t other_msdu_count : 16,
tcp_ack_msdu_count : 16;
uint32_t sw_response_reference_ptr : 32;
uint32_t received_qos_data_tid_bitmap : 16,
received_qos_data_tid_eosp_bitmap : 16;
uint32_t qosctrl_15_8_tid0 : 8,
qosctrl_15_8_tid1 : 8,
qosctrl_15_8_tid2 : 8,
qosctrl_15_8_tid3 : 8;
uint32_t qosctrl_15_8_tid4 : 8,
qosctrl_15_8_tid5 : 8,
qosctrl_15_8_tid6 : 8,
qosctrl_15_8_tid7 : 8;
uint32_t qosctrl_15_8_tid8 : 8,
qosctrl_15_8_tid9 : 8,
qosctrl_15_8_tid10 : 8,
qosctrl_15_8_tid11 : 8;
uint32_t qosctrl_15_8_tid12 : 8,
qosctrl_15_8_tid13 : 8,
qosctrl_15_8_tid14 : 8,
qosctrl_15_8_tid15 : 8;
uint32_t mpdu_ok_byte_count : 25,
ampdu_delim_ok_count_6_0 : 7;
uint32_t ampdu_delim_err_count : 25,
ampdu_delim_ok_count_13_7 : 7;
uint32_t mpdu_err_byte_count : 25,
ampdu_delim_ok_count_20_14 : 7;
uint32_t non_consecutive_delimiter_err : 16,
reserved_20a : 16;
uint32_t ht_control_null_field : 32;
uint32_t sw_response_reference_ptr_ext : 32;
uint32_t corrupted_due_to_fifo_delay : 1,
reserved_23a : 31;
};
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000ff80
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31
#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000
#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32
#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44
#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000
#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_MCS_LSB 45
#define RX_PPDU_END_USER_STATS_MCS_MSB 48
#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e00000000000
#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_NSS_LSB 49
#define RX_PPDU_END_USER_STATS_NSS_MSB 51
#define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e000000000000
#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 52
#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63
#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xfff0000000000000
#define RX_PPDU_END_USER_STATS_RESERVED_2A_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_RESERVED_2A_LSB 0
#define RX_PPDU_END_USER_STATS_RESERVED_2A_MSB 15
#define RX_PPDU_END_USER_STATS_RESERVED_2A_MASK 0x000000000000ffff
#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16
#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26
#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000
#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27
#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27
#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000
#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28
#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28
#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x0000000010000000
#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29
#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29
#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000
#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30
#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30
#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x0000000040000000
#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31
#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31
#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x0000000080000000
#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32
#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42
#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000
#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43
#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43
#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000
#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44
#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44
#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000
#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45
#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45
#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000
#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46
#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46
#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000
#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47
#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47
#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000
#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 48
#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 48
#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x0001000000000000
#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 49
#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 49
#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x0002000000000000
#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 50
#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 50
#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x0004000000000000
#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 51
#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 51
#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x0008000000000000
#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 52
#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 52
#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x0010000000000000
#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53
#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56
#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000
#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 57
#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63
#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xfe00000000000000
#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010
#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0
#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15
#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff
#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010
#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16
#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31
#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000
#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010
#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32
#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47
#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000
#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010
#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48
#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63
#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000
#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018
#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0
#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31
#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff
#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018
#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32
#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63
#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000
#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020
#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0
#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31
#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff
#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020
#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32
#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47
#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000
#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020
#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48
#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63
#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000
#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028
#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0
#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15
#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff
#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028
#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16
#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31
#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000
#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028
#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32
#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63
#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000
#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030
#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0
#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15
#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff
#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030
#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16
#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31
#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31
#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000
#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040
#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32
#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56
#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000
#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048
#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32
#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56
#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63
#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000
#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050
#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0
#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15
#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff
#define RX_PPDU_END_USER_STATS_RESERVED_20A_OFFSET 0x0000000000000050
#define RX_PPDU_END_USER_STATS_RESERVED_20A_LSB 16
#define RX_PPDU_END_USER_STATS_RESERVED_20A_MSB 31
#define RX_PPDU_END_USER_STATS_RESERVED_20A_MASK 0x00000000ffff0000
#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050
#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32
#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63
#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000
#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058
#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0
#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31
#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff
#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058
#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32
#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32
#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000
#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058
#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 33
#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63
#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xfffffffe00000000
#endif

194
drivers/staging/fw-api/hw/kiwi/v1/rx_ppdu_end_user_stats_ext.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
#define _RX_PPDU_END_USER_STATS_EXT_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_rxpcu_classification_overview.h"
#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8
#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4
struct rx_ppdu_end_user_stats_ext {
struct rx_rxpcu_classification_overview rxpcu_classification_details;
uint32_t fcs_ok_bitmap_95_64 : 32;
uint32_t fcs_ok_bitmap_127_96 : 32;
uint32_t fcs_ok_bitmap_159_128 : 32;
uint32_t fcs_ok_bitmap_191_160 : 32;
uint32_t fcs_ok_bitmap_223_192 : 32;
uint32_t fcs_ok_bitmap_255_224 : 32;
uint32_t corrupted_due_to_fifo_delay : 1,
reserved_7a : 31;
};
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000ff80
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31
#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31
#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff
#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018
#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32
#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32
#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000
#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018
#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33
#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63
#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000
#endif

117
drivers/staging/fw-api/hw/kiwi/v1/rx_ppdu_start.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_PPDU_START_H_
#define _RX_PPDU_START_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_PPDU_START 6
#define NUM_OF_QWORDS_RX_PPDU_START 3
struct rx_ppdu_start {
uint32_t phy_ppdu_id : 16,
preamble_time_to_rxframe : 8,
reserved_0a : 8;
uint32_t sw_phy_meta_data : 32;
uint32_t ppdu_start_timestamp_31_0 : 32;
uint32_t ppdu_start_timestamp_63_32 : 32;
uint32_t rxframe_assert_timestamp : 32;
uint32_t tlv64_padding : 32;
};
#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define RX_PPDU_START_PHY_PPDU_ID_LSB 0
#define RX_PPDU_START_PHY_PPDU_ID_MSB 15
#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff
#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000
#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16
#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23
#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000
#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000
#define RX_PPDU_START_RESERVED_0A_LSB 24
#define RX_PPDU_START_RESERVED_0A_MSB 31
#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000
#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000
#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32
#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63
#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000
#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008
#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0
#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31
#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff
#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008
#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32
#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63
#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000
#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010
#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0
#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31
#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff
#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010
#define RX_PPDU_START_TLV64_PADDING_LSB 32
#define RX_PPDU_START_TLV64_PADDING_MSB 63
#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000
#endif

354
drivers/staging/fw-api/hw/kiwi/v1/rx_ppdu_start_user_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_PPDU_START_USER_INFO_H_
#define _RX_PPDU_START_USER_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#include "receive_user_info.h"
#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 12
#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 6
struct rx_ppdu_start_user_info {
struct receive_user_info receive_user_info_details;
};
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 35
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f00000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 36
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 37
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000003000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 38
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 39
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x000000c000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x00000000000000fe
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_OFFSET 0x0000000000000010
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_LSB 0
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_MSB 31
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS0_MASK 0x00000000ffffffff
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_OFFSET 0x0000000000000010
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_LSB 32
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_MSB 63
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS1_MASK 0xffffffff00000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_OFFSET 0x0000000000000018
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_LSB 0
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_MSB 31
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS2_MASK 0x00000000ffffffff
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_OFFSET 0x0000000000000018
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_LSB 32
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_MSB 63
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS3_MASK 0xffffffff00000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_OFFSET 0x0000000000000020
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_LSB 0
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_MSB 31
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS4_MASK 0x00000000ffffffff
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_OFFSET 0x0000000000000020
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_LSB 32
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_MSB 63
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS5_MASK 0xffffffff00000000
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_OFFSET 0x0000000000000028
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_LSB 0
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_MSB 31
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS6_MASK 0x00000000ffffffff
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_OFFSET 0x0000000000000028
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_LSB 32
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_MSB 63
#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SS7_MASK 0xffffffff00000000
#endif

639
drivers/staging/fw-api/hw/kiwi/v1/rx_reo_queue.h Normal file
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@ -0,0 +1,639 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_REO_QUEUE_H_
#define _RX_REO_QUEUE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_descriptor_header.h"
#define NUM_OF_DWORDS_RX_REO_QUEUE 32
struct rx_reo_queue {
struct uniform_descriptor_header descriptor_header;
uint32_t receive_queue_number : 16,
reserved_1b : 16;
uint32_t vld : 1,
associated_link_descriptor_counter : 2,
disable_duplicate_detection : 1,
soft_reorder_enable : 1,
ac : 2,
bar : 1,
rty : 1,
chk_2k_mode : 1,
oor_mode : 1,
ba_window_size : 10,
pn_check_needed : 1,
pn_shall_be_even : 1,
pn_shall_be_uneven : 1,
pn_handling_enable : 1,
pn_size : 2,
ignore_ampdu_flag : 1,
reserved_2b : 4;
uint32_t svld : 1,
ssn : 12,
current_index : 10,
seq_2k_error_detected_flag : 1,
pn_error_detected_flag : 1,
reserved_3a : 6,
pn_valid : 1;
uint32_t pn_31_0 : 32;
uint32_t pn_63_32 : 32;
uint32_t pn_95_64 : 32;
uint32_t pn_127_96 : 32;
uint32_t last_rx_enqueue_timestamp : 32;
uint32_t last_rx_dequeue_timestamp : 32;
uint32_t ptr_to_next_aging_queue_31_0 : 32;
uint32_t ptr_to_next_aging_queue_39_32 : 8,
reserved_11a : 24;
uint32_t ptr_to_previous_aging_queue_31_0 : 32;
uint32_t ptr_to_previous_aging_queue_39_32 : 8,
reserved_13a : 24;
uint32_t rx_bitmap_31_0 : 32;
uint32_t rx_bitmap_63_32 : 32;
uint32_t rx_bitmap_95_64 : 32;
uint32_t rx_bitmap_127_96 : 32;
uint32_t rx_bitmap_159_128 : 32;
uint32_t rx_bitmap_191_160 : 32;
uint32_t rx_bitmap_223_192 : 32;
uint32_t rx_bitmap_255_224 : 32;
uint32_t rx_bitmap_287_256 : 32;
uint32_t current_mpdu_count : 7,
current_msdu_count : 25;
uint32_t last_sn_reg_index : 4,
timeout_count : 6,
forward_due_to_bar_count : 6,
duplicate_count : 16;
uint32_t frames_in_order_count : 24,
bar_received_count : 8;
uint32_t mpdu_frames_processed_count : 32;
uint32_t msdu_frames_processed_count : 32;
uint32_t total_processed_byte_count : 32;
uint32_t late_receive_mpdu_count : 12,
window_jump_2k : 4,
hole_count : 16;
uint32_t reserved_30 : 32;
uint32_t reserved_31 : 32;
};
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004
#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0
#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15
#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
#define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004
#define RX_REO_QUEUE_RESERVED_1B_LSB 16
#define RX_REO_QUEUE_RESERVED_1B_MSB 31
#define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000
#define RX_REO_QUEUE_VLD_OFFSET 0x00000008
#define RX_REO_QUEUE_VLD_LSB 0
#define RX_REO_QUEUE_VLD_MSB 0
#define RX_REO_QUEUE_VLD_MASK 0x00000001
#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008
#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1
#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2
#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006
#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008
#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3
#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3
#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008
#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008
#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4
#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4
#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010
#define RX_REO_QUEUE_AC_OFFSET 0x00000008
#define RX_REO_QUEUE_AC_LSB 5
#define RX_REO_QUEUE_AC_MSB 6
#define RX_REO_QUEUE_AC_MASK 0x00000060
#define RX_REO_QUEUE_BAR_OFFSET 0x00000008
#define RX_REO_QUEUE_BAR_LSB 7
#define RX_REO_QUEUE_BAR_MSB 7
#define RX_REO_QUEUE_BAR_MASK 0x00000080
#define RX_REO_QUEUE_RTY_OFFSET 0x00000008
#define RX_REO_QUEUE_RTY_LSB 8
#define RX_REO_QUEUE_RTY_MSB 8
#define RX_REO_QUEUE_RTY_MASK 0x00000100
#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008
#define RX_REO_QUEUE_CHK_2K_MODE_LSB 9
#define RX_REO_QUEUE_CHK_2K_MODE_MSB 9
#define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200
#define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008
#define RX_REO_QUEUE_OOR_MODE_LSB 10
#define RX_REO_QUEUE_OOR_MODE_MSB 10
#define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400
#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008
#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11
#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20
#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800
#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008
#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21
#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21
#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000
#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008
#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22
#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22
#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000
#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008
#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23
#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23
#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000
#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008
#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24
#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24
#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000
#define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008
#define RX_REO_QUEUE_PN_SIZE_LSB 25
#define RX_REO_QUEUE_PN_SIZE_MSB 26
#define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000
#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008
#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27
#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27
#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000
#define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008
#define RX_REO_QUEUE_RESERVED_2B_LSB 28
#define RX_REO_QUEUE_RESERVED_2B_MSB 31
#define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000
#define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c
#define RX_REO_QUEUE_SVLD_LSB 0
#define RX_REO_QUEUE_SVLD_MSB 0
#define RX_REO_QUEUE_SVLD_MASK 0x00000001
#define RX_REO_QUEUE_SSN_OFFSET 0x0000000c
#define RX_REO_QUEUE_SSN_LSB 1
#define RX_REO_QUEUE_SSN_MSB 12
#define RX_REO_QUEUE_SSN_MASK 0x00001ffe
#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c
#define RX_REO_QUEUE_CURRENT_INDEX_LSB 13
#define RX_REO_QUEUE_CURRENT_INDEX_MSB 22
#define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000
#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c
#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23
#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23
#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000
#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c
#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24
#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24
#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000
#define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c
#define RX_REO_QUEUE_RESERVED_3A_LSB 25
#define RX_REO_QUEUE_RESERVED_3A_MSB 30
#define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000
#define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c
#define RX_REO_QUEUE_PN_VALID_LSB 31
#define RX_REO_QUEUE_PN_VALID_MSB 31
#define RX_REO_QUEUE_PN_VALID_MASK 0x80000000
#define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010
#define RX_REO_QUEUE_PN_31_0_LSB 0
#define RX_REO_QUEUE_PN_31_0_MSB 31
#define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014
#define RX_REO_QUEUE_PN_63_32_LSB 0
#define RX_REO_QUEUE_PN_63_32_MSB 31
#define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff
#define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018
#define RX_REO_QUEUE_PN_95_64_LSB 0
#define RX_REO_QUEUE_PN_95_64_MSB 31
#define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff
#define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c
#define RX_REO_QUEUE_PN_127_96_LSB 0
#define RX_REO_QUEUE_PN_127_96_MSB 31
#define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff
#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020
#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0
#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31
#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff
#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024
#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31
#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c
#define RX_REO_QUEUE_RESERVED_11A_LSB 8
#define RX_REO_QUEUE_RESERVED_11A_MSB 31
#define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034
#define RX_REO_QUEUE_RESERVED_13A_LSB 8
#define RX_REO_QUEUE_RESERVED_13A_MSB 31
#define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffff00
#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038
#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c
#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040
#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044
#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048
#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c
#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050
#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054
#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058
#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff
#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c
#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0
#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6
#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f
#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c
#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7
#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31
#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80
#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060
#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0
#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3
#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f
#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060
#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4
#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9
#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0
#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060
#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10
#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15
#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00
#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060
#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16
#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31
#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000
#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064
#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0
#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23
#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff
#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064
#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24
#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31
#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000
#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068
#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31
#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c
#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31
#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070
#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31
#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074
#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0
#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11
#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff
#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074
#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12
#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15
#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000
#define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074
#define RX_REO_QUEUE_HOLE_COUNT_LSB 16
#define RX_REO_QUEUE_HOLE_COUNT_MSB 31
#define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000
#define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078
#define RX_REO_QUEUE_RESERVED_30_LSB 0
#define RX_REO_QUEUE_RESERVED_30_MSB 31
#define RX_REO_QUEUE_RESERVED_30_MASK 0xffffffff
#define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c
#define RX_REO_QUEUE_RESERVED_31_LSB 0
#define RX_REO_QUEUE_RESERVED_31_MSB 31
#define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff
#endif

667
drivers/staging/fw-api/hw/kiwi/v1/rx_reo_queue_ext.h Normal file
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@ -0,0 +1,667 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_REO_QUEUE_EXT_H_
#define _RX_REO_QUEUE_EXT_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_mpdu_link_ptr.h"
#include "uniform_descriptor_header.h"
#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
struct rx_reo_queue_ext {
struct uniform_descriptor_header descriptor_header;
uint32_t reserved_1a : 32;
struct rx_mpdu_link_ptr mpdu_link_pointer_0;
struct rx_mpdu_link_ptr mpdu_link_pointer_1;
struct rx_mpdu_link_ptr mpdu_link_pointer_2;
struct rx_mpdu_link_ptr mpdu_link_pointer_3;
struct rx_mpdu_link_ptr mpdu_link_pointer_4;
struct rx_mpdu_link_ptr mpdu_link_pointer_5;
struct rx_mpdu_link_ptr mpdu_link_pointer_6;
struct rx_mpdu_link_ptr mpdu_link_pointer_7;
struct rx_mpdu_link_ptr mpdu_link_pointer_8;
struct rx_mpdu_link_ptr mpdu_link_pointer_9;
struct rx_mpdu_link_ptr mpdu_link_pointer_10;
struct rx_mpdu_link_ptr mpdu_link_pointer_11;
struct rx_mpdu_link_ptr mpdu_link_pointer_12;
struct rx_mpdu_link_ptr mpdu_link_pointer_13;
struct rx_mpdu_link_ptr mpdu_link_pointer_14;
};
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004
#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0
#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31
#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#endif

124
drivers/staging/fw-api/hw/kiwi/v1/rx_rxpcu_classification_overview.h Normal file
View file

@ -0,0 +1,124 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
struct rx_rxpcu_classification_overview {
uint32_t filter_pass_mpdus : 1,
filter_pass_mpdus_fcs_ok : 1,
monitor_direct_mpdus : 1,
monitor_direct_mpdus_fcs_ok : 1,
monitor_other_mpdus : 1,
monitor_other_mpdus_fcs_ok : 1,
phyrx_abort_received : 1,
reserved_0 : 9,
phy_ppdu_id : 16;
};
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 7
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000ff80
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000
#endif

61
drivers/staging/fw-api/hw/kiwi/v1/rx_timing_offset_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RX_TIMING_OFFSET_INFO_H_
#define _RX_TIMING_OFFSET_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1
struct rx_timing_offset_info {
uint32_t residual_phase_offset : 12,
reserved : 20;
};
#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000
#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_LSB 0
#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MSB 11
#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
#define RX_TIMING_OFFSET_INFO_RESERVED_OFFSET 0x00000000
#define RX_TIMING_OFFSET_INFO_RESERVED_LSB 12
#define RX_TIMING_OFFSET_INFO_RESERVED_MSB 31
#define RX_TIMING_OFFSET_INFO_RESERVED_MASK 0xfffff000
#endif

1071
drivers/staging/fw-api/hw/kiwi/v1/rxpcu_ppdu_end_info.h Normal file
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439
drivers/staging/fw-api/hw/kiwi/v1/rxpcu_ppdu_end_layout_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_
#define _RXPCU_PPDU_END_LAYOUT_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10
struct rxpcu_ppdu_end_layout_info {
uint32_t rssi_legacy_offset : 2,
l_sig_a_offset : 6,
l_sig_b_offset : 6,
ht_sig_offset : 6,
vht_sig_a_offset : 6,
repeat_l_sig_a_offset : 6;
uint32_t he_sig_a_su_offset : 6,
he_sig_a_mu_dl_offset : 6,
he_sig_a_mu_ul_offset : 6,
generic_u_sig_offset : 6,
rssi_ht_offset : 7,
reserved_1a : 1;
uint32_t vht_sig_b_su20_offset : 7,
vht_sig_b_su40_offset : 7,
vht_sig_b_su80_offset : 7,
vht_sig_b_su160_offset : 7,
reserved_2a : 4;
uint32_t vht_sig_b_mu20_offset : 7,
vht_sig_b_mu40_offset : 7,
vht_sig_b_mu80_offset : 7,
vht_sig_b_mu160_offset : 7,
reserved_3a : 4;
uint32_t he_sig_b1_mu_offset : 7,
he_sig_b2_mu_offset : 7,
he_sig_b2_ofdma_offset : 7,
first_generic_eht_sig_offset : 7,
multiple_generic_eht_sig_included : 1,
reserved_4a : 3;
uint32_t common_user_info_offset : 7,
first_debug_info_offset : 8,
multiple_debug_info_included : 1,
first_other_receive_info_offset : 8,
multiple_other_receive_info_included : 1,
reserved_5a : 7;
uint32_t data_done_offset : 8,
generated_cbf_details_offset : 8,
pkt_end_part1_offset : 8,
location_offset : 8;
uint32_t az_integrity_data_offset : 8,
pkt_end_offset : 8,
abort_request_ack_offset : 8,
reserved_7a : 8;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
};
#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000
#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0
#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1
#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003
#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000
#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2
#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7
#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc
#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000
#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8
#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13
#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00
#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000
#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14
#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19
#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000
#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000
#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26
#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31
#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000
#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004
#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18
#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23
#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000
#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004
#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24
#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30
#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27
#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20
#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000
#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014
#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0
#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6
#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23
#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24
#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000
#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018
#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0
#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7
#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff
#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018
#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8
#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15
#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00
#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018
#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16
#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23
#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000
#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018
#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24
#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31
#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000
#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000001c
#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_LSB 0
#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MSB 7
#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff
#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c
#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8
#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15
#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00
#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c
#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16
#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23
#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31
#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff
#endif

169
drivers/staging/fw-api/hw/kiwi/v1/rxpt_classify_info.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RXPT_CLASSIFY_INFO_H_
#define _RXPT_CLASSIFY_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
struct rxpt_classify_info {
uint32_t reo_destination_indication : 5,
lmac_peer_id_msb : 2,
use_flow_id_toeplitz_clfy : 1,
pkt_selection_fp_ucast_data : 1,
pkt_selection_fp_mcast_data : 1,
pkt_selection_fp_1000 : 1,
rxdma0_source_ring_selection : 3,
rxdma0_destination_ring_selection : 3,
mcast_echo_drop_enable : 1,
wds_learning_detect_en : 1,
intrabss_check_en : 1,
use_ppe : 1,
ppe_routing_enable : 1,
reserved_0b : 10;
};
#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0
#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4
#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f
#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5
#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6
#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060
#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7
#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10
#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400
#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11
#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13
#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800
#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000
#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17
#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17
#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000
#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18
#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18
#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000
#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19
#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19
#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000
#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20
#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20
#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000
#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21
#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21
#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000
#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 22
#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31
#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xffc00000
#endif

94
drivers/staging/fw-api/hw/kiwi/v1/seq_hwio.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __SEQ_H__
#define __SEQ_H__
#include "HALhwio.h"
#define SEQ_INH(base, regtype, reg) \
SEQ_##regtype##_INH(base, reg)
#define SEQ_INMH(base, regtype, reg, mask) \
SEQ_##regtype##_INMH(base, reg, mask)
#define SEQ_INFH(base, regtype, reg, fld) \
(SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
#define SEQ_OUTH(base, regtype, reg, val) \
SEQ_##regtype##_OUTH(base, reg, val)
#define SEQ_OUTMH(base, regtype, reg, mask, val) \
SEQ_##regtype##_OUTMH(base, reg, mask, val)
#define SEQ_OUTFH(base, regtype, reg, fld, val) \
SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
typedef enum {
SEC,
MS,
US,
NS
} SEQ_TimeUnit;
extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
#endif

377
drivers/staging/fw-api/hw/kiwi/v1/tcl_data_cmd.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TCL_DATA_CMD_H_
#define _TCL_DATA_CMD_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_TCL_DATA_CMD 8
struct tcl_data_cmd {
struct buffer_addr_info buf_addr_info;
uint32_t tcl_cmd_type : 1,
buf_or_ext_desc_type : 1,
bank_id : 6,
tx_notify_frame : 3,
header_length_read_sel : 1,
buffer_timestamp : 19,
buffer_timestamp_valid : 1;
uint32_t reserved_3a : 16,
tcl_cmd_number : 16;
uint32_t data_length : 16,
ipv4_checksum_en : 1,
udp_over_ipv4_checksum_en : 1,
udp_over_ipv6_checksum_en : 1,
tcp_over_ipv4_checksum_en : 1,
tcp_over_ipv6_checksum_en : 1,
to_fw : 1,
reserved_4a : 1,
packet_offset : 9;
uint32_t hlos_tid_overwrite : 1,
flow_override_enable : 1,
who_classify_info_sel : 2,
hlos_tid : 4,
flow_override : 1,
pmac_id : 2,
reserved_5a : 13,
vdev_id : 8;
uint32_t search_index : 20,
cache_set_num : 4,
index_lookup_override : 1,
reserved_6a : 7;
uint32_t reserved_7a : 20,
ring_id : 8,
looping_count : 4;
};
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008
#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0
#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0
#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001
#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008
#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1
#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1
#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002
#define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008
#define TCL_DATA_CMD_BANK_ID_LSB 2
#define TCL_DATA_CMD_BANK_ID_MSB 7
#define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc
#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008
#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8
#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10
#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700
#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008
#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11
#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11
#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000
#define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c
#define TCL_DATA_CMD_RESERVED_3A_LSB 0
#define TCL_DATA_CMD_RESERVED_3A_MSB 15
#define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff
#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c
#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16
#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31
#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000
#define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010
#define TCL_DATA_CMD_DATA_LENGTH_LSB 0
#define TCL_DATA_CMD_DATA_LENGTH_MSB 15
#define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff
#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010
#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16
#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16
#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000
#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010
#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17
#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17
#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000
#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010
#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18
#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18
#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000
#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010
#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19
#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19
#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000
#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010
#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20
#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20
#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000
#define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010
#define TCL_DATA_CMD_TO_FW_LSB 21
#define TCL_DATA_CMD_TO_FW_MSB 21
#define TCL_DATA_CMD_TO_FW_MASK 0x00200000
#define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010
#define TCL_DATA_CMD_RESERVED_4A_LSB 22
#define TCL_DATA_CMD_RESERVED_4A_MSB 22
#define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000
#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010
#define TCL_DATA_CMD_PACKET_OFFSET_LSB 23
#define TCL_DATA_CMD_PACKET_OFFSET_MSB 31
#define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000
#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014
#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0
#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0
#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001
#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014
#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1
#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1
#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002
#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014
#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2
#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3
#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c
#define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014
#define TCL_DATA_CMD_HLOS_TID_LSB 4
#define TCL_DATA_CMD_HLOS_TID_MSB 7
#define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0
#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014
#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8
#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8
#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100
#define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014
#define TCL_DATA_CMD_PMAC_ID_LSB 9
#define TCL_DATA_CMD_PMAC_ID_MSB 10
#define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600
#define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014
#define TCL_DATA_CMD_RESERVED_5A_LSB 11
#define TCL_DATA_CMD_RESERVED_5A_MSB 23
#define TCL_DATA_CMD_RESERVED_5A_MASK 0x00fff800
#define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014
#define TCL_DATA_CMD_VDEV_ID_LSB 24
#define TCL_DATA_CMD_VDEV_ID_MSB 31
#define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000
#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018
#define TCL_DATA_CMD_SEARCH_INDEX_LSB 0
#define TCL_DATA_CMD_SEARCH_INDEX_MSB 19
#define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff
#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018
#define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20
#define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23
#define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000
#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018
#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24
#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24
#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000
#define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018
#define TCL_DATA_CMD_RESERVED_6A_LSB 25
#define TCL_DATA_CMD_RESERVED_6A_MSB 31
#define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000
#define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c
#define TCL_DATA_CMD_RESERVED_7A_LSB 0
#define TCL_DATA_CMD_RESERVED_7A_MSB 19
#define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff
#define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c
#define TCL_DATA_CMD_RING_ID_LSB 20
#define TCL_DATA_CMD_RING_ID_MSB 27
#define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000
#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c
#define TCL_DATA_CMD_LOOPING_COUNT_LSB 28
#define TCL_DATA_CMD_LOOPING_COUNT_MSB 31
#define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000
#endif

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drivers/staging/fw-api/hw/kiwi/v1/tcl_gse_cmd.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TCL_GSE_CMD_H_
#define _TCL_GSE_CMD_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_TCL_GSE_CMD 8
struct tcl_gse_cmd {
uint32_t control_buffer_addr_31_0 : 32;
uint32_t control_buffer_addr_39_32 : 8,
gse_ctrl : 4,
gse_sel : 1,
status_destination_ring_id : 1,
swap : 1,
index_search_en : 1,
cache_set_num : 4,
reserved_1a : 12;
uint32_t tcl_cmd_type : 1,
reserved_2a : 31;
uint32_t cmd_meta_data_31_0 : 32;
uint32_t cmd_meta_data_63_32 : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 20,
ring_id : 8,
looping_count : 4;
};
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004
#define TCL_GSE_CMD_GSE_CTRL_LSB 8
#define TCL_GSE_CMD_GSE_CTRL_MSB 11
#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00
#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004
#define TCL_GSE_CMD_GSE_SEL_LSB 12
#define TCL_GSE_CMD_GSE_SEL_MSB 12
#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000
#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13
#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13
#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000
#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004
#define TCL_GSE_CMD_SWAP_LSB 14
#define TCL_GSE_CMD_SWAP_MSB 14
#define TCL_GSE_CMD_SWAP_MASK 0x00004000
#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004
#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15
#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15
#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000
#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004
#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16
#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19
#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000
#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004
#define TCL_GSE_CMD_RESERVED_1A_LSB 20
#define TCL_GSE_CMD_RESERVED_1A_MSB 31
#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000
#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008
#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0
#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0
#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001
#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008
#define TCL_GSE_CMD_RESERVED_2A_LSB 1
#define TCL_GSE_CMD_RESERVED_2A_MSB 31
#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe
#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c
#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0
#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31
#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff
#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010
#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0
#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31
#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff
#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014
#define TCL_GSE_CMD_RESERVED_5A_LSB 0
#define TCL_GSE_CMD_RESERVED_5A_MSB 31
#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff
#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018
#define TCL_GSE_CMD_RESERVED_6A_LSB 0
#define TCL_GSE_CMD_RESERVED_6A_MSB 31
#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff
#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c
#define TCL_GSE_CMD_RESERVED_7A_LSB 0
#define TCL_GSE_CMD_RESERVED_7A_MSB 19
#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff
#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c
#define TCL_GSE_CMD_RING_ID_LSB 20
#define TCL_GSE_CMD_RING_ID_MSB 27
#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000
#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c
#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28
#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31
#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000
#endif

187
drivers/staging/fw-api/hw/kiwi/v1/tcl_status_ring.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TCL_STATUS_RING_H_
#define _TCL_STATUS_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_TCL_STATUS_RING 8
struct tcl_status_ring {
uint32_t gse_ctrl : 4,
ase_fse_sel : 1,
cache_op_res : 2,
index_search_en : 1,
msdu_cnt_n : 24;
uint32_t msdu_byte_cnt_n : 32;
uint32_t msdu_timestmp_n : 32;
uint32_t cmd_meta_data_31_0 : 32;
uint32_t cmd_meta_data_63_32 : 32;
uint32_t hash_indx_val : 20,
cache_set_num : 4,
reserved_5a : 8;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 20,
ring_id : 8,
looping_count : 4;
};
#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000
#define TCL_STATUS_RING_GSE_CTRL_LSB 0
#define TCL_STATUS_RING_GSE_CTRL_MSB 3
#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f
#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000
#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4
#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4
#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010
#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000
#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5
#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6
#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060
#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000
#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7
#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7
#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080
#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000
#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8
#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31
#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00
#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004
#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0
#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31
#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff
#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008
#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0
#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31
#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff
#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c
#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0
#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31
#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff
#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010
#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0
#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31
#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff
#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014
#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0
#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19
#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff
#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014
#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20
#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23
#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000
#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014
#define TCL_STATUS_RING_RESERVED_5A_LSB 24
#define TCL_STATUS_RING_RESERVED_5A_MSB 31
#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000
#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018
#define TCL_STATUS_RING_RESERVED_6A_LSB 0
#define TCL_STATUS_RING_RESERVED_6A_MSB 31
#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff
#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c
#define TCL_STATUS_RING_RESERVED_7A_LSB 0
#define TCL_STATUS_RING_RESERVED_7A_MSB 19
#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff
#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c
#define TCL_STATUS_RING_RING_ID_LSB 20
#define TCL_STATUS_RING_RING_ID_MSB 27
#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000
#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c
#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28
#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31
#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000
#endif

288
drivers/staging/fw-api/hw/kiwi/v1/tlv_hdr.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TLV_HDR_H_
#define _TLV_HDR_H_
#if !defined(__ASSEMBLER__)
#endif
#define _TLV_USERID_WIDTH_ 6
#define _TLV_DATA_WIDTH_ 32
#define _TLV_TAG_WIDTH_ 9
#define _TLV_MRV_EN_LEN_WIDTH_ 9
#define _TLV_MRV_DIS_LEN_WIDTH_ 12
#define _TLV_16_DATA_WIDTH_ 16
#define _TLV_16_TAG_WIDTH_ 5
#define _TLV_16_LEN_WIDTH_ 4
#define _TLV_CTAG_WIDTH_ 5
#define _TLV_44_DATA_WIDTH_ 44
#define _TLV_64_DATA_WIDTH_ 64
#define _TLV_76_DATA_WIDTH_ 64
#define _TLV_CDATA_WIDTH_ 32
#define _TLV_CDATA_76_WIDTH_ 64
struct tlv_usr_16_tlword_t {
uint16_t tlv_cflg_reserved : 1,
tlv_tag : _TLV_16_TAG_WIDTH_,
tlv_len : _TLV_16_LEN_WIDTH_,
tlv_usrid : _TLV_USERID_WIDTH_;
};
struct tlv_16_tlword_t {
uint16_t tlv_cflg_reserved : 1,
tlv_len : _TLV_16_LEN_WIDTH_,
tlv_tag : _TLV_16_TAG_WIDTH_,
tlv_reserved : 6;
};
struct tlv_mlo_usr_32_tlword_t {
uint32_t tlv_cflg_reserved : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
tlv_dst_linkid : 3,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_usrid : _TLV_USERID_WIDTH_;
};
struct tlv_mlo_32_tlword_t {
uint32_t tlv_cflg_reserved : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
tlv_dst_linkid : 3,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_reserved : 6;
};
struct tlv_mlo_usr_64_tlword_t {
uint64_t tlv_cflg_reserved : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
tlv_dst_linkid : 3,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_usrid : _TLV_USERID_WIDTH_,
tlv_reserved : 32;
};
struct tlv_mlo_64_tlword_t {
uint64_t tlv_cflg_reserved : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
tlv_dst_linkid : 3,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_reserved : 38;
};
struct tlv_mlo_usr_44_tlword_t {
uint64_t tlv_compression : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
tlv_dst_linkid : 3,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_usrid : _TLV_USERID_WIDTH_,
tlv_reserved : 10,
pad_44to64_bit : 22;
};
struct tlv_mlo_44_tlword_t {
uint64_t tlv_compression : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
tlv_dst_linkid : 3,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_reserved : 16,
pad_44to64_bit : 22;
};
struct tlv_mlo_usr_76_tlword_t {
uint64_t tlv_compression : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
tlv_dst_linkid : 3,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_usrid : _TLV_USERID_WIDTH_,
tlv_reserved : 32;
uint64_t pad_64to128_bit : 64;
};
struct tlv_mlo_76_tlword_t {
uint64_t tlv_compression : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
tlv_dst_linkid : 3,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_reserved : 38;
uint64_t pad_64to128_bit : 64;
};
struct tlv_mac_usr_32_tlword_t {
uint32_t tlv_cflg_reserved : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_usrid : _TLV_USERID_WIDTH_;
};
struct tlv_mac_32_tlword_t {
uint32_t tlv_cflg_reserved : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_reserved : 6;
};
struct tlv_mac_usr_64_tlword_t {
uint64_t tlv_cflg_reserved : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_usrid : _TLV_USERID_WIDTH_,
tlv_reserved : 32;
};
struct tlv_mac_64_tlword_t {
uint64_t tlv_cflg_reserved : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_reserved : 38;
};
struct tlv_mac_usr_44_tlword_t {
uint64_t tlv_compression : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_usrid : _TLV_USERID_WIDTH_,
tlv_reserved : 10,
pad_44to64_bit : 22;
};
struct tlv_mac_44_tlword_t {
uint64_t tlv_compression : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_reserved : 16,
pad_44to64_bit : 22;
};
struct tlv_mac_usr_76_tlword_t {
uint64_t tlv_compression : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_usrid : _TLV_USERID_WIDTH_,
tlv_reserved : 32;
uint64_t pad_64to128_bit : 64;
};
struct tlv_mac_76_tlword_t {
uint64_t tlv_compression : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_reserved : 38;
uint64_t pad_64to128_bit : 64;
};
struct tlv_usr_c_44_tlword_t {
uint64_t tlv_compression : 1,
tlv_ctag : _TLV_CTAG_WIDTH_,
tlv_usrid : _TLV_USERID_WIDTH_,
tlv_cdata : _TLV_CDATA_WIDTH_,
pad_44to64_bit : 20;
};
struct tlv_usr_c_76_tlword_t {
uint64_t tlv_compression : 1,
tlv_ctag : _TLV_CTAG_WIDTH_,
tlv_usrid : _TLV_USERID_WIDTH_,
tlv_cdata_lower_52 : 52;
uint64_t tlv_cdata_upper_12 : 12,
pad_76to128_bit : 52;
};
struct tlv_usr_32_hdr {
uint64_t tlv_cflg_reserved : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_usrid : _TLV_USERID_WIDTH_,
tlv_reserved : 32;
};
struct tlv_32_hdr {
uint64_t tlv_cflg_reserved : 1,
tlv_tag : _TLV_TAG_WIDTH_,
tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
tlv_src_linkid : 3,
tlv_mrv : 1,
tlv_reserved : 38;
};
#endif

515
drivers/staging/fw-api/hw/kiwi/v1/tlv_tag_def.h Normal file
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/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TLV_TAG_DEF_
#define _TLV_TAG_DEF_
typedef enum {
WIFIMACTX_CBF_START_E = 0,
WIFIPHYRX_DATA_E = 1,
WIFIPHYRX_CBF_DATA_RESP_E = 2,
WIFIPHYRX_ABORT_REQUEST_E = 3,
WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4,
WIFIMACTX_DATA_RESP_E = 5,
WIFIMACTX_CBF_DATA_E = 6,
WIFIMACTX_CBF_DONE_E = 7,
WIFIPHYRX_LMR_DATA_RESP_E = 8,
WIFIRXPCU_TO_UCODE_START_E = 9,
WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10,
WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11,
WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12,
WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13,
WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14,
WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15,
WIFIRXPCU_TO_UCODE_END_E = 16,
WIFIMACRX_CBF_READ_REQUEST_E = 32,
WIFIMACRX_CBF_DATA_REQUEST_E = 33,
WIFIMACRX_EXPECT_NDP_RECEPTION_E = 34,
WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 35,
WIFIMACRX_NDP_TIMEOUT_E = 36,
WIFIMACRX_ABORT_ACK_E = 37,
WIFIMACRX_REQ_IMPLICIT_FB_E = 38,
WIFIMACRX_CHAIN_MASK_E = 39,
WIFIMACRX_NAP_USER_E = 40,
WIFIMACRX_ABORT_REQUEST_E = 41,
WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 42,
WIFIPHYTX_ABORT_ACK_E = 43,
WIFIPHYTX_ABORT_REQUEST_E = 44,
WIFIPHYTX_PKT_END_E = 45,
WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 46,
WIFIPHYTX_REQUEST_CTRL_INFO_E = 47,
WIFIPHYTX_DATA_REQUEST_E = 48,
WIFIPHYTX_BF_CV_LOADING_DONE_E = 49,
WIFIPHYTX_NAP_ACK_E = 50,
WIFIPHYTX_NAP_DONE_E = 51,
WIFIPHYTX_OFF_ACK_E = 52,
WIFIPHYTX_ON_ACK_E = 53,
WIFIPHYTX_SYNTH_OFF_ACK_E = 54,
WIFIPHYTX_DEBUG16_E = 55,
WIFIMACTX_ABORT_REQUEST_E = 56,
WIFIMACTX_ABORT_ACK_E = 57,
WIFIMACTX_PKT_END_E = 58,
WIFIMACTX_PRE_PHY_DESC_E = 59,
WIFIMACTX_BF_PARAMS_COMMON_E = 60,
WIFIMACTX_BF_PARAMS_PER_USER_E = 61,
WIFIMACTX_PREFETCH_CV_E = 62,
WIFIMACTX_USER_DESC_COMMON_E = 63,
WIFIMACTX_USER_DESC_PER_USER_E = 64,
WIFIEXAMPLE_USER_TLV_16_E = 65,
WIFIEXAMPLE_TLV_16_E = 66,
WIFIMACTX_PHY_OFF_E = 67,
WIFIMACTX_PHY_ON_E = 68,
WIFIMACTX_SYNTH_OFF_E = 69,
WIFIMACTX_EXPECT_CBF_COMMON_E = 70,
WIFIMACTX_EXPECT_CBF_PER_USER_E = 71,
WIFIMACTX_PHY_DESC_E = 72,
WIFIMACTX_L_SIG_A_E = 73,
WIFIMACTX_L_SIG_B_E = 74,
WIFIMACTX_HT_SIG_E = 75,
WIFIMACTX_VHT_SIG_A_E = 76,
WIFIMACTX_VHT_SIG_B_SU20_E = 77,
WIFIMACTX_VHT_SIG_B_SU40_E = 78,
WIFIMACTX_VHT_SIG_B_SU80_E = 79,
WIFIMACTX_VHT_SIG_B_SU160_E = 80,
WIFIMACTX_VHT_SIG_B_MU20_E = 81,
WIFIMACTX_VHT_SIG_B_MU40_E = 82,
WIFIMACTX_VHT_SIG_B_MU80_E = 83,
WIFIMACTX_VHT_SIG_B_MU160_E = 84,
WIFIMACTX_SERVICE_E = 85,
WIFIMACTX_HE_SIG_A_SU_E = 86,
WIFIMACTX_HE_SIG_A_MU_DL_E = 87,
WIFIMACTX_HE_SIG_A_MU_UL_E = 88,
WIFIMACTX_HE_SIG_B1_MU_E = 89,
WIFIMACTX_HE_SIG_B2_MU_E = 90,
WIFIMACTX_HE_SIG_B2_OFDMA_E = 91,
WIFIMACTX_DELETE_CV_E = 92,
WIFIMACTX_MU_UPLINK_COMMON_E = 93,
WIFIMACTX_MU_UPLINK_USER_SETUP_E = 94,
WIFIMACTX_OTHER_TRANSMIT_INFO_E = 95,
WIFIMACTX_PHY_NAP_E = 96,
WIFIMACTX_DEBUG_E = 97,
WIFIPHYRX_ABORT_ACK_E = 98,
WIFIPHYRX_GENERATED_CBF_DETAILS_E = 99,
WIFIPHYRX_RSSI_LEGACY_E = 100,
WIFIPHYRX_RSSI_HT_E = 101,
WIFIPHYRX_USER_INFO_E = 102,
WIFIPHYRX_PKT_END_E = 103,
WIFIPHYRX_DEBUG_E = 104,
WIFIPHYRX_CBF_TRANSFER_DONE_E = 105,
WIFIPHYRX_CBF_TRANSFER_ABORT_E = 106,
WIFIPHYRX_L_SIG_A_E = 107,
WIFIPHYRX_L_SIG_B_E = 108,
WIFIPHYRX_HT_SIG_E = 109,
WIFIPHYRX_VHT_SIG_A_E = 110,
WIFIPHYRX_VHT_SIG_B_SU20_E = 111,
WIFIPHYRX_VHT_SIG_B_SU40_E = 112,
WIFIPHYRX_VHT_SIG_B_SU80_E = 113,
WIFIPHYRX_VHT_SIG_B_SU160_E = 114,
WIFIPHYRX_VHT_SIG_B_MU20_E = 115,
WIFIPHYRX_VHT_SIG_B_MU40_E = 116,
WIFIPHYRX_VHT_SIG_B_MU80_E = 117,
WIFIPHYRX_VHT_SIG_B_MU160_E = 118,
WIFIPHYRX_HE_SIG_A_SU_E = 119,
WIFIPHYRX_HE_SIG_A_MU_DL_E = 120,
WIFIPHYRX_HE_SIG_A_MU_UL_E = 121,
WIFIPHYRX_HE_SIG_B1_MU_E = 122,
WIFIPHYRX_HE_SIG_B2_MU_E = 123,
WIFIPHYRX_HE_SIG_B2_OFDMA_E = 124,
WIFIPHYRX_OTHER_RECEIVE_INFO_E = 125,
WIFIPHYRX_COMMON_USER_INFO_E = 126,
WIFIPHYRX_DATA_DONE_E = 127,
WIFICOEX_TX_REQ_E = 128,
WIFIDUMMY_E = 129,
WIFIEXAMPLE_TLV_32_NAME_E = 130,
WIFIMPDU_LIMIT_E = 131,
WIFINA_LENGTH_END_E = 132,
WIFIOLE_BUF_STATUS_E = 133,
WIFIPCU_PPDU_SETUP_DONE_E = 134,
WIFIPCU_PPDU_SETUP_END_E = 135,
WIFIPCU_PPDU_SETUP_INIT_E = 136,
WIFIPCU_PPDU_SETUP_START_E = 137,
WIFIPDG_FES_SETUP_E = 138,
WIFIPDG_RESPONSE_E = 139,
WIFIPDG_TX_REQ_E = 140,
WIFISCH_WAIT_INSTR_E = 141,
WIFITQM_FLOW_EMPTY_STATUS_E = 143,
WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 144,
WIFITQM_GEN_MPDU_LENGTH_LIST_E = 145,
WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 146,
WIFITQM_GEN_MPDUS_E = 147,
WIFITQM_GEN_MPDUS_STATUS_E = 148,
WIFITQM_REMOVE_MPDU_E = 149,
WIFITQM_REMOVE_MPDU_STATUS_E = 150,
WIFITQM_REMOVE_MSDU_E = 151,
WIFITQM_REMOVE_MSDU_STATUS_E = 152,
WIFITQM_UPDATE_TX_MPDU_COUNT_E = 153,
WIFITQM_WRITE_CMD_E = 154,
WIFIOFDMA_TRIGGER_DETAILS_E = 155,
WIFITX_DATA_E = 156,
WIFITX_FES_SETUP_E = 157,
WIFIRX_PACKET_E = 158,
WIFIEXPECTED_RESPONSE_E = 159,
WIFITX_MPDU_END_E = 160,
WIFITX_MPDU_START_E = 161,
WIFITX_MSDU_END_E = 162,
WIFITX_MSDU_START_E = 163,
WIFITX_SW_MODE_SETUP_E = 164,
WIFITXPCU_BUFFER_STATUS_E = 165,
WIFITXPCU_USER_BUFFER_STATUS_E = 166,
WIFIDATA_TO_TIME_CONFIG_E = 167,
WIFIEXAMPLE_USER_TLV_32_E = 168,
WIFIMPDU_INFO_E = 169,
WIFIPDG_USER_SETUP_E = 170,
WIFITX_11AH_SETUP_E = 171,
WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 172,
WIFITX_PEER_ENTRY_E = 173,
WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 174,
WIFIEXAMPLE_USER_TLV_44_E = 175,
WIFITX_FLUSH_E = 176,
WIFITX_FLUSH_REQ_E = 177,
WIFITQM_WRITE_CMD_STATUS_E = 178,
WIFITQM_GET_MPDU_QUEUE_STATS_E = 179,
WIFITQM_GET_MSDU_FLOW_STATS_E = 180,
WIFIEXAMPLE_USER_CTLV_44_E = 181,
WIFITX_FES_STATUS_START_E = 182,
WIFITX_FES_STATUS_USER_PPDU_E = 183,
WIFITX_FES_STATUS_USER_RESPONSE_E = 184,
WIFITX_FES_STATUS_END_E = 185,
WIFIRX_TRIG_INFO_E = 186,
WIFIRXPCU_TX_SETUP_CLEAR_E = 187,
WIFIRX_FRAME_BITMAP_REQ_E = 188,
WIFIRX_FRAME_BITMAP_ACK_E = 189,
WIFICOEX_RX_STATUS_E = 190,
WIFIRX_START_PARAM_E = 191,
WIFIRX_PPDU_START_E = 192,
WIFIRX_PPDU_END_E = 193,
WIFIRX_MPDU_START_E = 194,
WIFIRX_MPDU_END_E = 195,
WIFIRX_MSDU_START_E = 196,
WIFIRX_MSDU_END_E = 197,
WIFIRX_ATTENTION_E = 198,
WIFIRECEIVED_RESPONSE_INFO_E = 199,
WIFIRX_PHY_SLEEP_E = 200,
WIFIRX_HEADER_E = 201,
WIFIRX_PEER_ENTRY_E = 202,
WIFIRX_FLUSH_E = 203,
WIFIRX_RESPONSE_REQUIRED_INFO_E = 204,
WIFIRX_FRAMELESS_BAR_DETAILS_E = 205,
WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 206,
WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 207,
WIFITX_CBF_INFO_E = 208,
WIFIPCU_PPDU_SETUP_USER_E = 209,
WIFIRX_MPDU_PCU_START_E = 210,
WIFIRX_PM_INFO_E = 211,
WIFIRX_USER_PPDU_END_E = 212,
WIFIRX_PRE_PPDU_START_E = 213,
WIFIRX_PREAMBLE_E = 214,
WIFITX_FES_SETUP_COMPLETE_E = 215,
WIFITX_LAST_MPDU_FETCHED_E = 216,
WIFITXDMA_STOP_REQUEST_E = 217,
WIFIRXPCU_SETUP_E = 218,
WIFIRXPCU_USER_SETUP_E = 219,
WIFITX_FES_STATUS_ACK_OR_BA_E = 220,
WIFITQM_ACKED_MPDU_E = 221,
WIFICOEX_TX_RESP_E = 222,
WIFICOEX_TX_STATUS_E = 223,
WIFIMACTX_COEX_PHY_CTRL_E = 224,
WIFICOEX_STATUS_BROADCAST_E = 225,
WIFIRESPONSE_START_STATUS_E = 226,
WIFIRESPONSE_END_STATUS_E = 227,
WIFICRYPTO_STATUS_E = 228,
WIFIRECEIVED_TRIGGER_INFO_E = 229,
WIFICOEX_TX_STOP_CTRL_E = 230,
WIFIRX_PPDU_ACK_REPORT_E = 231,
WIFIRX_PPDU_NO_ACK_REPORT_E = 232,
WIFISCH_COEX_STATUS_E = 233,
WIFISCHEDULER_COMMAND_STATUS_E = 234,
WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 235,
WIFITX_FES_STATUS_PROT_E = 236,
WIFITX_FES_STATUS_START_PPDU_E = 237,
WIFITX_FES_STATUS_START_PROT_E = 238,
WIFITXPCU_PHYTX_DEBUG32_E = 239,
WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 240,
WIFITX_MPDU_COUNT_TRANSFER_END_E = 241,
WIFIWHO_ANCHOR_OFFSET_E = 242,
WIFIWHO_ANCHOR_VALUE_E = 243,
WIFIWHO_CCE_INFO_E = 244,
WIFIWHO_COMMIT_E = 245,
WIFIWHO_COMMIT_DONE_E = 246,
WIFIWHO_FLUSH_E = 247,
WIFIWHO_L2_LLC_E = 248,
WIFIWHO_L2_PAYLOAD_E = 249,
WIFIWHO_L3_CHECKSUM_E = 250,
WIFIWHO_L3_INFO_E = 251,
WIFIWHO_L4_CHECKSUM_E = 252,
WIFIWHO_L4_INFO_E = 253,
WIFIWHO_MSDU_E = 254,
WIFIWHO_MSDU_MISC_E = 255,
WIFIWHO_PACKET_DATA_E = 256,
WIFIWHO_PACKET_HDR_E = 257,
WIFIWHO_PPDU_END_E = 258,
WIFIWHO_PPDU_START_E = 259,
WIFIWHO_TSO_E = 260,
WIFIWHO_WMAC_HEADER_PV0_E = 261,
WIFIWHO_WMAC_HEADER_PV1_E = 262,
WIFIWHO_WMAC_IV_E = 263,
WIFIMPDU_INFO_END_E = 264,
WIFIMPDU_INFO_BITMAP_E = 265,
WIFITX_QUEUE_EXTENSION_E = 266,
WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 267,
WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 268,
WIFITQM_ACKED_MPDU_STATUS_E = 269,
WIFITQM_ADD_MSDU_STATUS_E = 270,
WIFITQM_LIST_GEN_DONE_E = 271,
WIFIWHO_TERMINATE_E = 272,
WIFITX_LAST_MPDU_END_E = 273,
WIFITX_CV_DATA_E = 274,
WIFIPPDU_TX_END_E = 275,
WIFIPROT_TX_END_E = 276,
WIFIMPDU_INFO_GLOBAL_END_E = 277,
WIFITQM_SCH_INSTR_GLOBAL_END_E = 278,
WIFIRX_PPDU_END_USER_STATS_E = 279,
WIFIRX_PPDU_END_USER_STATS_EXT_E = 280,
WIFIREO_GET_QUEUE_STATS_E = 281,
WIFIREO_FLUSH_QUEUE_E = 282,
WIFIREO_FLUSH_CACHE_E = 283,
WIFIREO_UNBLOCK_CACHE_E = 284,
WIFIREO_GET_QUEUE_STATS_STATUS_E = 285,
WIFIREO_FLUSH_QUEUE_STATUS_E = 286,
WIFIREO_FLUSH_CACHE_STATUS_E = 287,
WIFIREO_UNBLOCK_CACHE_STATUS_E = 288,
WIFITQM_FLUSH_CACHE_E = 289,
WIFITQM_UNBLOCK_CACHE_E = 290,
WIFITQM_FLUSH_CACHE_STATUS_E = 291,
WIFITQM_UNBLOCK_CACHE_STATUS_E = 292,
WIFIRX_PPDU_END_STATUS_DONE_E = 293,
WIFIRX_STATUS_BUFFER_DONE_E = 294,
WIFITX_DATA_SYNC_E = 297,
WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 298,
WIFITQM_GET_MPDU_HEAD_INFO_E = 299,
WIFITQM_SYNC_CMD_E = 300,
WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 301,
WIFITQM_SYNC_CMD_STATUS_E = 302,
WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 303,
WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 304,
WIFIREO_FLUSH_TIMEOUT_LIST_E = 305,
WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 306,
WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 307,
WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 308,
WIFIEXAMPLE_USER_TLV_32_NAME_E = 309,
WIFIRX_PPDU_START_USER_INFO_E = 310,
WIFIRX_RING_MASK_E = 311,
WIFICOEX_MAC_NAP_E = 312,
WIFIRXPCU_PPDU_END_INFO_E = 313,
WIFIWHO_MESH_CONTROL_E = 314,
WIFIPDG_SW_MODE_BW_START_E = 315,
WIFIPDG_SW_MODE_BW_END_E = 316,
WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 317,
WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 318,
WIFISCHEDULER_END_E = 319,
WIFIRX_PPDU_START_DROPPED_E = 320,
WIFIRX_PPDU_END_DROPPED_E = 321,
WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 322,
WIFIRX_MPDU_START_DROPPED_E = 323,
WIFIRX_MSDU_START_DROPPED_E = 324,
WIFIRX_MSDU_END_DROPPED_E = 325,
WIFIRX_MPDU_END_DROPPED_E = 326,
WIFIRX_ATTENTION_DROPPED_E = 327,
WIFITXPCU_USER_SETUP_E = 328,
WIFIRXPCU_USER_SETUP_EXT_E = 329,
WIFICMD_PART_0_END_E = 330,
WIFIMACTX_SYNTH_ON_E = 331,
WIFISCH_CRITICAL_TLV_REFERENCE_E = 332,
WIFITQM_MPDU_GLOBAL_START_E = 333,
WIFIEXAMPLE_TLV_32_E = 334,
WIFITQM_UPDATE_TX_MSDU_FLOW_E = 335,
WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 336,
WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 337,
WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 338,
WIFIREO_UPDATE_RX_REO_QUEUE_E = 339,
WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 340,
WIFITQM_2_SCH_MPDU_AVAILABLE_E = 341,
WIFIPDG_TRIG_RESPONSE_E = 342,
WIFITRIGGER_RESPONSE_TX_DONE_E = 343,
WIFIABORT_FROM_PHYRX_DETAILS_E = 344,
WIFISCH_TQM_CMD_WRAPPER_E = 345,
WIFIMPDUS_AVAILABLE_E = 346,
WIFIRECEIVED_RESPONSE_INFO_PART2_E = 347,
WIFIPHYRX_TX_START_TIMING_E = 348,
WIFITXPCU_PREAMBLE_DONE_E = 349,
WIFINDP_PREAMBLE_DONE_E = 350,
WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 351,
WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 352,
WIFIMACTX_CLEAR_PREV_TX_INFO_E = 353,
WIFITX_PUNCTURE_SETUP_E = 354,
WIFIR2R_STATUS_END_E = 355,
WIFIMACTX_PREFETCH_CV_COMMON_E = 356,
WIFIEND_OF_FLUSH_MARKER_E = 357,
WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 358,
WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 359,
WIFIRECEIVED_RESPONSE_USER_7_0_E = 360,
WIFIRECEIVED_RESPONSE_USER_15_8_E = 361,
WIFIRECEIVED_RESPONSE_USER_23_16_E = 362,
WIFIRECEIVED_RESPONSE_USER_31_24_E = 363,
WIFIRECEIVED_RESPONSE_USER_36_32_E = 364,
WIFITX_LOOPBACK_SETUP_E = 365,
WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 366,
WIFISCH_WAIT_INSTR_TX_PATH_E = 367,
WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 368,
WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 369,
WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 370,
WIFITX_WUR_DATA_E = 371,
WIFIRX_PPDU_END_START_E = 372,
WIFIRX_PPDU_END_MIDDLE_E = 373,
WIFIRX_PPDU_END_LAST_E = 374,
WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 375,
WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 376,
WIFISRP_INFO_E = 377,
WIFIOBSS_SR_INFO_E = 378,
WIFISCHEDULER_SW_MSG_STATUS_E = 379,
WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 380,
WIFIRXPCU_SETUP_COMPLETE_E = 381,
WIFISNOOP_PPDU_START_E = 382,
WIFISNOOP_MPDU_USR_DBG_INFO_E = 383,
WIFISNOOP_MSDU_USR_DBG_INFO_E = 384,
WIFISNOOP_MSDU_USR_DATA_E = 385,
WIFISNOOP_MPDU_USR_STAT_INFO_E = 386,
WIFISNOOP_PPDU_END_E = 387,
WIFISNOOP_SPARE_E = 388,
WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 390,
WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 391,
WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 392,
WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 393,
WIFISCH_TLV_WRAPPER_E = 394,
WIFISCHEDULER_STATUS_WRAPPER_E = 395,
WIFIMPDU_INFO_6X_E = 396,
WIFIMACTX_11AZ_USER_DESC_PER_USER_E = 397,
WIFIMACTX_U_SIG_EHT_SU_MU_E = 398,
WIFIMACTX_U_SIG_EHT_TB_E = 399,
WIFIPHYRX_U_SIG_EHT_SU_MU_E = 403,
WIFIPHYRX_U_SIG_EHT_TB_E = 404,
WIFIMACRX_LMR_READ_REQUEST_E = 408,
WIFIMACRX_LMR_DATA_REQUEST_E = 409,
WIFIPHYRX_LMR_TRANSFER_DONE_E = 410,
WIFIPHYRX_LMR_TRANSFER_ABORT_E = 411,
WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 412,
WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 413,
WIFIPHYRX_USER_INFO_MU_UL_E = 414,
WIFIMPDU_QUEUE_OVERVIEW_E = 415,
WIFISCHEDULER_NAV_INFO_E = 416,
WIFILMR_PEER_ENTRY_E = 418,
WIFILMR_MPDU_START_E = 419,
WIFILMR_DATA_E = 420,
WIFILMR_MPDU_END_E = 421,
WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 422,
WIFIRX_FRAME_1K_BITMAP_ACK_E = 423,
WIFITX_FES_STATUS_1K_BA_E = 424,
WIFITQM_ACKED_1K_MPDU_E = 425,
WIFIMACRX_INBSS_OBSS_IND_E = 426,
WIFIPHYRX_LOCATION_E = 427,
WIFIMLO_TX_NOTIFICATION_SU_E = 428,
WIFIMLO_TX_NOTIFICATION_MU_E = 429,
WIFIMLO_TX_REQ_SU_E = 430,
WIFIMLO_TX_REQ_MU_E = 431,
WIFIMLO_TX_RESP_E = 432,
WIFIMLO_RX_NOTIFICATION_E = 433,
WIFIMLO_BKOFF_TRUNC_REQ_E = 434,
WIFIMLO_TBTT_NOTIFICATION_E = 435,
WIFIMLO_MESSAGE_E = 436,
WIFIMLO_TS_SYNC_MSG_E = 437,
WIFIMLO_FES_SETUP_E = 438,
WIFIMLO_PDG_FES_SETUP_SU_E = 439,
WIFIMLO_PDG_FES_SETUP_MU_E = 440,
WIFIMPDU_INFO_1K_BITMAP_E = 441,
WIFIMON_BUFFER_ADDR_E = 442,
WIFITX_FRAG_STATE_E = 443,
WIFIMACTX_EHT_SIG_USR_OFDMA_E = 446,
WIFIPHYRX_EHT_SIG_CMN_PUNC_E = 448,
WIFIPHYRX_EHT_SIG_CMN_NO_PUNC_E = 449,
WIFIPHYRX_EHT_SIG_CMN_OFDMA_E = 450,
WIFIPHYRX_EHT_SIG_CMN_UNCOMP_E = 451,
WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 454,
WIFIPHYRX_PKT_END_PART1_E = 456,
WIFIMACTX_EXPECT_NDP_RECEPTION_E = 457,
WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 458,
WIFIMACTX_NOTIFICATION_FOR_PHY_E = 459,
WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 460,
WIFIPHYRX_11AZ_INTEGRITY_DATA_E = 461,
WIFIPHYTX_LOCATION_E = 462,
WIFIPHYTX_11AZ_INTEGRITY_DATA_E = 463,
WIFIMACTX_U_SIG_EHT_SU_E = 464,
WIFIPHYRX_U_SIG_EHT_SU_E = 465,
WIFIMACTX_EHT_SIG_USR_SU_E = 466,
WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 467,
WIFIPHYRX_EHT_SIG_USR_SU_E = 468,
WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 469,
WIFIPHYRX_GENERIC_U_SIG_E = 470,
WIFIPHYRX_GENERIC_EHT_SIG_E = 471,
WIFIOVERWRITE_RESP_START_E = 472,
WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 473,
WIFIOVERWRITE_RESP_FRAME_INFO_E = 474,
WIFIOVERWRITE_RESP_END_E = 475,
WIFIRXPCU_EARLY_RX_INDICATION_E = 476,
WIFIMON_DROP_E = 477,
WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 478,
WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 479,
WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 480,
WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 481,
WIFIMACTX_PREFETCH_CV_DMA_E = 482,
WIFIMACTX_PREFETCH_CV_PER_USER_E = 483,
WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 484,
WIFIMACTX_BF_PARAMS_CORR_COMMON_E = 485,
WIFIMACTX_BF_PARAMS_CORR_PER_USER_E = 486,
WIFISPARE_REUSE_TAG_0_E = 487,
WIFISPARE_REUSE_TAG_1_E = 488,
WIFISPARE_REUSE_TAG_2_E = 489,
WIFISPARE_REUSE_TAG_3_E = 490,
WIFISPARE_REUSE_TAG_4_E = 491,
WIFISPARE_REUSE_TAG_5_E = 492,
WIFISPARE_REUSE_TAG_6_E = 493,
WIFISPARE_REUSE_TAG_7_E = 494,
WIFISPARE_REUSE_TAG_8_E = 495,
WIFISPARE_REUSE_TAG_9_E = 496,
WIFISPARE_REUSE_TAG_10_E = 497,
WIFISPARE_REUSE_TAG_11_E = 498,
WIFISPARE_REUSE_TAG_12_E = 499,
WIFISPARE_REUSE_TAG_13_E = 500,
WIFISPARE_REUSE_TAG_14_E = 501,
WIFISPARE_REUSE_TAG_15_E = 502,
WIFISPARE_REUSE_TAG_16_E = 503,
WIFISPARE_REUSE_TAG_17_E = 504,
WIFISPARE_REUSE_TAG_18_E = 505,
WIFISPARE_REUSE_TAG_19_E = 506,
WIFISPARE_REUSE_TAG_20_E = 507,
WIFISPARE_REUSE_TAG_21_E = 508,
WIFISPARE_REUSE_TAG_22_E = 509
} tlv_tag_def__e;
#endif

475
drivers/staging/fw-api/hw/kiwi/v1/tx_msdu_extension.h Normal file
View file

@ -0,0 +1,475 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TX_MSDU_EXTENSION_H_
#define _TX_MSDU_EXTENSION_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
struct tx_msdu_extension {
uint32_t tso_enable : 1,
reserved_0a : 6,
tcp_flag : 9,
tcp_flag_mask : 9,
reserved_0b : 7;
uint32_t l2_length : 16,
ip_length : 16;
uint32_t tcp_seq_number : 32;
uint32_t ip_identification : 16,
udp_length : 16;
uint32_t checksum_offset : 14,
partial_checksum_en : 1,
reserved_4a : 1,
payload_start_offset : 14,
reserved_4b : 2;
uint32_t payload_end_offset : 14,
reserved_5a : 2,
wds : 1,
reserved_5b : 15;
uint32_t buf0_ptr_31_0 : 32;
uint32_t buf0_ptr_39_32 : 8,
extn_override : 1,
encap_type : 2,
encrypt_type : 4,
tqm_no_drop : 1,
buf0_len : 16;
uint32_t buf1_ptr_31_0 : 32;
uint32_t buf1_ptr_39_32 : 8,
epd : 1,
mesh_enable : 2,
reserved_9a : 5,
buf1_len : 16;
uint32_t buf2_ptr_31_0 : 32;
uint32_t buf2_ptr_39_32 : 8,
reserved_11a : 8,
buf2_len : 16;
uint32_t buf3_ptr_31_0 : 32;
uint32_t buf3_ptr_39_32 : 8,
reserved_13a : 8,
buf3_len : 16;
uint32_t buf4_ptr_31_0 : 32;
uint32_t buf4_ptr_39_32 : 8,
reserved_15a : 8,
buf4_len : 16;
uint32_t buf5_ptr_31_0 : 32;
uint32_t buf5_ptr_39_32 : 8,
reserved_17a : 8,
buf5_len : 16;
};
#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0
#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0
#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001
#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1
#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6
#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e
#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7
#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15
#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80
#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16
#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24
#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000
#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25
#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31
#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000
#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004
#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0
#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15
#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff
#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004
#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16
#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31
#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000
#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008
#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0
#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31
#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff
#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c
#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0
#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15
#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff
#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c
#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16
#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31
#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000
#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0
#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13
#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff
#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14
#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14
#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000
#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15
#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15
#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000
#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16
#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29
#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000
#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30
#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31
#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000
#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0
#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13
#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff
#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14
#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15
#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000
#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_WDS_LSB 16
#define TX_MSDU_EXTENSION_WDS_MSB 16
#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000
#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17
#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31
#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000
#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018
#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31
#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff
#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7
#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff
#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB 8
#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB 8
#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK 0x00000100
#define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB 9
#define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB 10
#define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK 0x00000600
#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB 11
#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB 14
#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK 0x00007800
#define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB 15
#define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB 15
#define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK 0x00008000
#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16
#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31
#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000
#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020
#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31
#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff
#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024
#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7
#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff
#define TX_MSDU_EXTENSION_EPD_OFFSET 0x00000024
#define TX_MSDU_EXTENSION_EPD_LSB 8
#define TX_MSDU_EXTENSION_EPD_MSB 8
#define TX_MSDU_EXTENSION_EPD_MASK 0x00000100
#define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET 0x00000024
#define TX_MSDU_EXTENSION_MESH_ENABLE_LSB 9
#define TX_MSDU_EXTENSION_MESH_ENABLE_MSB 10
#define TX_MSDU_EXTENSION_MESH_ENABLE_MASK 0x00000600
#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024
#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 11
#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15
#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000f800
#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024
#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16
#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31
#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000
#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028
#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31
#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff
#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c
#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7
#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff
#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c
#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 8
#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15
#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000ff00
#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c
#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16
#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31
#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000
#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030
#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31
#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff
#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034
#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7
#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff
#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034
#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8
#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15
#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00
#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034
#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16
#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31
#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000
#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038
#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31
#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff
#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c
#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7
#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff
#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c
#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8
#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15
#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00
#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c
#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16
#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31
#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000
#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040
#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31
#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff
#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044
#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7
#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff
#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044
#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8
#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15
#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00
#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044
#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16
#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31
#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000
#endif

142
drivers/staging/fw-api/hw/kiwi/v1/tx_rate_stats_info.h Normal file
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@ -0,0 +1,142 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TX_RATE_STATS_INFO_H_
#define _TX_RATE_STATS_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
struct tx_rate_stats_info {
uint32_t tx_rate_stats_info_valid : 1,
transmit_bw : 3,
transmit_pkt_type : 4,
transmit_stbc : 1,
transmit_ldpc : 1,
transmit_sgi : 2,
transmit_mcs : 4,
ofdma_transmission : 1,
tones_in_ru : 12,
reserved_0a : 3;
uint32_t ppdu_transmission_tsf : 32;
};
#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0
#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0
#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1
#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3
#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e
#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4
#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7
#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0
#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8
#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8
#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100
#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9
#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9
#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200
#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10
#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11
#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00
#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12
#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 15
#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0000f000
#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 16
#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 16
#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00010000
#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 17
#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28
#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1ffe0000
#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_RESERVED_0A_LSB 29
#define TX_RATE_STATS_INFO_RESERVED_0A_MSB 31
#define TX_RATE_STATS_INFO_RESERVED_0A_MASK 0xe0000000
#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004
#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0
#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31
#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff
#endif

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