mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 03:27:44 -04:00
The clock framework changes for 3.20 contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices. Additionaly the framework core underwent a bit of surgery with
two major changes. The boundary between the clock core and clock
providers (e.g clock drivers) is now more well defined with dedicated
provider helper functions. struct clk no longer maps 1:1 with the
hardware clock but is a true per-user cookie which helps us tracker
users of hardware clocks and debug bad behavior. The second major change
is the addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the regulator
framework. Unfortunately these changes to the core created some
breakeage. We think we fixed it all up but for this reason there are
lots of last minute commits trying to undo the damage.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJU54D5AAoJEDqPOy9afJhJs6AQAK5YuUwjDchdpNZx9p7OnT1q
+poehuUwE/gYjmdACqYFyaPrI/9f43iNCfFAgKGLQqmB5ZK4sm4ktzfBEhjWINR2
iiCx9QYMQVGiKwC8KU0ddeBciglE2b/DwxB45m9TsJEjowucUeBzwLEIj5DsGxf7
teXRoOWgXdz1MkQJ4pnA09Q3qEPQgmu8prhMfka/v75/yn7nb9VWiJ6seR2GqTKY
sIKL9WbKjN4AzctggdqHnMSIqZoq6vew850bv2C1fPn7GiYFQfWW+jvMlVY40dp8
nNa2ixSQSIXVw4fCtZhTIZcIvZ8puc7WVLcl8fz3mUe3VJn1VaGs0E+Yd3GexpIV
7bwkTOIdS8gSRlsUaIPiMnUob5TUMmMqjF4KIh/AhP4dYrmVbU7Ie8ccvSxe31Ku
lK7ww6BFv3KweTnW/58856ZXDlXLC6x3KT+Fw58L23VhPToFgYOdTxn8AVtE/LKP
YR3UnY9BqFx6WHXVoNvg3Piyej7RH8fYmE9om8tyWc/Ab8Eo501SHs9l3b2J8snf
w/5STd2CYxyKf1/9JLGnBvGo754O9NvdzBttRlygB14gCCtS/SDk/ELG2Ae+/a9P
YgRk2+257h8PMD3qlp94dLidEZN4kYxP/J6oj0t1/TIkERWfZjzkg5tKn3/hEcU9
qM97ZBTplTm6FM+Dt/Vk
=zCVK
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette:
"The clock framework changes contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices.
Additionally the framework core underwent a bit of surgery with two
major changes:
- The boundary between the clock core and clock providers (e.g clock
drivers) is now more well defined with dedicated provider helper
functions. struct clk no longer maps 1:1 with the hardware clock
but is a true per-user cookie which helps us tracker users of
hardware clocks and debug bad behavior.
- The addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the
regulator framework.
Unfortunately these changes to the core created some breakeage. We
think we fixed it all up but for this reason there are lots of last
minute commits trying to undo the damage"
* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
clk: Only recalculate the rate if needed
Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
clk: qoriq: Add support for the platform PLL
powerpc/corenet: Enable CLK_QORIQ
clk: Replace explicit clk assignment with __clk_hw_set_clk
clk: Add __clk_hw_set_clk helper function
clk: Don't dereference parent clock if is NULL
MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
clk: shmobile: div6: Avoid division by zero in .round_rate()
clk: mxs: Fix invalid 32-bit access to frac registers
clk: omap: compile legacy omap3 clocks conditionally
clkdev: Export clk_register_clkdev
clk: Add rate constraints to clocks
clk: remove clk-private.h
pci: xgene: do not use clk-private.h
arm: omap2+ remove dead clock code
clk: Make clk API return per-user struct clk instances
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
clk: tegra: Add support for the Tegra132 CAR IP block
...
This commit is contained in:
Linus Torvalds
commit
18a8d49973
132 changed files with 13039 additions and 5696 deletions
|
|
@ -21,8 +21,6 @@
|
|||
#include <linux/err.h>
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk/sunxi.h>
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
|
@ -229,6 +227,8 @@ struct sunxi_mmc_host {
|
|||
/* clock management */
|
||||
struct clk *clk_ahb;
|
||||
struct clk *clk_mmc;
|
||||
struct clk *clk_sample;
|
||||
struct clk *clk_output;
|
||||
|
||||
/* irq */
|
||||
spinlock_t lock;
|
||||
|
|
@ -653,26 +653,31 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
|
|||
|
||||
/* determine delays */
|
||||
if (rate <= 400000) {
|
||||
oclk_dly = 0;
|
||||
sclk_dly = 7;
|
||||
oclk_dly = 180;
|
||||
sclk_dly = 42;
|
||||
} else if (rate <= 25000000) {
|
||||
oclk_dly = 0;
|
||||
sclk_dly = 5;
|
||||
oclk_dly = 180;
|
||||
sclk_dly = 75;
|
||||
} else if (rate <= 50000000) {
|
||||
if (ios->timing == MMC_TIMING_UHS_DDR50) {
|
||||
oclk_dly = 2;
|
||||
sclk_dly = 4;
|
||||
oclk_dly = 60;
|
||||
sclk_dly = 120;
|
||||
} else {
|
||||
oclk_dly = 3;
|
||||
sclk_dly = 5;
|
||||
oclk_dly = 90;
|
||||
sclk_dly = 150;
|
||||
}
|
||||
} else if (rate <= 100000000) {
|
||||
oclk_dly = 6;
|
||||
sclk_dly = 24;
|
||||
} else if (rate <= 200000000) {
|
||||
oclk_dly = 3;
|
||||
sclk_dly = 12;
|
||||
} else {
|
||||
/* rate > 50000000 */
|
||||
oclk_dly = 2;
|
||||
sclk_dly = 4;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
clk_sunxi_mmc_phase_control(host->clk_mmc, sclk_dly, oclk_dly);
|
||||
clk_set_phase(host->clk_sample, sclk_dly);
|
||||
clk_set_phase(host->clk_output, oclk_dly);
|
||||
|
||||
return sunxi_mmc_oclk_onoff(host, 1);
|
||||
}
|
||||
|
|
@ -913,6 +918,18 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
|
|||
return PTR_ERR(host->clk_mmc);
|
||||
}
|
||||
|
||||
host->clk_output = devm_clk_get(&pdev->dev, "output");
|
||||
if (IS_ERR(host->clk_output)) {
|
||||
dev_err(&pdev->dev, "Could not get output clock\n");
|
||||
return PTR_ERR(host->clk_output);
|
||||
}
|
||||
|
||||
host->clk_sample = devm_clk_get(&pdev->dev, "sample");
|
||||
if (IS_ERR(host->clk_sample)) {
|
||||
dev_err(&pdev->dev, "Could not get sample clock\n");
|
||||
return PTR_ERR(host->clk_sample);
|
||||
}
|
||||
|
||||
host->reset = devm_reset_control_get(&pdev->dev, "ahb");
|
||||
|
||||
ret = clk_prepare_enable(host->clk_ahb);
|
||||
|
|
@ -927,11 +944,23 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
|
|||
goto error_disable_clk_ahb;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(host->clk_output);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
|
||||
goto error_disable_clk_mmc;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(host->clk_sample);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
|
||||
goto error_disable_clk_output;
|
||||
}
|
||||
|
||||
if (!IS_ERR(host->reset)) {
|
||||
ret = reset_control_deassert(host->reset);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "reset err %d\n", ret);
|
||||
goto error_disable_clk_mmc;
|
||||
goto error_disable_clk_sample;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -950,6 +979,10 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
|
|||
error_assert_reset:
|
||||
if (!IS_ERR(host->reset))
|
||||
reset_control_assert(host->reset);
|
||||
error_disable_clk_sample:
|
||||
clk_disable_unprepare(host->clk_sample);
|
||||
error_disable_clk_output:
|
||||
clk_disable_unprepare(host->clk_output);
|
||||
error_disable_clk_mmc:
|
||||
clk_disable_unprepare(host->clk_mmc);
|
||||
error_disable_clk_ahb:
|
||||
|
|
|
|||
Loading…
Reference in a new issue