From 4d2ead1122ec73304dca3734a67d0af7a901cc15 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 18 Nov 2019 11:50:17 -0800 Subject: [PATCH] dt-bindings: clock: add MDSS clock names for Lahaina This change adds names for the clocks and dividers used by DP and DSI PLL on 5nm architecture. Change-Id: Ia6a49b765cbfbc517e4f2bc06c357c5f3109f912 Signed-off-by: Satya Rama Aditya Pinapala Signed-off-by: Shashank Babu Chinta Venkata --- include/dt-bindings/clock/mdss-5nm-pll-clk.h | 54 ++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 include/dt-bindings/clock/mdss-5nm-pll-clk.h diff --git a/include/dt-bindings/clock/mdss-5nm-pll-clk.h b/include/dt-bindings/clock/mdss-5nm-pll-clk.h new file mode 100644 index 000000000000..4a83638afbbe --- /dev/null +++ b/include/dt-bindings/clock/mdss-5nm-pll-clk.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __MDSS_5NM_PLL_CLK_H +#define __MDSS_5NM_PLL_CLK_H + +/* DSI PLL clocks */ +#define VCO_CLK_0 0 +#define PLL_OUT_DIV_0_CLK 1 +#define BITCLK_SRC_0_CLK 2 +#define BYTECLK_SRC_0_CLK 3 +#define POST_BIT_DIV_0_CLK 4 +#define POST_VCO_DIV_0_CLK 5 +#define BYTECLK_MUX_0_CLK 6 +#define PCLK_SRC_MUX_0_CLK 7 +#define PCLK_SRC_0_CLK 8 +#define PCLK_MUX_0_CLK 9 +#define SHADOW_VCO_CLK_0 10 +#define SHADOW_PLL_OUT_DIV_0_CLK 11 +#define SHADOW_BITCLK_SRC_0_CLK 12 +#define SHADOW_BYTECLK_SRC_0_CLK 13 +#define SHADOW_POST_BIT_DIV_0_CLK 14 +#define SHADOW_POST_VCO_DIV_0_CLK 15 +#define SHADOW_PCLK_SRC_MUX_0_CLK 16 +#define SHADOW_PCLK_SRC_0_CLK 17 +#define VCO_CLK_1 18 +#define PLL_OUT_DIV_1_CLK 19 +#define BITCLK_SRC_1_CLK 20 +#define BYTECLK_SRC_1_CLK 21 +#define POST_BIT_DIV_1_CLK 22 +#define POST_VCO_DIV_1_CLK 23 +#define BYTECLK_MUX_1_CLK 24 +#define PCLK_SRC_MUX_1_CLK 25 +#define PCLK_SRC_1_CLK 26 +#define PCLK_MUX_1_CLK 27 +#define SHADOW_VCO_CLK_1 28 +#define SHADOW_PLL_OUT_DIV_1_CLK 29 +#define SHADOW_BITCLK_SRC_1_CLK 30 +#define SHADOW_BYTECLK_SRC_1_CLK 31 +#define SHADOW_POST_BIT_DIV_1_CLK 32 +#define SHADOW_POST_VCO_DIV_1_CLK 33 +#define SHADOW_PCLK_SRC_MUX_1_CLK 34 +#define SHADOW_PCLK_SRC_1_CLK 35 + +/* DP PLL clocks */ +#define DP_VCO_CLK 0 +#define DP_LINK_CLK_DIVSEL_TEN 1 +#define DP_VCO_DIVIDED_TWO_CLK_SRC 2 +#define DP_VCO_DIVIDED_FOUR_CLK_SRC 3 +#define DP_VCO_DIVIDED_SIX_CLK_SRC 4 +#define DP_VCO_DIVIDED_CLK_SRC_MUX 5 +#endif