From 3566a6afd5a2f4b8060ff8c8a9c3ea3471581dd6 Mon Sep 17 00:00:00 2001 From: Naman Padhiar Date: Tue, 4 Aug 2020 19:53:48 +0530 Subject: [PATCH] ICNSS2: Send MSA address range to firmware Send MSA segment of DDR to FW with IOVA range as part of Host Capability. So that FW detect invalid host DDR access before SMMU fault happens. Change-Id: I21c011b50c54f37dd7b5a942e1914c1afdf6d766 Signed-off-by: Naman Padhiar --- drivers/soc/qcom/icnss2/qmi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/qcom/icnss2/qmi.c b/drivers/soc/qcom/icnss2/qmi.c index 38d934fe57e2..74fdde017893 100644 --- a/drivers/soc/qcom/icnss2/qmi.c +++ b/drivers/soc/qcom/icnss2/qmi.c @@ -2321,8 +2321,12 @@ int wlfw_host_cap_send_sync(struct icnss_priv *priv) req->ddr_range_valid = 1; req->ddr_range[0].start = iova_start; req->ddr_range[0].size = iova_size + iova_ipa_size; + req->ddr_range[1].start = priv->msa_pa; + req->ddr_range[1].size = priv->msa_mem_size; icnss_pr_dbg("Sending iova starting 0x%llx with size 0x%llx\n", req->ddr_range[0].start, req->ddr_range[0].size); + icnss_pr_dbg("Sending msa starting 0x%llx with size 0x%llx\n", + req->ddr_range[1].start, req->ddr_range[1].size); } req->host_build_type_valid = 1;