mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 13:49:24 -04:00
fw-api: CL 30519258 - update fw common interface files
Change-Id: I5d30393252c3d2ff2dc1883c30f4679aff27779e CRs-Fixed: 3830439
This commit is contained in:
spuligil
cnssbldsw
parent
4649af0f53
commit
19d0fdfc78
3 changed files with 387 additions and 2 deletions
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@ -1512,6 +1512,7 @@ typedef enum {
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WMITLV_TAG_STRUC_wmi_pdev_coex_stats,
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WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param,
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WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param,
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WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2,
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} WMITLV_TAG_ID;
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/*
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* IMPORTANT: Please add _ALL_ WMI Commands Here.
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@ -5990,7 +5991,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
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WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_POWER_BOOST_CAPABILITIES, power_boost_capabilities, WMITLV_SIZE_VAR) \
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WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES, rssi_accuracy_improvement_capabilities, WMITLV_SIZE_VAR) \
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WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_ltf_length_capabilities, wr_ltf_caps, WMITLV_SIZE_VAR) \
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WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR)
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WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR) \
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WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES_EXT2, mac_phy_caps2, WMITLV_SIZE_VAR)
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WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
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#define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \
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383
fw/wmi_unified.h
383
fw/wmi_unified.h
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@ -3055,6 +3055,9 @@ typedef struct _wmi_ppe_threshold {
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#define WMI_MAX_EHTCAP_MAC_SIZE 2
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#define WMI_MAX_EHTCAP_PHY_SIZE 3
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#define WMI_MAX_UHRCAP_MAC_SIZE 4
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#define WMI_MAX_UHRCAP_PHY_SIZE 3
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/*
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* 0 – index indicated EHT-MCS map for 20Mhz only sta (4 bytes valid)
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* 1 – index for <= 80MHz bw (only 3 bytes are valid and other is reserved)
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@ -38294,6 +38297,386 @@ typedef struct {
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};
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} WMI_MAC_PHY_CAPABILITIES_EXT;
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typedef struct {
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A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2 */
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/* hw_mode_id:
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* Identify a particular set of HW characteristics, as specified by
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* the subsequent fields.
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* WMI_MAC_PHY_CAPABILITIES element must be mapped to its parent
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* WMI_HW_MODE_CAPABILITIES element using hw_mode_id.
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* No particular ordering of WMI_MAC_PHY_CAPABILITIES elements
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* should be assumed, though in practice the elements will likely
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* be ordered by hw_mode_id.
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*/
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A_UINT32 hw_mode_id;
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/*
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* pdev_id starts with 1. pdev_id 1 => phy_id 0, pdev_id 2 => phy_id 1
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* hw_link_id: Unique link id across SOCs, got as part of QMI handshake.
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* For legacy chips which do not support MLO, these top bits will always
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* be set to 0, so it won't impact the legacy chips which treat pdev_id
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* as 32 bits.
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*/
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union {
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struct {
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A_UINT32 pdev_id:16,
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hw_link_id:16;
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} pdev_to_link_map;
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A_UINT32 pdev_to_link_map_word32;
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};
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/* phy id. Starts with 0 */
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A_UINT32 phy_id;
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A_UINT32 wireless_modes_ext; /* REGDMN MODE EXT, see REGDMN_MODE_ enum */
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/**************************************************************************
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* following new params are for 802.11bn, but under development
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**************************************************************************/
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/* UHR capability mac info field of 802.11bn */
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A_UINT32 uhr_cap_mac_info_2G[WMI_MAX_UHRCAP_MAC_SIZE];
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A_UINT32 uhr_cap_mac_info_5G[WMI_MAX_UHRCAP_MAC_SIZE];
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/* UHR capability phy field of 802.11bn, WMI_UHR_CAP defines */
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A_UINT32 uhr_cap_phy_info_2G[WMI_MAX_UHRCAP_PHY_SIZE];
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A_UINT32 uhr_cap_phy_info_5G[WMI_MAX_UHRCAP_PHY_SIZE];
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union {
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struct {
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A_UINT32 npca_enabled:1, /* bit 0 */
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npca_min_dur_threshold:4, /* bits 4:1 */
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npca_switch_delay:6, /* bits 10:5 */
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npca_switch_back_delay:6, /* bits 16:11 */
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npca_qsrc:2, /* bits 18:17 */
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npca_moplen:1, /* bit 19 */
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reserved: 12;
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};
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A_UINT32 npca_capability;
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};
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} WMI_MAC_PHY_CAPABILITIES_EXT2;
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#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_PDEV_ID_GET(pdev_to_link_map_word32) \
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WMI_GET_BITS(pdev_to_link_map_word32, 0, 16)
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#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_PDEV_ID_SET(pdev_to_link_map_word32, val) \
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WMI_SET_BITS(pdev_to_link_map_word32, 0, 16, val)
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#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_HW_LINK_ID_GET(pdev_to_link_map_word32) \
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WMI_GET_BITS(pdev_to_link_map_word32, 16, 16)
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#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_HW_LINK_ID_SET(pdev_to_link_map_word32, val) \
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WMI_SET_BITS(pdev_to_link_map_word32, 16, 16, val)
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/****** 11BN UHR PHY Capabilities Information field ******/ /* { */
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/* Bit 0: Max Nss Rx for sounding NDP (≤ 80 MHz) */
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#define WMI_UHRCAP_PHY_MAX_NSS_RX_80_GET(uhr_cap_phy) \
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WMI_GET_BITS(uhr_cap_phy[0], 0, 1)
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#define WMI_UHRCAP_PHY_MAX_NSS_RX_80_SET(uhr_cap_phy, value) \
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WMI_SET_BITS(uhr_cap_phy[0], 0, 1, value)
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/* Bit 1: Max Nss,total Rx for DL MU-MIMO (≤ 80 MHz) */
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#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_80_GET(uhr_cap_phy) \
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WMI_GET_BITS(uhr_cap_phy[0], 1, 1)
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#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_80_SET(uhr_cap_phy, value) \
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WMI_SET_BITS(uhr_cap_phy[0], 1, 1, value)
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/* Bit 2: Max Nss Rx for sounding NDP (≤ 160 MHz) */
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#define WMI_UHRCAP_PHY_MAX_NSS_RX_160_GET(uhr_cap_phy) \
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WMI_GET_BITS(uhr_cap_phy[0], 2, 1)
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#define WMI_UHRCAP_PHY_MAX_NSS_RX_160_SET(uhr_cap_phy, value) \
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WMI_SET_BITS(uhr_cap_phy[0], 2, 1, value)
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/* Bit 3: Max Nss,total Rx for DL MU-MIMO (≤ 160 MHz) */
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#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_160_GET(uhr_cap_phy) \
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WMI_GET_BITS(uhr_cap_phy[0], 3, 1)
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#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_160_SET(uhr_cap_phy, value) \
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WMI_SET_BITS(uhr_cap_phy[0], 3, 1, value)
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/* Bit 4: Max Nss Rx for sounding NDP (≤ 320 MHz) */
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#define WMI_UHRCAP_PHY_MAX_NSS_RX_320_GET(uhr_cap_phy) \
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WMI_GET_BITS(uhr_cap_phy[0], 4, 1)
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#define WMI_UHRCAP_PHY_MAX_NSS_RX_320_SET(uhr_cap_phy, value) \
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WMI_SET_BITS(uhr_cap_phy[0], 4, 1, value)
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/* Bit 5: Max Nss,total Rx for DL MU-MIMO (≤ 320 MHz) */
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#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_320_GET(uhr_cap_phy) \
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WMI_GET_BITS(uhr_cap_phy[0], 5, 1)
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#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_320_SET(uhr_cap_phy, value) \
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WMI_SET_BITS(uhr_cap_phy[0], 5, 1, value)
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/* Bit 6: ELR Rx Support */
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#define WMI_UHRCAP_PHY_ELR_RX_GET(uhr_cap_phy) \
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WMI_GET_BITS(uhr_cap_phy[0], 6, 1)
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#define WMI_UHRCAP_PHY_ELR_RX_SET(uhr_cap_phy, value) \
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WMI_SET_BITS(uhr_cap_phy[0], 6, 1, value)
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/* Bit 7: ELR Tx Support */
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#define WMI_UHRCAP_PHY_ELR_TX_GET(uhr_cap_phy) \
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WMI_GET_BITS(uhr_cap_phy[0], 7, 1)
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#define WMI_UHRCAP_PHY_ELR_TX_SET(uhr_cap_phy, value) \
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WMI_SET_BITS(uhr_cap_phy[0], 7, 1, value)
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/****** End of 11BN UHR PHY Capabilities Information field ******/ /* } */
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/****** 11BN UHR MAC Capabilities Information field ******/ /* { */
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/* Bit 0: DPS Support */
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#define WMI_UHRCAP_MAC_DPS_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 0, 1)
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#define WMI_UHRCAP_MAC_DPS_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 0, 1, value)
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/* Bit 1: DPS Assisting support */
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#define WMI_UHRCAP_MAC_DPS_ASSIS_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 1, 1)
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#define WMI_UHRCAP_MAC_DPS_ASSIS_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 1, 1, value)
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/* Bit 2: DPS AP Static HCM Support */
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#define WMI_UHRCAP_MAC_DPS_AP_HCM_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 2, 1)
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#define WMI_UHRCAP_MAC_DPS_AP_HCM_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 2, 1, value)
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/* Bit 3: Multi Link Power Management support */
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#define WMI_UHRCAP_MAC_MULTI_LINK_PM_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 3, 1)
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#define WMI_UHRCAP_MAC_MULTI_LINK_PM_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 3, 1, value)
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/* Bit 4: NPCA support */
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#define WMI_UHRCAP_MAC_NPCA_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 4, 1)
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#define WMI_UHRCAP_MAC_NPCA_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 4, 1, value)
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/* Bit 5: Enhanced BSR support */
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#define WMI_UHRCAP_MAC_BSR_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 5, 1)
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#define WMI_UHRCAP_MAC_BSR_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 5, 1, value)
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/* Bit 6: Additional Mapped TID Support */
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#define WMI_UHRCAP_MAC_ADDITIONAL_TID_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 6, 1)
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#define WMI_UHRCAP_MAC_ADDITIONAL_TID_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 6, 1, value)
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/* Bit 7: EOTSP Support */
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#define WMI_UHRCAP_MAC_EOTSP_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 7, 1)
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#define WMI_UHRCAP_MAC_EOTSP_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 7, 1, value)
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/* Bit 8: DSO Support */
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#define WMI_UHRCAP_MAC_DSO_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 8, 1)
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#define WMI_UHRCAP_MAC_DSO_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 8, 1, value)
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/* Bit 9: P-EDCA Support */
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#define WMI_UHRCAP_MAC_P_EDCA_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 9, 1)
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#define WMI_UHRCAP_MAC_P_EDCA_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 9, 1, value)
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/* Bit 10: DBE Support */
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#define WMI_UHRCAP_MAC_DBE_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 10, 1)
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#define WMI_UHRCAP_MAC_DBE_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 10, 1, value)
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/* Bit 11: UL LLI Support */
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#define WMI_UHRCAP_MAC_UL_LLI_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 11, 1)
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#define WMI_UHRCAP_MAC_UL_LLI_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 11, 1, value)
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/* Bit 12: Peer-to-Peer LLI Support */
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#define WMI_UHRCAP_MAC_PEER_LLI_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 12, 1)
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#define WMI_UHRCAP_MAC_PEER_LLI_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 12, 1, value)
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/* Bit 13: PUO Support */
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#define WMI_UHRCAP_MAC_PUO_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 13, 1)
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#define WMI_UHRCAP_MAC_PUO_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 13, 1, value)
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/* Bit 14: AP PUO Support */
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#define WMI_UHRCAP_MAC_AP_PUO_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 14, 1)
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#define WMI_UHRCAP_MAC_AP_PUO_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 14, 1, value)
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/* Bit 15: DUO Support */
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#define WMI_UHRCAP_MAC_DUO_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 15, 1)
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#define WMI_UHRCAP_MAC_DUO_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 15, 1, value)
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/* Bit 16: OM Control UL MU Data Disable RX Support */
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#define WMI_UHRCAP_MAC_OM_CTRL_UL_MU_DISABLE_RX_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 16, 1)
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#define WMI_UHRCAP_MAC_OM_CTRL_UL_MU_DISABLE_RX_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 16, 1, value)
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/* Bit 17: AOM Support */
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#define WMI_UHRCAP_MAC_AOM_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 17, 1)
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#define WMI_UHRCAP_MAC_AOM_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 17, 1, value)
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/* Bit 18: IFCS Location Support */
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#define WMI_UHRCAP_MAC_IFCS_LOC_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 18, 1)
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#define WMI_UHRCAP_MAC_IFCS_LOC_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 18, 1, value)
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/* Bit 19: UHR TRS Support */
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#define WMI_UHRCAP_MAC_UHR_TRS_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 19, 1)
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#define WMI_UHRCAP_MAC_UHR_TRS_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 19, 1, value)
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/* Bit 20: TXSPG Support */
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#define WMI_UHRCAP_MAC_TXSPG_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 20, 1)
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#define WMI_UHRCAP_MAC_TXSPG_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 20, 1, value)
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/* Bit 21: TXOP Return Support in TXSPG */
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#define WMI_UHRCAP_MAC_TXOP_RETURN_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 21, 1)
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#define WMI_UHRCAP_MAC_TXOP_RETURN_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 21, 1, value)
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/* Bit 22 - 25: UHR Operating Mode And Parameters Update Timeout
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*
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* UHR Operating Mode And Parameters Update Timeout Lookup Table
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*
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* +------------------+-----------------------------+
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* | Sub-field Value | Timeout Duration |
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* +------------------+-----------------------------+
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* | 0 | 0 TUs |
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* | 1 | 128 µs |
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* | 2 | 256 µs |
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* | 3 | 512 µs |
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* | 4 | 1 TU |
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* | 5 | 2 TUs |
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* | 6 | 4 TUs |
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* | 7 | 8 TUs |
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* | 8 | 16 TUs |
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* | 9 | 32 TUs |
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* | 10 | 64 TUs |
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* | 11 | 128 TUs |
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* | 12 - 15 | Reserved for future use |
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* +------------------+-----------------------------+
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*/
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#define WMI_UHRCAP_MAC_UHR_OPMODE_TIMEOUT_GET(uhr_cap_mac) \
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WMI_GET_BITS(uhr_cap_mac[0], 22, 4)
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#define WMI_UHRCAP_MAC_UHR_OPMODE_TIMEOUT_SET(uhr_cap_mac, value) \
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WMI_SET_BITS(uhr_cap_mac[0], 22, 4, value)
|
||||
|
||||
/* Bit 26 - 28 : Parameter Update Adv Notification Interval */
|
||||
#define WMI_UHRCAP_MAC_PARAM_UPDATE_ADV_GET(uhr_cap_mac) \
|
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WMI_GET_BITS(uhr_cap_mac[0], 26, 3)
|
||||
#define WMI_UHRCAP_MAC_PARAM_UPDATE_ADV_SET(uhr_cap_mac, value) \
|
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WMI_SET_BITS(uhr_cap_mac[0], 26, 3, value)
|
||||
|
||||
/* Bit 29-33: Update Indication In TIM Interval */
|
||||
#define WMI_UHRCAP_MAC_UPDATE_IND_TIM_GET(uhr_cap_mac) \
|
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(WMI_GET_BITS(uhr_cap_mac[0], 29, 3) | \
|
||||
(WMI_GET_BITS(uhr_cap_mac[1], 0, 2) << 3))
|
||||
#define WMI_UHRCAP_MAC_UPDATE_IND_TIM_SET(uhr_cap_mac, value) \
|
||||
do { \
|
||||
WMI_SET_BITS(uhr_cap_mac[0], 29, 3, value & 0x7) \
|
||||
WMI_SET_BITS(uhr_cap_mac[1], 0, 2, ((value & 0x18) >> 3)) \
|
||||
} while (0)
|
||||
|
||||
/* Bit 34: Bounded ESS */
|
||||
#define WMI_UHRCAP_MAC_BOUNDED_ESS_GET(uhr_cap_mac) \
|
||||
WMI_GET_BITS(uhr_cap_mac[1], 3, 1)
|
||||
#define WMI_UHRCAP_MAC_BOUNDED_ESS_SET(uhr_cap_mac, value) \
|
||||
WMI_SET_BITS(uhr_cap_mac[1], 3, 1, value)
|
||||
|
||||
/* Bit 35: BTM Assurance */
|
||||
#define WMI_UHRCAP_MAC_BTM_ASSURANCE_GET(uhr_cap_mac) \
|
||||
WMI_GET_BITS(uhr_cap_mac[1], 4, 1)
|
||||
#define WMI_UHRCAP_MAC_BTM_ASSURANCE_SET(uhr_cap_mac, value) \
|
||||
WMI_SET_BITS(uhr_cap_mac[1], 4, 1, value)
|
||||
|
||||
/* Bits 36-63 --- Reserved */
|
||||
|
||||
/* To be decided spec not provided clear bits */
|
||||
|
||||
|
||||
/* Bit 64-66: DBE Capabilities Params */
|
||||
#define WMI_UHRCAP_MAC_DBE_MAX_SUP_BW_GET(uhr_cap_mac) \
|
||||
WMI_GET_BITS(uhr_cap_mac[2], 0, 3)
|
||||
#define WMI_UHRCAP_MAC_DBE_MAX_SUP_BW_SET(uhr_cap_mac, value) \
|
||||
WMI_SET_BITS(uhr_cap_mac[2], 0, 3, value)
|
||||
|
||||
|
||||
/* Bit 67: EHT-MCS Map (BW=160 MHz) Present */
|
||||
#define WMI_UHRCAP_MAC_EHT_MCS_160_PRESENT_GET(uhr_cap_mac) \
|
||||
WMI_GET_BITS(uhr_cap_mac[2], 3, 1)
|
||||
#define WMI_UHRCAP_MAC_EHT_MCS_160_PRESENT_SET(uhr_cap_mac, value) \
|
||||
WMI_SET_BITS(uhr_cap_mac[2], 3, 1, value)
|
||||
|
||||
/* Bit 68: EHT-MCS Map (BW=320 MHz) Present */
|
||||
#define WMI_UHRCAP_MAC_EHT_MCS_320_PRESENT_GET(uhr_cap_mac) \
|
||||
WMI_GET_BITS(uhr_cap_mac[2], 4, 1)
|
||||
#define WMI_UHRCAP_MAC_EHT_MCS_320_PRESENT_SET(uhr_cap_mac, value) \
|
||||
WMI_SET_BITS(uhr_cap_mac[2], 4, 1, value)
|
||||
|
||||
/* Bit 69-71: Reserved */
|
||||
|
||||
/* Bit 72 to 95: EHT-MCS Map (BW=160 MHz) */
|
||||
#define WMI_UHRCAP_MAC_EHT_MCS_MAP_160_GET(uhr_cap_mac) \
|
||||
WMI_GET_BITS(uhr_cap_mac[2], 8, 24)
|
||||
#define WMI_UHRCAP_MAC_EHT_MCS_MAP_160_SET(uhr_cap_mac, value) \
|
||||
WMI_SET_BITS(uhr_cap_mac[2], 8, 24, value)
|
||||
|
||||
/* Bit 96 to 121: EHT-MCS Map (BW=320 MHz) */
|
||||
#define WMI_UHRCAP_MAC_EHT_MCS_MAP_320_GET(uhr_cap_mac) \
|
||||
WMI_GET_BITS(uhr_cap_mac[3], 0, 24)
|
||||
#define WMI_UHRCAP_MAC_EHT_MCS_MAP_320_SET(uhr_cap_mac, value) \
|
||||
WMI_SET_BITS(uhr_cap_mac[3], 0, 24, value)
|
||||
|
||||
/****** End of 11BN UHR MAC Capabilities Information field ******/ /* } */
|
||||
|
||||
#define WMI_CAP_EXT2_NPCA_ENABLED_GET(npca_capability) \
|
||||
WMI_GET_BITS(npca_capability, 0, 1)
|
||||
#define WMI_CAP_EXT2_NPCA_ENABLED_SET(npca_capability, value) \
|
||||
WMI_sET_BITS(npca_capability, 0, 1, value)
|
||||
|
||||
#define WMI_CAP_EXT2_NPCA_MIN_DUR_THRESHOLD_GET(npca_capability) \
|
||||
WMI_GET_BITS(npca_capability, 1, 4)
|
||||
#define WMI_CAP_EXT2_NPCA_MIN_DUR_THRESHOLD_SET(npca_capability, value) \
|
||||
WMI_sET_BITS(npca_capability, 1, 5, value)
|
||||
|
||||
#define WMI_CAP_EXT2_NPCA_SWITCH_DELAY_GET(npca_capability) \
|
||||
WMI_GET_BITS(npca_capability, 5, 6)
|
||||
#define WMI_CAP_EXT2_NPCA_SWITCH_DELAY_SET(npca_capability, value) \
|
||||
WMI_sET_BITS(npca_capability, 5, 6, value)
|
||||
|
||||
#define WMI_CAP_EXT2_NPCA_SWITCH_BACK_DELAY_GET(npca_capability) \
|
||||
WMI_GET_BITS(npca_capability, 11, 6)
|
||||
#define WMI_CAP_EXT2_NPCA_SWITCH_BACK_DELAY_SET(npca_capability, value) \
|
||||
WMI_sET_BITS(npca_capability, 11, 6, value)
|
||||
|
||||
#define WMI_CAP_EXT2_NPCA_QSRC_GET(npca_capability) \
|
||||
WMI_GET_BITS(npca_capability, 17, 2)
|
||||
#define WMI_CAP_EXT2_NPCA_QSRC_SET(npca_capability, value) \
|
||||
WMI_sET_BITS(npca_capability, 17, 2, value)
|
||||
|
||||
#define WMI_CAP_EXT2_NPCA_MOPLEN_GET(npca_capability) \
|
||||
WMI_GET_BITS(npca_capability, 19, 1)
|
||||
#define WMI_CAP_EXT2_NPCA_MOPLEN_SET(npca_capability, value) \
|
||||
WMI_sET_BITS(npca_capability, 19, 1, value)
|
||||
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_HW_MODE_CAPABILITIES */
|
||||
/* hw_mode_id - identify a particular set of HW characteristics,
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@
|
|||
#define __WMI_VER_MINOR_ 0
|
||||
/** WMI revision number has to be incremented when there is a
|
||||
* change that may or may not break compatibility. */
|
||||
#define __WMI_REVISION_ 1654
|
||||
#define __WMI_REVISION_ 1655
|
||||
|
||||
/** The Version Namespace should not be normally changed. Only
|
||||
* host and firmware of the same WMI namespace will work
|
||||
|
|
|
|||
Loading…
Reference in a new issue