From 19e6ce4fa22ddde7137bf23300e2da69a482f874 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Mon, 17 Aug 2020 18:38:54 +0530 Subject: [PATCH] dt-bindings: interconnect: add CPUCP L3 bindings Add bindings for the new interconnect CPUCP L3 driver. Change-Id: I12ee7e6509fe18aef859ff36d17a8b40941d83dd --- bindings/interconnect/qcom,cpucp-l3.txt | 35 +++++++++++++++++++++++++ bindings/interconnect/qcom,epss-l3.txt | 1 - 2 files changed, 35 insertions(+), 1 deletion(-) create mode 100644 bindings/interconnect/qcom,cpucp-l3.txt diff --git a/bindings/interconnect/qcom,cpucp-l3.txt b/bindings/interconnect/qcom,cpucp-l3.txt new file mode 100644 index 000000000000..9fc668ce80de --- /dev/null +++ b/bindings/interconnect/qcom,cpucp-l3.txt @@ -0,0 +1,35 @@ +Qualcomm Technologies, Inc. CPUCP L3 interconnect driver binding +----------------------------------------------------------- + +The CPUCP L3 Interconnect provider supports the scaling of L3 cache +performance states of the CPU subsystem. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,holi-cpucp-l3-shared", + "qcom,holi-cpucp-l3-cpu"; +- reg : Address and length of the register set for the device +- clock-names: should contain "xo", "alternate" +- clocks: list of phandle and clock specifier pairs corresponding to + entries in the clock-names property. +- #interconnect-cells : should contain 1 + +Examples: + +cpucp_l3_shared: l3_shared@fd90000 { + reg = <0x0fd90000 0x3000>; + compatible = "qcom,holi-cpucp-l3-shared"; + #interconnect-cells = <1>; + clock-names = "xo", "alternate"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPLL0>; +}; + +cpucp_l3_cpu: l3_cpu@fd90000{ + reg = <0x0fd90000 0x3000>; + compatible = "qcom,holi-cpucp-l3-cpu"; + #interconnect-cells = <1>; + clock-names = "xo", "alternate"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPLL0>; +}; diff --git a/bindings/interconnect/qcom,epss-l3.txt b/bindings/interconnect/qcom,epss-l3.txt index 1ce85c18cdea..8bd41c0a753e 100644 --- a/bindings/interconnect/qcom,epss-l3.txt +++ b/bindings/interconnect/qcom,epss-l3.txt @@ -8,7 +8,6 @@ Required properties : - compatible : shall contain only one of the following: "qcom,lahaina-epss-l3-shared", "qcom,lahaina-epss-l3-cpu", - "qcom,holi-epss-l3-cpu", "qcom,shima-epss-l3-cpu", "qcom,shima-epss-l3-shared"; - reg : Address and length of the register set for the device