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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge tag 'LA.UM.9.14.r1-21200-LAHAINA.QSSI13.0' of https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/fw-api into android13-5.4-lahaina
"LA.UM.9.14.r1-21200-LAHAINA.QSSI13.0" * tag 'LA.UM.9.14.r1-21200-LAHAINA.QSSI13.0' of https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/fw-api: fw-api: CL 21148594 - update fw common interface files fw-api: CL 21143159 - update fw common interface files fw-api: CL 21137859 - update fw common interface files fw-api: CL 21136812 - update fw common interface files fw-api: CL 21107002 - update fw common interface files fw-api: CL 21038289 - update fw common interface files fw-api: CL 21013894 - update fw common interface files fw-api: CL 20924965 - update fw common interface files fw-api: CL 20915612 - update fw common interface files fw-api: CL 20914692 - update fw common interface files fw-api: CL 20873434 - update fw common interface files fw-api: CL 20843979 - update fw common interface files fw-api: CL 20835037 - update fw common interface files fw-api: CL 20824419 - update fw common interface files fw-api: CL 20794001 - update fw common interface files fw-api: CL 20790906 - update fw common interface files fw-api: CL 20790715 - update fw common interface files fw-api: CL 20771706 - update fw common interface files fw-api: CL 20755332 - update fw common interface files fw-api: CL 20735560 - update fw common interface files fw-api: CL 20694406 - update fw common interface files fw-api: CL 20689038 - update fw common interface files fw-api: CL 20679902 - update fw common interface files fw-api: CL 20679446 - update fw common interface files fw-api: CL 20665555 - update fw common interface files fw-api: CL 20661618 - update fw common interface files fw-api: CL 20649274 - update fw common interface files fw-api: CL 20640871 - update fw common interface files fw-api: CL 20621183 - update fw common interface files fw-api: CL 20599887 - update fw common interface files fw-api: CL 20595785 - update fw common interface files fw-api: CL 20556455 - update fw common interface files fw-api: CL 20540830 - update fw common interface files fw-api: CL 20522535 - update fw common interface files fw-api: CL 20486184 - update fw common interface files fw-api: CL 20467959 - update fw common interface files fw-api: CL 20458896 - update fw common interface files fw-api: CL 20444597 - update fw common interface files fw-api: CL 20442805 - update fw common interface files fw-api: CL 20427704 - update fw common interface files fw-api: Add fw generated tlv for tx monitor fw-api: CL 20406907 - update fw common interface files fw-api: CL 20391906 - update fw common interface files fw-api: CL 20391903 - update fw common interface files fw-api: CL 20378090 - update fw common interface files fw-api: CL 20374109 - update fw common interface files fw-api: CL 20351206 - update fw common interface files fw-api: CL 20281973 - update fw common interface files fw-api: CL 20281921 - update fw common interface files fw-api: CL 20281905 - update fw common interface files fw-api: CL 20275495 - update fw common interface files fw-api: Add macros for PPE2TCL ring fw-api: CL 20254047 - update fw common interface files fw-api: CL 20254044 - update fw common interface files fw-api: CL 20220934 - update fw common interface files fw-api: CL 20220890 - update fw common interface files fw-api: CL 20197888 - update fw common interface files fw-api: CL 20167573 - update fw common interface files fw-api: CL 20152213 - update fw common interface files Change-Id: I0094ccf82da01d2263e2b9ee700bf5c9fa4c1e10
This commit is contained in:
Michael Bestas
commit
19eb405c43
11 changed files with 2774 additions and 274 deletions
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@ -39,6 +39,7 @@ typedef enum {
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CFG_NV_SERVICE_GROUP = 4,
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WDI_IPA_SERVICE_GROUP = 5,
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PACKET_LOG_SERVICE_GROUP = 6,
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LPASS_SERVICE_GROUP = 7,
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HTC_TEST_GROUP = 254,
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HTC_SERVICE_GROUP_LAST = 255
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@ -98,6 +99,8 @@ typedef enum {
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#define PACKET_LOG_SVC MAKE_SERVICE_ID(PACKET_LOG_SERVICE_GROUP,0)
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#define LPASS_DATA_MSG_SVC MAKE_SERVICE_ID(LPASS_SERVICE_GROUP,0)
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/*
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* Directions for interconnect pipe configuration.
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* These definitions may be used during configuration and are shared
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2011-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
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*
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@ -237,9 +237,13 @@
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* 3.110 Add more word_mask fields in htt_tx_monitor_cfg_t.
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* 3.111 Add RXPCU filter enable flag in RX_RING_SELECTION_CFG msg.
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* 3.112 Add logical_link_id field in rx_peer_metadata_v1.
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* 3.113 Add add rx msdu,mpdu,ppdu fields in rx_ring_selection_cfg_t
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* 3.114 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET def.
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* 3.115 Add HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP and
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* HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE msg defs.
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*/
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#define HTT_CURRENT_VERSION_MAJOR 3
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#define HTT_CURRENT_VERSION_MINOR 112
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#define HTT_CURRENT_VERSION_MINOR 115
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#define HTT_NUM_TX_FRAG_DESC 1024
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@ -761,11 +765,16 @@ typedef enum {
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HTT_DBG_ODD_MANDATORY_MUMIMO_TAG = 166, /* htt_odd_mandatory_mumimo_pdev_stats_tlv */
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HTT_DBG_ODD_MANDATORY_MUOFDMA_TAG = 167, /* htt_odd_mandatory_muofdma_pdev_stats_tlv */
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HTT_STATS_LATENCY_PROF_CAL_STATS_TAG = 168, /* htt_latency_prof_cal_stats_tlv */
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HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG = 169, /* htt_tx_pdev_muedca_params_stats_tlv_v */
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HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG = 169, /* htt_tx_pdev_muedca_params_stats_tlv_v - DEPRECATED */
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HTT_STATS_PDEV_BW_MGR_STATS_TAG = 170, /* htt_pdev_bw_mgr_stats_tlv */
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HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v */
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HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, /* htt_txbf_ofdma_ax_steer_mpdu_stats_tlv */
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HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG = 173, /* htt_txbf_ofdma_be_steer_mpdu_stats_tlv */
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HTT_STATS_PEER_AX_OFDMA_STATS_TAG = 174, /* htt_peer_ax_ofdma_stats_tlv */
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HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG = 175, /* htt_tx_pdev_mu_edca_params_stats_tlv_v */
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HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */
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HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */
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HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */
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HTT_STATS_MAX_TAG,
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@ -835,6 +844,8 @@ enum htt_h2t_msg_type {
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HTT_H2T_MSG_TYPE_MSI_SETUP = 0x1f,
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HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20,
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HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21,
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HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22,
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HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23,
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/* keep this last */
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HTT_H2T_NUM_MSGS
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@ -5813,6 +5824,15 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
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A_UINT32 en_rx_tlv_pkt_offset: 1,
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rx_pkt_tlv_offset: 15,
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rsvd6: 16;
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A_UINT32 rx_mpdu_start_word_mask_v2: 20,
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rx_mpdu_end_word_mask_v2: 8,
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rsvd8: 4;
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A_UINT32 rx_msdu_end_word_mask_v2: 20,
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rsvd9: 12;
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A_UINT32 rx_ppdu_end_usr_stats_word_mask_v2: 20,
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rsvd10: 12;
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A_UINT32 packet_type_enable_fpmo_flags0;
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A_UINT32 packet_type_enable_fpmo_flags1;
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} POSTPACK;
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#define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t))
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@ -5950,14 +5970,14 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
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} while(0)
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#define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M 0x08000000
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#define HTT_RX_RING_SELECTION_CFG_RXPXU_FILTER_S 27
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#define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S 27
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#define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXPXU_FILTER_S)
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HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S)
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#define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXPXU_FILTER_S));\
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S));\
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} while(0)
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M 0xffffffff
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@ -6316,6 +6336,71 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_M 0x000FFFFF
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#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S 0
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#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_M)>> \
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HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S)
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#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2, _val);\
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_M 0x0FF00000
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#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S 20
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#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_M)>> \
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HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S)
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#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2, _val);\
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_M 0x000FFFFF
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#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S 0
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#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_M)>> \
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HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S)
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#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2, _val);\
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_M 0x000FFFFF
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#define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S 0
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#define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_M)>> \
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HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S)
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#define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2, _val);\
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_M 0xFFFFFFFF
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#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S 0
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#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_M)>> \
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HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S)
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#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_M 0xFFFFFFFF
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#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S 0
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#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_M)>> \
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HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S)
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#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S)); \
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} while (0)
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/*
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* Subtype based MGMT frames enable bits.
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@ -6675,6 +6760,87 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_M 0x04000000
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_S 26
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/* FPMO mode flags */
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/* MGMT */
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0000_M 0x00000001
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0000_S 0
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0001_M 0x00000002
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0001_S 1
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0010_M 0x00000004
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0010_S 2
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0011_M 0x00000008
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0011_S 3
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0100_M 0x00000010
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0100_S 4
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0101_M 0x00000020
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0101_S 5
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0110_M 0x00000040
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0110_S 6
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0111_M 0x00000080
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0111_S 7
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1000_M 0x00000100
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1000_S 8
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1001_M 0x00000200
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1001_S 9
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1010_M 0x00000400
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1010_S 10
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1011_M 0x00000800
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1011_S 11
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1100_M 0x00001000
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1100_S 12
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1101_M 0x00002000
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1101_S 13
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1110_M 0x00004000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1110_S 14
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1111_M 0x00008000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1111_S 15
|
||||
|
||||
/* CTRL */
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0000_M 0x00010000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0000_S 16
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0001_M 0x00020000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0001_S 17
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0010_M 0x00040000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0010_S 18
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0011_M 0x00080000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0011_S 19
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0100_M 0x00100000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0100_S 20
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0101_M 0x00200000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0101_S 21
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0110_M 0x00400000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0110_S 22
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0111_M 0x00800000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0111_S 23
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1000_M 0x01000000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1000_S 24
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1001_M 0x02000000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1001_S 25
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1010_M 0x04000000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1010_S 26
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1011_M 0x08000000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1011_S 27
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1100_M 0x10000000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1100_S 28
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1101_M 0x20000000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1101_S 29
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1110_M 0x40000000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1110_S 30
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1111_M 0x80000000
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1111_S 31
|
||||
|
||||
/* DATA */
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_MCAST_M 0x00000001
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_MCAST_S 0
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_UCAST_M 0x00000002
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_UCAST_S 1
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_NULL_M 0x00000004
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_NULL_S 2
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_DATA_M 0x00000008
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_DATA_S 3
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_TB_M 0x00000010
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_TB_S 4
|
||||
|
||||
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET(word, httsym, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(httsym, value); \
|
||||
|
|
@ -9725,6 +9891,9 @@ PREPACK struct htt_h2t_sawf_def_queues_map_report_req {
|
|||
* @details
|
||||
* This is shared memory between Host and Target allocated
|
||||
* and used in chips where UMAC hang recovery feature is supported.
|
||||
* This shared memory is allocated per SOC level by Host since each
|
||||
* SOC's target Q6FW needs to communicate independently to the Host
|
||||
* through its own shared memory.
|
||||
* If target sets a bit in t2h_msg (provided it's valid bit offset)
|
||||
* then host interprets it as a new message from target.
|
||||
* Host clears that particular read bit in t2h_msg after each read
|
||||
|
|
@ -9738,11 +9907,13 @@ PREPACK struct htt_h2t_sawf_def_queues_map_report_req {
|
|||
* dword1 - b'0 - do_pre_reset
|
||||
* b'1 - do_post_reset_start
|
||||
* b'2 - do_post_reset_complete
|
||||
* b'3:31 - rsvd_t2h
|
||||
* b'3 - initiate_umac_recovery
|
||||
* b'4:31 - rsvd_t2h
|
||||
* dword2 - b'0 - pre_reset_done
|
||||
* b'1 - post_reset_start_done
|
||||
* b'2 - post_reset_complete_done
|
||||
* b'3:31 - rsvd_h2t
|
||||
* b'3 - start_pre_reset
|
||||
* b'4:31 - rsvd_h2t
|
||||
*/
|
||||
PREPACK typedef struct {
|
||||
/** Magic number added for debuggability. */
|
||||
|
|
@ -9752,14 +9923,18 @@ PREPACK typedef struct {
|
|||
* BIT [0] :- T2H msg to do pre-reset
|
||||
* BIT [1] :- T2H msg to do post-reset start
|
||||
* BIT [2] :- T2H msg to do post-reset complete
|
||||
* BIT [31 : 3] :- reserved
|
||||
* BIT [3] :- T2H msg to initiate UMAC recovery sequence.
|
||||
* This is needed to synchronize UMAC recovery
|
||||
* across all SOCs.
|
||||
* BIT [31 : 4] :- reserved
|
||||
*/
|
||||
A_UINT32 t2h_msg;
|
||||
struct {
|
||||
A_UINT32 do_pre_reset : 1, /* BIT [0] */
|
||||
do_post_reset_start : 1, /* BIT [1] */
|
||||
do_post_reset_complete : 1, /* BIT [2] */
|
||||
rsvd_t2h : 29; /* BIT [31 : 3] */
|
||||
initiate_umac_recovery : 1, /* BIT [3] */
|
||||
rsvd_t2h : 28; /* BIT [31 : 4] */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -9768,14 +9943,19 @@ PREPACK typedef struct {
|
|||
* BIT [0] :- H2T msg to send pre-reset done
|
||||
* BIT [1] :- H2T msg to send post-reset start done
|
||||
* BIT [2] :- H2T msg to send post-reset complete done
|
||||
* BIT [31 : 3] :- reserved
|
||||
* BIT [3] :- H2T msg to start pre-reset.
|
||||
* This is expected only after T2H
|
||||
* initiate_umac_recovery was received by Host
|
||||
* from one of the SOCs.
|
||||
* BIT [31 : 4] :- reserved
|
||||
*/
|
||||
A_UINT32 h2t_msg;
|
||||
struct {
|
||||
A_UINT32 pre_reset_done : 1, /* BIT [0] */
|
||||
post_reset_start_done : 1, /* BIT [1] */
|
||||
post_reset_complete_done : 1, /* BIT [2] */
|
||||
rsvd_h2t : 29; /* BIT [31 : 3] */
|
||||
start_pre_reset : 1, /* BIT [3] */
|
||||
rsvd_h2t : 28; /* BIT [31 : 4] */
|
||||
};
|
||||
};
|
||||
} POSTPACK htt_umac_hang_recovery_msg_shmem_t;
|
||||
|
|
@ -9821,6 +10001,18 @@ PREPACK typedef struct {
|
|||
((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S));\
|
||||
} while (0)
|
||||
|
||||
/* dword1 - b'3 - initiate_umac_recovery */
|
||||
#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M 0x00000008
|
||||
#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S 3
|
||||
#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_GET(word1) \
|
||||
(((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M) >> \
|
||||
HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S)
|
||||
#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_SET(word1, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY, _val); \
|
||||
((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S));\
|
||||
} while (0)
|
||||
|
||||
/* dword2 - b'0 - pre_reset_done */
|
||||
#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M 0x00000001
|
||||
#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S 0
|
||||
|
|
@ -9857,6 +10049,18 @@ PREPACK typedef struct {
|
|||
((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S));\
|
||||
} while (0)
|
||||
|
||||
/* dword2 - b'3 - start_pre_reset */
|
||||
#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_M 0x00000008
|
||||
#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S 3
|
||||
#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_GET(word2) \
|
||||
(((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_M) >> \
|
||||
HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S)
|
||||
#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_SET(word2, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET, _val); \
|
||||
((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S));\
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @brief HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message
|
||||
*
|
||||
|
|
@ -9885,7 +10089,8 @@ PREPACK typedef struct {
|
|||
* |--------------------------------------------------------------------------|
|
||||
*
|
||||
* The message is interpreted as follows:
|
||||
* dword0 - b'0:7 - msg_type (= HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SETUP)
|
||||
* dword0 - b'0:7 - msg_type
|
||||
* (HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP)
|
||||
* b'8:11 - t2h_msg_method: indicates method to be used for
|
||||
* T2H communication in UMAC hang recovery mode.
|
||||
* Value zero indicates MSI interrupt (default method).
|
||||
|
|
@ -9951,6 +10156,324 @@ PREPACK typedef struct {
|
|||
((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S));\
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @brief HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET message
|
||||
*
|
||||
* @details
|
||||
* The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET is a SOC level
|
||||
* HTT message sent by the host to indicate that the target needs to start the
|
||||
* UMAC hang recovery feature from the point of pre-reset routine.
|
||||
* The purpose of this H2T message is to have host synchronize and trigger
|
||||
* UMAC recovery across all targets.
|
||||
* The info sent in this H2T message is the flag to indicate whether the
|
||||
* target needs to execute UMAC-recovery in context of the Initiator or
|
||||
* Non-Initiator.
|
||||
* This H2T message is expected to be sent as response to the
|
||||
* initiate_umac_recovery indication from the Initiator target attached to
|
||||
* this same host.
|
||||
* This H2T message is expected to be only sent if the WMI service bit
|
||||
* WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target
|
||||
* and HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP was sent
|
||||
* beforehand.
|
||||
*
|
||||
* |31 9|8|7 0|
|
||||
* |-----------------------------------------------------------|
|
||||
* | reserved |I| msg_type |
|
||||
* |-----------------------------------------------------------|
|
||||
* Where:
|
||||
* I = is_initiator
|
||||
*
|
||||
* The message is interpreted as follows:
|
||||
* dword0 - b'0:7 - msg_type
|
||||
* (HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET)
|
||||
* b'8 - is_initiator: indicates whether the target needs to
|
||||
* execute the UMAC-recovery in context of the Initiator or
|
||||
* Non-Initiator.
|
||||
* The value zero indicates this target is Non-Initiator.
|
||||
* b'9:31 - reserved.
|
||||
*/
|
||||
|
||||
PREPACK typedef struct {
|
||||
A_UINT32 msg_type : 8,
|
||||
is_initiator : 1,
|
||||
reserved : 23;
|
||||
} POSTPACK htt_h2t_umac_hang_recovery_start_pre_reset_t;
|
||||
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES \
|
||||
(sizeof(htt_h2t_umac_hang_recovery_start_pre_reset_t))
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_DWORDS \
|
||||
(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES >> 2)
|
||||
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_M 0x00000100
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S 8
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_GET(word0) \
|
||||
(((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_M) >> \
|
||||
HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S)
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_SET(word0, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR, _val); \
|
||||
((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S));\
|
||||
} while (0)
|
||||
|
||||
|
||||
/*
|
||||
* @brief host -> target HTT RX_CCE_SUPER_RULE_SETUP message
|
||||
*
|
||||
* MSG_TYPE => HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP
|
||||
*
|
||||
* @details
|
||||
* Host sends RX_CCE_SUPER_RULE setup message to target, in order to request,
|
||||
* install or uninstall rx cce super rules to match certain kind of packets
|
||||
* with specific parameters. Target sets up HW registers based on setup message
|
||||
* and always confirms back to Host.
|
||||
*
|
||||
* The message would appear as follows:
|
||||
* |31 24|23 16|15 8|7 0|
|
||||
* |-----------------+-----------------+-----------------+-----------------|
|
||||
* | reserved | operation | vdev_id | msg_type |
|
||||
* |-----------------------------------------------------------------------|
|
||||
* | cce_super_rule_param[0] |
|
||||
* |-----------------------------------------------------------------------|
|
||||
* | cce_super_rule_param[1] |
|
||||
* |-----------------------------------------------------------------------|
|
||||
*
|
||||
* The message is interpreted as follows:
|
||||
* dword0 - b'0:7 - msg_type: This will be set to
|
||||
* 0x23 (HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP)
|
||||
* b'8:15 - vdev_id: Identify which vdev RX_CCE_SUPER_RULE is for
|
||||
* b'16:23 - operation: Identify operation to be taken,
|
||||
* 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST
|
||||
* 1: HTT_RX_CCE_SUPER_RULE_INSTALL
|
||||
* 2: HTT_RX_CCE_SUPER_RULE_RELEASE
|
||||
* b'24:31 - reserved
|
||||
* dword1~10 - cce_super_rule_param[0]:
|
||||
* contains parameters used to setup RX_CCE_SUPER_RULE_0
|
||||
* dword11~20 - cce_super_rule_param[1]:
|
||||
* contains parameters used to setup RX_CCE_SUPER_RULE_1
|
||||
*
|
||||
* Each cce_super_rule_param structure would appear as follows:
|
||||
* |31 24|23 16|15 8|7 0|
|
||||
* |-----------------+-----------------+-----------------+-----------------|
|
||||
* |src_ipv6_addr[3] |src_ipv6_addr[2] |src_ipv6_addr[1] |src_ipv6_addr[0] |
|
||||
* |/src_ipv4_addr[3]|/src_ipv4_addr[2]|/src_ipv4_addr[1]|/src_ipv4_addr[0]|
|
||||
* |-----------------------------------------------------------------------|
|
||||
* |src_ipv6_addr[7] |src_ipv6_addr[6] |src_ipv6_addr[5] |src_ipv6_addr[4] |
|
||||
* |-----------------------------------------------------------------------|
|
||||
* |src_ipv6_addr[11]|src_ipv6_addr[10]|src_ipv6_addr[9] |src_ipv6_addr[8] |
|
||||
* |-----------------------------------------------------------------------|
|
||||
* |src_ipv6_addr[15]|src_ipv6_addr[14]|src_ipv6_addr[13]|src_ipv6_addr[12]|
|
||||
* |-----------------------------------------------------------------------|
|
||||
* |dst_ipv6_addr[3] |dst_ipv6_addr[2] |dst_ipv6_addr[1] |dst_ipv6_addr[0] |
|
||||
* |/dst_ipv4_addr[3]|/dst_ipv4_addr[2]|/dst_ipv4_addr[1]|/dst_ipv4_addr[0]|
|
||||
* |-----------------------------------------------------------------------|
|
||||
* |dst_ipv6_addr[7] |dst_ipv6_addr[6] |dst_ipv6_addr[5] |dst_ipv6_addr[4] |
|
||||
* |-----------------------------------------------------------------------|
|
||||
* |dst_ipv6_addr[11]|dst_ipv6_addr[10]|dst_ipv6_addr[9] |dst_ipv6_addr[8] |
|
||||
* |-----------------------------------------------------------------------|
|
||||
* |dst_ipv6_addr[15]|dst_ipv6_addr[14]|dst_ipv6_addr[13]|dst_ipv6_addr[12]|
|
||||
* |-----------------------------------------------------------------------|
|
||||
* | is_valid | l4_type | l3_type |
|
||||
* |-----------------------------------------------------------------------|
|
||||
* | l4_dst_port | l4_src_port |
|
||||
* |-----------------------------------------------------------------------|
|
||||
*
|
||||
* The cce_super_rule_param[0] structure is interpreted as follows:
|
||||
* dword1 - b'0:7 - src_ipv6_addr[0]: b'120:127 of source ipv6 address
|
||||
* (or src_ipv4_addr[0]: b'24:31 of source ipv4 address,
|
||||
* in case of ipv4)
|
||||
* b'8:15 - src_ipv6_addr[1]: b'112:119 of source ipv6 address
|
||||
* (or src_ipv4_addr[1]: b'16:23 of source ipv4 address,
|
||||
* in case of ipv4)
|
||||
* b'16:23 - src_ipv6_addr[2]: b'104:111 of source ipv6 address
|
||||
* (or src_ipv4_addr[2]: b'8:15 of source ipv4 address,
|
||||
* in case of ipv4)
|
||||
* b'24:31 - src_ipv6_addr[3]: b'96:103 of source ipv6 address
|
||||
* (or src_ipv4_addr[3]: b'0:7 of source ipv4 address,
|
||||
* in case of ipv4)
|
||||
* dword2 - b'0:7 - src_ipv6_addr[4]: b'88:95 of source ipv6 address
|
||||
* b'8:15 - src_ipv6_addr[5]: b'80:87 of source ipv6 address
|
||||
* b'16:23 - src_ipv6_addr[6]: b'72:79 of source ipv6 address
|
||||
* b'24:31 - src_ipv6_addr[7]: b'64:71 of source ipv6 address
|
||||
* dword3 - b'0:7 - src_ipv6_addr[8]: b'56:63 of source ipv6 address
|
||||
* b'8:15 - src_ipv6_addr[9]: b'48:55 of source ipv6 address
|
||||
* b'16:23 - src_ipv6_addr[10]: b'40:47 of source ipv6 address
|
||||
* b'24:31 - src_ipv6_addr[11]: b'32:39 of source ipv6 address
|
||||
* dword4 - b'0:7 - src_ipv6_addr[12]: b'24:31 of source ipv6 address
|
||||
* b'8:15 - src_ipv6_addr[13]: b'16:23 of source ipv6 address
|
||||
* b'16:23 - src_ipv6_addr[14]: b'8:15 of source ipv6 address
|
||||
* b'24:31 - src_ipv6_addr[15]: b'0:7 of source ipv6 address
|
||||
* dword5 - b'0:7 - dst_ipv6_addr[0]: b'120:127 of destination ipv6 address
|
||||
* (or dst_ipv4_addr[0]: b'24:31 of destination
|
||||
* ipv4 address, in case of ipv4)
|
||||
* b'8:15 - dst_ipv6_addr[1]: b'112:119 of destination ipv6 address
|
||||
* (or dst_ipv4_addr[1]: b'16:23 of destination
|
||||
* ipv4 address, in case of ipv4)
|
||||
* b'16:23 - dst_ipv6_addr[2]: b'104:111 of destination ipv6 address
|
||||
* (or dst_ipv4_addr[2]: b'8:15 of destination
|
||||
* ipv4 address, in case of ipv4)
|
||||
* b'24:31 - dst_ipv6_addr[3]: b'96:103 of destination ipv6 address
|
||||
* (or dst_ipv4_addr[3]: b'0:7 of destination
|
||||
* ipv4 address, in case of ipv4)
|
||||
* dword6 - b'0:7 - dst_ipv6_addr[4]: b'88:95 of destination ipv6 address
|
||||
* b'8:15 - dst_ipv6_addr[5]: b'80:87 of destination ipv6 address
|
||||
* b'16:23 - dst_ipv6_addr[6]: b'72:79 of destination ipv6 address
|
||||
* b'24:31 - dst_ipv6_addr[7]: b'64:71 of destination ipv6 address
|
||||
* dword7 - b'0:7 - dst_ipv6_addr[8]: b'56:63 of destination ipv6 address
|
||||
* b'8:15 - dst_ipv6_addr[9]: b'48:55 of destination ipv6 address
|
||||
* b'16:23 - dst_ipv6_addr[10]: b'40:47 of destination ipv6 address
|
||||
* b'24:31 - dst_ipv6_addr[11]: b'32:39 of destination ipv6 address
|
||||
* dword8 - b'0:7 - dst_ipv6_addr[12]: b'24:31 of destination ipv6 address
|
||||
* b'8:15 - dst_ipv6_addr[13]: b'16:23 of destination ipv6 address
|
||||
* b'16:23 - dst_ipv6_addr[14]: b'8:15 of destination ipv6 address
|
||||
* b'24:31 - dst_ipv6_addr[15]: b'0:7 of destination ipv6 address
|
||||
* dword9 - b'0:15 - l3_type: type of L3 protocol, indicating L3 protocol used
|
||||
* 0x0008: ipv4
|
||||
* 0xdd86: ipv6
|
||||
* b'16:23 - l4_type: type of L4 protocol, indicating L4 protocol used
|
||||
* 6: TCP
|
||||
* 17: UDP
|
||||
* b'24:31 - is_valid: indicate whether this parameter is valid
|
||||
* 0: invalid
|
||||
* 1: valid
|
||||
* dword10 - b'0:15 - l4_src_port: TCP/UDP source port field
|
||||
* b'16:31 - l4_dst_port: TCP/UDP destination port field
|
||||
*
|
||||
* The cce_super_rule_param[1] structure is similar.
|
||||
*/
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_NUM 2
|
||||
|
||||
enum htt_rx_cce_super_rule_setup_operation {
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST = 0,
|
||||
HTT_RX_CCE_SUPER_RULE_INSTALL,
|
||||
HTT_RX_CCE_SUPER_RULE_RELEASE,
|
||||
|
||||
/* All operation should be before this */
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_OPERATION,
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
union {
|
||||
A_UINT8 src_ipv4_addr[4];
|
||||
A_UINT8 src_ipv6_addr[16];
|
||||
};
|
||||
union {
|
||||
A_UINT8 dst_ipv4_addr[4];
|
||||
A_UINT8 dst_ipv6_addr[16];
|
||||
};
|
||||
A_UINT32 l3_type: 16,
|
||||
l4_type: 8,
|
||||
is_valid: 8;
|
||||
A_UINT32 l4_src_port: 16,
|
||||
l4_dst_port: 16;
|
||||
} htt_rx_cce_super_rule_param_t;
|
||||
|
||||
PREPACK struct htt_rx_cce_super_rule_setup_t {
|
||||
A_UINT32 msg_type: 8,
|
||||
vdev_id: 8,
|
||||
operation: 8,
|
||||
reserved: 8;
|
||||
htt_rx_cce_super_rule_param_t
|
||||
cce_super_rule_param[HTT_RX_CCE_SUPER_RULE_SETUP_NUM];
|
||||
} POSTPACK;
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_SZ \
|
||||
(sizeof(struct htt_rx_cce_super_rule_setup_t))
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_M 0x0000ff00
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S 8
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M 0x00ff0000
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S 16
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M 0x0000ffff
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S 0
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M 0x00ff0000
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S 16
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M 0xff000000
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S 24
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M 0x0000ffff
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S 0
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M 0xffff0000
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S 16
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_GET(_ptr, _array) \
|
||||
do { \
|
||||
A_MEMCPY(_array, _ptr, 4); \
|
||||
} while (0)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_SET(_ptr, _array) \
|
||||
do { \
|
||||
A_MEMCPY(_ptr, _array, 4); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_GET(_ptr, _array) \
|
||||
do { \
|
||||
A_MEMCPY(_array, _ptr, 16); \
|
||||
} while (0)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_SET(_ptr, _array) \
|
||||
do { \
|
||||
A_MEMCPY(_ptr, _array, 16); \
|
||||
} while (0)
|
||||
|
||||
|
||||
/*=== target -> host messages ===============================================*/
|
||||
|
||||
|
|
@ -10014,6 +10537,7 @@ enum htt_t2h_msg_type {
|
|||
HTT_T2H_PPDU_ID_FMT_IND = 0x30,
|
||||
HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN = 0x31,
|
||||
HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32,
|
||||
HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE = 0x33,
|
||||
|
||||
|
||||
HTT_T2H_MSG_TYPE_TEST,
|
||||
|
|
@ -19205,4 +19729,176 @@ typedef struct {
|
|||
} htt_t2h_ppdu_id_fmt_ind_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief target -> host RX_CCE_SUPER_RULE setup done message
|
||||
*
|
||||
* MSG_TYPE => HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE
|
||||
*
|
||||
* @details
|
||||
* HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE message is sent by the target
|
||||
* when RX_CCE_SUPER_RULE setup is done
|
||||
*
|
||||
* This message shows the configuration results after the setup operation.
|
||||
* It will always be sent to host.
|
||||
* The message would appear as follows:
|
||||
*
|
||||
* |31 24|23 16|15 8|7 0|
|
||||
* |-----------------+-----------------+----------------+----------------|
|
||||
* | result | response_type | vdev_id | msg_type |
|
||||
* |---------------------------------------------------------------------|
|
||||
*
|
||||
* The message is interpreted as follows:
|
||||
* dword0 - b'0:7 - msg_type: This will be set to 0x33
|
||||
* (HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE)
|
||||
* b'8:15 - vdev_id: Identify which vdev RX_CCE_SUPER_RULE is setup on
|
||||
* b'16:23 - response_type: Indicate the response type of this setup
|
||||
* done msg
|
||||
* 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE,
|
||||
* response to HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST
|
||||
* 1: HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE,
|
||||
* response to HTT_RX_CCE_SUPER_RULE_INSTALL
|
||||
* 2: HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE,
|
||||
* response to HTT_RX_CCE_SUPER_RULE_RELEASE
|
||||
* b'24:31 - result: Indicate result of setup operation
|
||||
* For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE:
|
||||
* b'24 - is_rule_enough: indicate if there are
|
||||
* enough free cce rule slots
|
||||
* 0: not enough
|
||||
* 1: enough
|
||||
* b'25:31 - avail_rule_num: indicate the number of
|
||||
* remaining free cce rule slots, only makes sense
|
||||
* when is_rule_enough = 0
|
||||
* For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE:
|
||||
* b'24 - cfg_result_0: indicate the config result
|
||||
* of RX_CCE_SUPER_RULE_0
|
||||
* 0: Install/Uninstall fails
|
||||
* 1: Install/Uninstall succeeds
|
||||
* b'25 - cfg_result_1: indicate the config result
|
||||
* of RX_CCE_SUPER_RULE_1
|
||||
* 0: Install/Uninstall fails
|
||||
* 1: Install/Uninstall succeeds
|
||||
* b'26:31 - reserved
|
||||
* For HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE:
|
||||
* b'24 - cfg_result_0: indicate the config result
|
||||
* of RX_CCE_SUPER_RULE_0
|
||||
* 0: Release fails
|
||||
* 1: Release succeeds
|
||||
* b'25 - cfg_result_1: indicate the config result
|
||||
* of RX_CCE_SUPER_RULE_1
|
||||
* 0: Release fails
|
||||
* 1: Release succeeds
|
||||
* b'26:31 - reserved
|
||||
*/
|
||||
|
||||
enum htt_rx_cce_super_rule_setup_done_response_type {
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE = 0,
|
||||
HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE,
|
||||
HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE,
|
||||
|
||||
/*All reply type should be before this*/
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_RESPONSE,
|
||||
};
|
||||
|
||||
PREPACK struct htt_rx_cce_super_rule_setup_done_t {
|
||||
A_UINT8 msg_type;
|
||||
A_UINT8 vdev_id;
|
||||
A_UINT8 response_type;
|
||||
union {
|
||||
struct {
|
||||
/* For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE */
|
||||
A_UINT8 is_rule_enough: 1,
|
||||
avail_rule_num: 7;
|
||||
};
|
||||
struct {
|
||||
/*
|
||||
* For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE and
|
||||
* HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE
|
||||
*/
|
||||
A_UINT8 cfg_result_0: 1,
|
||||
cfg_result_1: 1,
|
||||
rsvd: 6;
|
||||
};
|
||||
} result;
|
||||
} POSTPACK;
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_SZ (sizeof(struct htt_rx_cce_super_rule_setup_done_t))
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_M 0x0000ff00
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S 8
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M 0x00ff0000
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S 16
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M 0xff000000
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S 24
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M 0x01000000
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S 24
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M 0xFE000000
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S 25
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M 0x01000000
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S 24
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M 0x02000000
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S 25
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_GET(_var) \
|
||||
(((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M) >> \
|
||||
HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S)
|
||||
#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S)); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -612,6 +612,58 @@ typedef enum HTT_PPDU_STATS_SPATIAL_REUSE HTT_PPDU_STATS_SPATIAL_REUSE;
|
|||
((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_M 0x00020000
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_S 17
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_GET(_var) \
|
||||
(((_var) & HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_M) >> \
|
||||
HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_S)
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID, _val); \
|
||||
((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_M 0x000c0000
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_S 18
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_GET(_var) \
|
||||
(((_var) & HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_M) >> \
|
||||
HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_S)
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_AC_VALID, _val); \
|
||||
((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_M 0x00100000
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_S 20
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_GET(_var) \
|
||||
(((_var) & HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_M) >> \
|
||||
HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_S)
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID, _val); \
|
||||
((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_M 0x1fe00000
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_S 21
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_GET(_var) \
|
||||
(((_var) & HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_M) >> \
|
||||
HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_S)
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID, _val); \
|
||||
((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_PPDU_STATS_COMMON_TRIG_COOKIE_M 0x0000ffff
|
||||
#define HTT_PPDU_STATS_COMMON_TRIG_COOKIE_S 0
|
||||
|
||||
|
|
@ -760,19 +812,36 @@ typedef struct {
|
|||
* by which SRG/Non-SRG based spatial reuse opportunity
|
||||
* was created.
|
||||
* BIT [16:16] - PPDU transmitted using PSR opportunity
|
||||
* BIT [31:17] - reserved
|
||||
* BIT [17:17] - backoff_ac_valid
|
||||
* BIT [19:18] - backoff_ac: WMM ACI Value of the backoff engine used for
|
||||
* this transmission. Only valid if backoff_ac_valid is set
|
||||
* to 1. Typically this would match the default tid
|
||||
* number -> AC mapping. For frames in the middle of a SIFS
|
||||
* burst, the backoff_ac_valid will be 0.
|
||||
* BIT [20:20] - num_ul_user_responses_valid
|
||||
* BIT [21:28] - num_ul_user_responses: The number of user responses
|
||||
* detected by the MAC layer. This value can be compared with
|
||||
* the "num_ul_expected_users" field to see whether this frame
|
||||
* had a complete or partial response failure. Only valid if
|
||||
* num_ul_user_responses_valid is set to 1.
|
||||
* BIT [31:29] - reserved
|
||||
*/
|
||||
union {
|
||||
A_UINT32 reserved__num_ul_user_responses__num_ul_user_responses_valid__backoff_ac__backoff_ac_valid__psr_tx__aborted_obss_rssi__srg_tx__non_srg_tx__bss_color_id;
|
||||
A_UINT32 reserved__psr_tx__aborted_obss_rssi__srg_tx__non_srg_tx___bss_color_id;
|
||||
A_UINT32 reserved__aborted_obss_rssi__srg_tx__non_srg_tx___bss_color_id;
|
||||
A_UINT32 reserved__bss_color_id;
|
||||
struct {
|
||||
A_UINT32 bss_color_id: 6,
|
||||
non_srg_tx: 1,
|
||||
srg_tx: 1,
|
||||
aborted_obss_rssi: 8,
|
||||
psr_tx: 1,
|
||||
reserved2: 15;
|
||||
A_UINT32 bss_color_id: 6,
|
||||
non_srg_tx: 1,
|
||||
srg_tx: 1,
|
||||
aborted_obss_rssi: 8,
|
||||
psr_tx: 1,
|
||||
backoff_ac_valid: 1,
|
||||
backoff_ac: 2,
|
||||
num_ul_user_responses_valid: 1,
|
||||
num_ul_user_responses: 8,
|
||||
reserved2: 3;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -787,16 +856,18 @@ typedef struct {
|
|||
};
|
||||
|
||||
/*
|
||||
* htt_seq_type field is added for backward compatibility with
|
||||
* pktlog decoder, host driver or any third party tool interpreting
|
||||
* ppdu sequence type. If field 'htt_seq_type'is not present or is
|
||||
* present but set to WAL_PPDU_SEQ_TYPE, decoder should interpret
|
||||
* the seq type as WAL_TXSEND_PPDU_SEQUENCE.
|
||||
* If the new field htt_seq_type is present and is set to
|
||||
* HTT_PPDU_SEQ_TYPE then decoder should interpret the seq type as
|
||||
* HTT_PPDU_STATS_SEQ_TYPE. htt_seq_type field will be set to
|
||||
* HTT_PPDU_SEQ_TYPE in firmware versions where this field is
|
||||
* defined.
|
||||
* BIT [0 : 0] - htt_seq_type field is added for backward compatibility
|
||||
* with pktlog decoder, host driver or any third party tool
|
||||
* interpreting ppdu sequence type. If field 'htt_seq_type'
|
||||
* is not present or is present but set to WAL_PPDU_SEQ_TYPE,
|
||||
* decoder should interpret the seq type as
|
||||
* WAL_TXSEND_PPDU_SEQUENCE.
|
||||
* If the new field htt_seq_type is present and is set to
|
||||
* HTT_PPDU_SEQ_TYPE then decoder should interpret the
|
||||
* seq type as HTT_PPDU_STATS_SEQ_TYPE.
|
||||
* htt_seq_type field will be set to HTT_PPDU_SEQ_TYPE in
|
||||
* firmware versions where this field is defined.
|
||||
* BIT [31: 1] - reserved
|
||||
*/
|
||||
union {
|
||||
A_UINT32 reserved__htt_seq_type;
|
||||
|
|
@ -1169,6 +1240,19 @@ typedef struct {
|
|||
* value is larger than A_INT8.
|
||||
*/
|
||||
A_UINT32 alt_tx_pwr[HTT_STATS_MAX_CHAINS / HTT_PPDU_STATS_USER_COMMON_TLV_TX_PWR_CHAINS_PER_U32];
|
||||
|
||||
/*
|
||||
* A bitmap indicating the MSDUQs that the scheduler is attempting to
|
||||
* transmit in this PPDU. Note that in some cases, the scheduler's notion
|
||||
* of what MSDUQs are being transmitted from may not be fully accurate,
|
||||
* such as when MPDUs are retried, or when some previously generated MPDUs
|
||||
* that were not attempted OTA yet are tried.
|
||||
*
|
||||
* The valid bit indices for this bitmap are defined by the HTT_MSDUQ_INDEX
|
||||
* enum (in htt.h). For example, (1 << HTT_MSDUQ_INDEX_UDP) would
|
||||
* correspond to the default UDP msduq.
|
||||
*/
|
||||
A_UINT32 msduq_bitmap;
|
||||
} htt_ppdu_stats_user_common_tlv;
|
||||
|
||||
#define HTT_PPDU_STATS_USER_RATE_TLV_TID_NUM_M 0x000000ff
|
||||
|
|
|
|||
|
|
@ -147,6 +147,7 @@ enum htt_dbg_ext_stats_type {
|
|||
* 5 bit htt_rx_tid_stats_tlv
|
||||
* 6 bit htt_msdu_flow_stats_tlv
|
||||
* 7 bit htt_peer_sched_stats_tlv
|
||||
* 8 bit htt_peer_ax_ofdma_stats_tlv
|
||||
* - config_param2: [Bit31 : Bit0] mac_addr31to0
|
||||
* - config_param3: [Bit15 : Bit0] mac_addr47to32
|
||||
* [Bit 16] If this bit is set, reset per peer stats
|
||||
|
|
@ -510,6 +511,14 @@ enum htt_dbg_ext_stats_type {
|
|||
*/
|
||||
HTT_DBG_EXT_STATS_PDEV_BW_MGR = 53,
|
||||
|
||||
/** HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS
|
||||
* PARAMS:
|
||||
* - No Params
|
||||
* RESP MSG:
|
||||
* - htt_pdev_mbssid_ctrl_frame_stats
|
||||
*/
|
||||
HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS = 54,
|
||||
|
||||
|
||||
/* keep this last */
|
||||
HTT_DBG_NUM_EXT_STATS = 256,
|
||||
|
|
@ -919,6 +928,20 @@ typedef struct {
|
|||
A_UINT32 flush_errs[1]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */
|
||||
} htt_tx_pdev_stats_flush_tlv_v;
|
||||
|
||||
#define HTT_TX_PDEV_STATS_MLO_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
|
||||
/* NOTE: Variable length TLV, use length spec to infer array size */
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
A_UINT32 mlo_abort_cnt[]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */
|
||||
} htt_tx_pdev_stats_mlo_abort_tlv_v;
|
||||
|
||||
#define HTT_TX_PDEV_STATS_MLO_TXOP_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
|
||||
/* NOTE: Variable length TLV, use length spec to infer array size */
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
A_UINT32 mlo_txop_abort_cnt[]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */
|
||||
} htt_tx_pdev_stats_mlo_txop_abort_tlv_v;
|
||||
|
||||
#define HTT_TX_PDEV_STATS_SIFS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
|
||||
/* NOTE: Variable length TLV, use length spec to infer array size */
|
||||
typedef struct {
|
||||
|
|
@ -940,13 +963,24 @@ typedef struct {
|
|||
* that particular value for the MU EDCA parameter in question.
|
||||
*/
|
||||
#define HTT_STATS_MUEDCA_VALUE_MAX 16
|
||||
typedef struct {
|
||||
typedef struct { /* DEPRECATED */
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
A_UINT32 aifs[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX];
|
||||
A_UINT32 cw_min[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX];
|
||||
A_UINT32 cw_max[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX];
|
||||
} htt_tx_pdev_muedca_params_stats_tlv_v;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
A_UINT32 relaxed_mu_edca[HTT_NUM_AC_WMM];
|
||||
A_UINT32 mumimo_aggressive_mu_edca[HTT_NUM_AC_WMM];
|
||||
A_UINT32 mumimo_relaxed_mu_edca[HTT_NUM_AC_WMM];
|
||||
A_UINT32 muofdma_aggressive_mu_edca[HTT_NUM_AC_WMM];
|
||||
A_UINT32 muofdma_relaxed_mu_edca[HTT_NUM_AC_WMM];
|
||||
A_UINT32 latency_mu_edca[HTT_NUM_AC_WMM];
|
||||
A_UINT32 psd_boost_mu_edca[HTT_NUM_AC_WMM];
|
||||
} htt_tx_pdev_mu_edca_params_stats_tlv_v;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
A_UINT32 ul_mumimo_less_aggressive[HTT_NUM_AC_WMM];
|
||||
|
|
@ -1804,16 +1838,17 @@ typedef enum {
|
|||
} htt_peer_stats_req_mode_t;
|
||||
|
||||
typedef enum {
|
||||
HTT_PEER_STATS_CMN_TLV = 0,
|
||||
HTT_PEER_DETAILS_TLV = 1,
|
||||
HTT_TX_PEER_RATE_STATS_TLV = 2,
|
||||
HTT_RX_PEER_RATE_STATS_TLV = 3,
|
||||
HTT_TX_TID_STATS_TLV = 4,
|
||||
HTT_RX_TID_STATS_TLV = 5,
|
||||
HTT_MSDU_FLOW_STATS_TLV = 6,
|
||||
HTT_PEER_SCHED_STATS_TLV = 7,
|
||||
HTT_PEER_STATS_CMN_TLV = 0,
|
||||
HTT_PEER_DETAILS_TLV = 1,
|
||||
HTT_TX_PEER_RATE_STATS_TLV = 2,
|
||||
HTT_RX_PEER_RATE_STATS_TLV = 3,
|
||||
HTT_TX_TID_STATS_TLV = 4,
|
||||
HTT_RX_TID_STATS_TLV = 5,
|
||||
HTT_MSDU_FLOW_STATS_TLV = 6,
|
||||
HTT_PEER_SCHED_STATS_TLV = 7,
|
||||
HTT_PEER_AX_OFDMA_STATS_TLV = 8,
|
||||
|
||||
HTT_PEER_STATS_MAX_TLV = 31,
|
||||
HTT_PEER_STATS_MAX_TLV = 31,
|
||||
} htt_peer_stats_tlv_enum;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -1832,6 +1867,31 @@ typedef struct {
|
|||
A_UINT32 peer_curr_rate_kbps;
|
||||
} htt_peer_sched_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
A_UINT32 peer_id;
|
||||
A_UINT32 ax_basic_trig_count;
|
||||
A_UINT32 ax_basic_trig_err;
|
||||
A_UINT32 ax_bsr_trig_count;
|
||||
A_UINT32 ax_bsr_trig_err;
|
||||
A_UINT32 ax_mu_bar_trig_count;
|
||||
A_UINT32 ax_mu_bar_trig_err;
|
||||
A_UINT32 ax_basic_trig_with_per;
|
||||
A_UINT32 ax_bsr_trig_with_per;
|
||||
A_UINT32 ax_mu_bar_trig_with_per;
|
||||
/* is_airtime_large_for_dl_ofdma, is_airtime_large_for_ul_ofdma
|
||||
* These fields contain 2 counters each. The first element in each
|
||||
* array counts how many times the airtime is short enough to use
|
||||
* OFDMA, and the second element in each array counts how many times the
|
||||
* airtime is too large to select OFDMA for the PPDUs involving the peer.
|
||||
*/
|
||||
A_UINT32 is_airtime_large_for_dl_ofdma[2];
|
||||
A_UINT32 is_airtime_large_for_ul_ofdma[2];
|
||||
/* Last updated value of DL and UL queue depths for each peer per AC */
|
||||
A_UINT32 last_updated_dl_qdepth[HTT_NUM_AC_WMM];
|
||||
A_UINT32 last_updated_ul_qdepth[HTT_NUM_AC_WMM];
|
||||
} htt_peer_ax_ofdma_stats_tlv;
|
||||
|
||||
/* config_param0 */
|
||||
|
||||
#define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_M 0x00000001
|
||||
|
|
@ -1902,6 +1962,7 @@ typedef struct {
|
|||
* - HTT_STATS_PEER_MSDU_FLOWQ_TAG (multiple)
|
||||
* - HTT_STATS_TX_TID_DETAILS_V1_TAG (multiple)
|
||||
* - HTT_STATS_PEER_SCHED_STATS_TAG
|
||||
* - HTT_STATS_PEER_AX_OFDMA_STATS_TAG
|
||||
*/
|
||||
/* NOTE:
|
||||
* This structure is for documentation, and cannot be safely used directly.
|
||||
|
|
@ -1919,6 +1980,7 @@ typedef struct _htt_peer_stats {
|
|||
htt_msdu_flow_stats_tlv msdu_flowq[1];
|
||||
htt_tx_tid_stats_v1_tlv tx_tid_stats_v1[1];
|
||||
htt_peer_sched_stats_tlv peer_sched_stats;
|
||||
htt_peer_ax_ofdma_stats_tlv ax_ofdma_stats;
|
||||
} htt_peer_stats_t;
|
||||
|
||||
/* =========== ACTIVE PEER LIST ========== */
|
||||
|
|
@ -2336,6 +2398,7 @@ typedef struct {
|
|||
A_UINT32 su_sw_rts_flushed;
|
||||
/** CTS (RTS response) received in different BW */
|
||||
A_UINT32 su_sw_rts_rcvd_cts_diff_bw;
|
||||
/* START DEPRECATED FIELDS */
|
||||
/** 11AX HE MU Combined Freq. BSRP Trigger frame sent over the air */
|
||||
A_UINT32 combined_ax_bsr_trigger_tried[HTT_NUM_AC_WMM];
|
||||
/** 11AX HE MU Combined Freq. BSRP Trigger completed with error(s) */
|
||||
|
|
@ -2344,6 +2407,7 @@ typedef struct {
|
|||
A_UINT32 standalone_ax_bsr_trigger_tried[HTT_NUM_AC_WMM];
|
||||
/** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */
|
||||
A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM];
|
||||
/* END DEPRECATED FIELDS */
|
||||
} htt_tx_selfgen_cmn_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -2427,6 +2491,14 @@ typedef struct {
|
|||
* successfully sent over the air
|
||||
*/
|
||||
A_UINT32 ax_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS];
|
||||
/** 11AX HE MU Combined Freq. BSRP Trigger frame sent over the air */
|
||||
A_UINT32 combined_ax_bsr_trigger_tried[HTT_NUM_AC_WMM];
|
||||
/** 11AX HE MU Combined Freq. BSRP Trigger completed with error(s) */
|
||||
A_UINT32 combined_ax_bsr_trigger_err[HTT_NUM_AC_WMM];
|
||||
/** 11AX HE MU Standalone Freq. BSRP Trigger frame sent over the air */
|
||||
A_UINT32 standalone_ax_bsr_trigger_tried[HTT_NUM_AC_WMM];
|
||||
/** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */
|
||||
A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM];
|
||||
} htt_tx_selfgen_ax_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -2466,6 +2538,14 @@ typedef struct {
|
|||
* successfully sent over the air
|
||||
*/
|
||||
A_UINT32 be_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS];
|
||||
/** 11BE EHT MU Combined Freq. BSRP Trigger frame sent over the air */
|
||||
A_UINT32 combined_be_bsr_trigger_tried[HTT_NUM_AC_WMM];
|
||||
/** 11BE EHT MU Combined Freq. BSRP Trigger completed with error(s) */
|
||||
A_UINT32 combined_be_bsr_trigger_err[HTT_NUM_AC_WMM];
|
||||
/** 11BE EHT MU Standalone Freq. BSRP Trigger frame sent over the air */
|
||||
A_UINT32 standalone_be_bsr_trigger_tried[HTT_NUM_AC_WMM];
|
||||
/** 11BE EHT MU Standalone Freq. BSRP Trigger completed with error(s) */
|
||||
A_UINT32 standalone_be_bsr_trigger_err[HTT_NUM_AC_WMM];
|
||||
} htt_tx_selfgen_be_stats_tlv;
|
||||
|
||||
typedef struct { /* DEPRECATED */
|
||||
|
|
@ -3819,6 +3899,7 @@ typedef struct {
|
|||
A_UINT32 total_get_mpdu_head_info_cmds_by_sched_algo_la_query;
|
||||
A_UINT32 total_get_mpdu_head_info_cmds_by_tac;
|
||||
A_UINT32 total_gen_mpdu_cmds_by_sched_algo_la_query;
|
||||
A_UINT32 high_prio_q_not_empty;
|
||||
} htt_tx_tqm_cmn_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -7294,6 +7375,11 @@ typedef struct {
|
|||
#define HTT_MAX_RX_PKT_CRC_PASS_CNT 8
|
||||
#define HTT_MAX_PER_BLK_ERR_CNT 20
|
||||
#define HTT_MAX_RX_OTA_ERR_CNT 14
|
||||
#define HTT_MAX_RX_PKT_CNT_EXT 4
|
||||
#define HTT_MAX_RX_PKT_CRC_PASS_CNT_EXT 4
|
||||
#define HTT_MAX_RX_PKT_MU_CNT 14
|
||||
#define HTT_MAX_TX_PKT_CNT 10
|
||||
#define HTT_MAX_PHY_TX_ABORT_CNT 10
|
||||
|
||||
typedef enum {
|
||||
HTT_STATS_CHANNEL_HALF_RATE = 0x0001, /* Half rate */
|
||||
|
|
@ -7434,6 +7520,38 @@ typedef struct {
|
|||
* [9-13]=RSVD
|
||||
*/
|
||||
A_UINT32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT];
|
||||
/** rx_pkt_cnt_ext -
|
||||
* Received EOP (end-of-packet) count per packet type for BE;
|
||||
* [0] = EHT; [1] = WUR; [2] = AZ; [3]=RVSD
|
||||
*/
|
||||
A_UINT32 rx_pkt_cnt_ext[HTT_MAX_RX_PKT_CNT_EXT];
|
||||
/** rx_pkt_crc_pass_cnt_ext -
|
||||
* Received EOP (end-of-packet) count per packet type for BE;
|
||||
* [0] = EHT; [1] = WUR; [2] = AZ; [3]=RVSD
|
||||
*/
|
||||
A_UINT32 rx_pkt_crc_pass_cnt_ext[HTT_MAX_RX_PKT_CRC_PASS_CNT_EXT];
|
||||
/** rx_pkt_mu_cnt -
|
||||
* RX MU MIMO+OFDMA packet count per packet type for BE;
|
||||
* [0] = 11ax OFDMA; [1] = 11ax OFDMA+MUMIMO; [2] = 11be OFDMA;
|
||||
* [3] = 11be OFDMA+MUMIMO; [4] = 11ax MIMO; [5] = 11be MIMO;
|
||||
* [6] = 11ax OFDMA; [7] = 11ax OFDMA+MUMIMO; [8] = 11be OFDMA;
|
||||
* [9] = 11be OFDMA+MUMIMO; [10] = 11ax MIMO; [11] = 11be MIMO;
|
||||
* [12-13]=RSVD
|
||||
*/
|
||||
A_UINT32 rx_pkt_mu_cnt[HTT_MAX_RX_PKT_MU_CNT];
|
||||
/** tx_pkt_cnt -
|
||||
* num of transfered packet count per packet type;
|
||||
* [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF;
|
||||
* [6]= EHT; [7] = WUR; [8] = AZ; [9]=RSVD; [6-8] = Applicable only for BE
|
||||
*/
|
||||
A_UINT32 tx_pkt_cnt[HTT_MAX_TX_PKT_CNT];
|
||||
/** phy_tx_abort_cnt -
|
||||
* phy tx abort after each tlv;
|
||||
* [0] = PRE-PHY desc tlv; [1] = PHY desc tlv; [2] = LSIGA tlv;
|
||||
* [3] = LSIGB tlv; [4] = Per User tlv; [5] = HESIGB tlv;
|
||||
* [6] = Service tlv; [7] = Tx Packet End tlv; [8-9]=RSVD;
|
||||
*/
|
||||
A_UINT32 phy_tx_abort_cnt[HTT_MAX_PHY_TX_ABORT_CNT];
|
||||
} htt_phy_counters_tlv;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -8536,6 +8654,25 @@ typedef struct {
|
|||
A_UINT32 dlofdma_disabled_consec_no_mpdus_success[HTT_NUM_AC_WMM];
|
||||
} htt_pdev_sched_algo_ofdma_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
/** mac_id__word:
|
||||
* BIT [ 7 : 0] :- mac_id
|
||||
* Use the HTT_STATS_CMN_MAC_ID_GET,_SET macros to
|
||||
* read/write this bitfield.
|
||||
* BIT [31 : 8] :- reserved
|
||||
*/
|
||||
A_UINT32 mac_id__word;
|
||||
A_UINT32 basic_trigger_across_bss;
|
||||
A_UINT32 basic_trigger_within_bss;
|
||||
A_UINT32 bsr_trigger_across_bss;
|
||||
A_UINT32 bsr_trigger_within_bss;
|
||||
A_UINT32 mu_rts_across_bss;
|
||||
A_UINT32 mu_rts_within_bss;
|
||||
A_UINT32 ul_mumimo_trigger_across_bss;
|
||||
A_UINT32 ul_mumimo_trigger_within_bss;
|
||||
} htt_pdev_mbssid_ctrl_frame_stats_tlv;
|
||||
|
||||
/*======= Bandwidth Manager stats ====================*/
|
||||
|
||||
#define HTT_BW_MGR_STATS_MAC_ID_M 0x000000ff
|
||||
|
|
|
|||
141
drivers/staging/fw-api/fw/txmon_tlvs.h
Normal file
141
drivers/staging/fw-api/fw/txmon_tlvs.h
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _TXMON_TLVS_H_
|
||||
#define _TXMON_TLVS_H_
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_M 0x0000ffff
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_S 0
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_M 0xffff0000
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_S 16
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_M 0x000000ff
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_S 0
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_MHZ_M 0x00ffff00
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_MHZ_S 8
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_M 0xffffffff
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_S 0
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_GET(_var) \
|
||||
(((_var) & TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_M) >> \
|
||||
TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_S)
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1, _val); \
|
||||
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_S)); \
|
||||
} while (0)
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_GET(_var) \
|
||||
(((_var) & TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_M) >> \
|
||||
TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_S)
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2, _val); \
|
||||
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_S)); \
|
||||
} while (0)
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_GET(_var) \
|
||||
(((_var) & TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_M) >> \
|
||||
TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_S)
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_PHY_MODE, _val); \
|
||||
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_S)); \
|
||||
} while (0)
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_MHZ_GET(_var) \
|
||||
(((_var) & TXMON_FW2SW_MON_FES_SETUP_MHZ_M) >> \
|
||||
TXMON_FW2SW_MON_FES_SETUP_MHZ_S)
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_MHZ_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_MHZ, _val); \
|
||||
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_MHZ_S)); \
|
||||
} while (0)
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_GET(_var) \
|
||||
(((_var) & TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_M) >> \
|
||||
TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_S)
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID, _val); \
|
||||
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_S)); \
|
||||
} while (0)
|
||||
|
||||
enum txmon_fw2sw_user_id {
|
||||
TXMON_FW2SW_TYPE_FES_SETUP = 0, /* Placed after FES_SETUP */
|
||||
TXMON_FW2SW_TYPE_FES_SETUP_USER = 1, /* Placed before FES_SETUP_COMPLETE */
|
||||
TXMON_FW2SW_TYPE_FES_SETUP_EXT = 2, /* Placed after FES_SETUP_COMPLETE */
|
||||
TXMON_FW2SW_TYPE_MAX = 4
|
||||
};
|
||||
|
||||
typedef struct txmon_fw2sw_fes_setup {
|
||||
A_UINT32 band_center_freq1 : 16,
|
||||
band_center_freq2 : 16;
|
||||
A_UINT32 phy_mode : 8, /* this field is filled with WLAN_PHY_MODE enum value */
|
||||
mhz : 16,
|
||||
reserved : 8;
|
||||
A_UINT32 schedule_id;
|
||||
} txmon_fw2sw_fes_setup_t;
|
||||
|
||||
typedef struct txmon_fw2sw_fes_setup_ext {
|
||||
A_UINT32 reserved;
|
||||
} txmon_fw2sw_fes_setup_ext_t;
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_M 0x0000003f
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_S 0
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_GET(_var) \
|
||||
(((_var) & TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_M) >> \
|
||||
TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_S)
|
||||
|
||||
#define TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID, _val); \
|
||||
((_var) |= ((_val) << TXMON_FW2SW_MON_FES_SETUP_USER_USER_ID_S)); \
|
||||
} while (0)
|
||||
|
||||
|
||||
typedef struct txmon_fw2sw_fes_setup_user {
|
||||
A_UINT32 user_id : 6,
|
||||
reserved : 24;
|
||||
} txmon_fw2sw_fes_setup_user_t;
|
||||
|
||||
struct txmon_fw2sw_mon_fes_setup_tlv {
|
||||
struct tlv_usr_32_hdr tag; /* tlv_usrid => TXMON_FW2SW_TYPE_FES_SETUP */
|
||||
struct txmon_fw2sw_fes_setup setup;
|
||||
};
|
||||
|
||||
struct txmon_fw2sw_mon_fes_setup_ext_tlv {
|
||||
struct tlv_usr_32_hdr tag; /* tlv_usrid => TXMON_FW2SW_TYPE_FES_SETUP_EXT*/
|
||||
struct txmon_fw2sw_fes_setup_ext setup_ext;
|
||||
};
|
||||
|
||||
struct txmon_fw2sw_mon_fes_setup_user_tlv {
|
||||
struct tlv_usr_32_hdr tag; /* tlv_usrid => TXMON_FW2SW_TYPE_FES_SETUP_USER */
|
||||
struct txmon_fw2sw_fes_setup_user user_setup;
|
||||
};
|
||||
|
||||
#endif /* _TXMON_TLVS_H_ */
|
||||
|
|
@ -141,6 +141,17 @@ typedef enum {
|
|||
WLAN_MODULE_XGAP, /* 0x66 */
|
||||
WLAN_MODULE_MLO_OWNERSHIP_UPDATE, /* 0x67 */
|
||||
|
||||
WLAN_MODULE_SCHED_ALGO_TXBF, /* 0x68 */
|
||||
WLAN_MODULE_SCHED_ALGO_DL_MU_MIMO, /* 0x69 */
|
||||
WLAN_MODULE_SCHED_ALGO_UL_MU_MIMO, /* 0x6a */
|
||||
WLAN_MODULE_SCHED_ALGO_DL_MU_OFDMA, /* 0x6b */
|
||||
WLAN_MODULE_SCHED_ALGO_UL_MU_OFDMA, /* 0x6c */
|
||||
WLAN_MODULE_SCHED_ALGO_SU, /* 0x6d */
|
||||
WLAN_MODULE_SCHED_ALGO_MLO, /* 0x6e */
|
||||
WLAN_MODULE_SCHED_ALGO_SAWF, /* 0x6f */
|
||||
WLAN_MODULE_BAR, /* 0x70 */
|
||||
WLAN_MODULE_SMART_TX, /* 0x71 */
|
||||
|
||||
|
||||
WLAN_MODULE_ID_MAX,
|
||||
WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2021 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
|
|
@ -563,7 +563,7 @@ typedef enum {
|
|||
WMI_SERVICE_DYNAMIC_VDEV_MAC_ADDR_UPDATE_SUPPORT = 310, /* FW supports dynamic vdev mac address updating */
|
||||
WMI_SERVICE_SAWF_LEVEL0 = 311, /* FW supports WMI_SAWF_SVC_CLASS CFG_CMD + DISABLE_CMD msgs */
|
||||
WMI_SERVICE_RTT_11AZ_NTB_SUPPORT = 312, /* FW support for 11AZ non trigger based ranging */
|
||||
WMI_SERVICE_RTT_11AZ_TB_SUPPORT = 313, /* FW support for 11AZ trigger based ranging */
|
||||
WMI_SERVICE_RTT_11AZ_TB_SUPPORT = 313, /* FW support for 11AZ trigger based ranging ISTA role */
|
||||
WMI_SERVICE_RTT_11AZ_MAC_SEC_SUPPORT = 314, /* FW support for 11AZ secure FTM */
|
||||
WMI_SERVICE_RTT_11AZ_MAC_PHY_SEC_SUPPORT = 315, /* FW support for 11AZ secure LTF + FTM */
|
||||
WMI_SERVICE_SPECTRAL_SESSION_INFO_SUPPORT = 316, /* Information corresponding to each Spectral scan session will be sent by the FW before the reports corresponding to that session are sent */
|
||||
|
|
@ -603,7 +603,14 @@ typedef enum {
|
|||
WMI_SERVICE_WMI_SERVICE_WPA3_SHA384_ROAM_SUPPORT = 350, /* Indicates FW supports WPA3 SHA384 roaming */
|
||||
WMI_SERVICE_ODD_LIVEDUMP_SUPPORT = 351, /* Support for ODD Livedump from the FW */
|
||||
WMI_SERVICE_EIRP_PREFERRED_SUPPORT = 352, /* Support for OOBE feature where only EIRP powers will be sent in 6 GHz TPC WMI */
|
||||
|
||||
WMI_SERVICE_RTT_TX_RX_CHAIN_IDX_SUPPORT = 353, /* FW Supports configuring Tx and Rx Chainmask in intiator and Responder */
|
||||
WMI_SERVICE_RESTRICTED_TWT = 354, /* Support for R-TWT feature */
|
||||
WMI_SERVICE_SLO_SUPPORTED = 355, /* Support for Single Link 11BE */
|
||||
WMI_SERVICE_RTT_11AZ_TB_RSTA_SUPPORT = 356, /* FW support for 11AZ trigger based ranging Responder (RSTA) role */
|
||||
WMI_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357,
|
||||
WMI_SERVICE_DETERMINISTIC_SCHEDULER_LEVEL0 = 358, /* FW supports 12.2 level scheduler mode disable commands and stats */
|
||||
WMI_SERVICE_COORDINATED_AP_TDMA = 359, /* Support for Coordinated-AP TDMA feature */
|
||||
WMI_SERVICE_HPA_SUPPORT = 360, /* Support for Host Platform Authentication */
|
||||
|
||||
WMI_MAX_EXT2_SERVICE
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2021 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
|
|
@ -1303,6 +1303,39 @@ typedef enum {
|
|||
WMITLV_TAG_STRUC_wmi_livedump_request_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_livedump_response_event_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_prb_resp_tmpl_ml_info,
|
||||
WMITLV_TAG_STRUC_wmi_mlo_link_removal_tbtt_count,
|
||||
WMITLV_TAG_STRUC_wmi_mlo_link_removal_tbtt_update,
|
||||
WMITLV_TAG_STRUC_wmi_mlo_link_removal_evt_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_mlo_link_removal_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_reason_cmm_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_rssi_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_bss_load_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_deauth_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_btm_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_bmiss_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_dense_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_force_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_kickout_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_per_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_periodic_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_trigger_hi_rssi_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_mlo_bcast_t2lm_info,
|
||||
WMITLV_TAG_STRUC_wmi_mlo_ap_vdev_tid_to_link_map_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_mlo_ap_vdev_tid_to_link_map_evt_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_mlo_ap_vdev_tid_to_link_map_ie_info,
|
||||
WMITLV_TAG_STRUC_wmi_vdev_set_twt_edca_params_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_pifs_params,
|
||||
WMITLV_TAG_STRUC_wmi_tas_power_history_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_tas_power_history_event_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_ctrl_path_pmlo_stats_struct,
|
||||
WMITLV_TAG_STRUC_wmi_ctrl_path_cfr_stats_struct,
|
||||
WMITLV_TAG_STRUC_WMI_COEX_FIX_CHANNEL_CAPABILITIES,
|
||||
WMITLV_TAG_STRUC_wmi_peer_sched_mode_disable_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_per_peer_sched_mode_disable,
|
||||
WMITLV_TAG_STRUC_wmi_esl_egid_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_tdma_schedule_request_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_hpa_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_hpa_evt_fixed_param,
|
||||
} WMITLV_TAG_ID;
|
||||
|
||||
/*
|
||||
|
|
@ -1813,6 +1846,14 @@ typedef enum {
|
|||
OP(WMI_XGAP_ENABLE_CMDID) \
|
||||
OP(WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID) \
|
||||
OP(WMI_ODD_LIVEDUMP_REQUEST_CMDID) \
|
||||
OP(WMI_MLO_LINK_REMOVAL_CMDID) \
|
||||
OP(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID) \
|
||||
OP(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID) \
|
||||
OP(WMI_TAS_POWER_HISTORY_CMDID) \
|
||||
OP(WMI_PEER_SCHED_MODE_DISABLE_CMDID) \
|
||||
OP(WMI_ESL_EGID_CMDID) \
|
||||
OP(WMI_TDMA_SCHEDULE_REQUEST_CMDID) \
|
||||
OP(WMI_HPA_CMDID) \
|
||||
/* add new CMD_LIST elements above this line */
|
||||
|
||||
|
||||
|
|
@ -2108,6 +2149,10 @@ typedef enum {
|
|||
OP(WMI_PDEV_SCHED_TIDQ_SUSP_INFO_EVENTID) \
|
||||
OP(WMI_XGAP_ENABLE_COMPLETE_EVENTID) \
|
||||
OP(WMI_ODD_LIVEDUMP_RESPONSE_EVENTID) \
|
||||
OP(WMI_MLO_LINK_REMOVAL_EVENTID) \
|
||||
OP(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID) \
|
||||
OP(WMI_TAS_POWER_HISTORY_EVENTID) \
|
||||
OP(WMI_HPA_EVENTID) \
|
||||
/* add new EVT_LIST elements above this line */
|
||||
|
||||
|
||||
|
|
@ -3434,6 +3479,13 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_WMM_DELTS_CMDID);
|
|||
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_WMM_PARAMS_CMDID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_twt_edca_params_cmd_fixed_param, wmi_vdev_set_twt_edca_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wmm_params, wmm_params, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pifs_params, pifs_params, WMITLV_SIZE_VAR)
|
||||
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_VDEV_SET_GTX_PARAMS_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_gtx_params_cmd_fixed_param, wmi_vdev_set_gtx_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
|
||||
|
|
@ -4306,6 +4358,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TX_FILTER_CMDID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_pn_mgmt_rx_filter_cmd_fixed_param, wmi_vdev_pn_mgmt_rx_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PN_MGMT_RX_FILTER_CMDID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_ESL_EGID_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_esl_egid_cmd_fixed_param, wmi_esl_egid_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ESL_EGID_CMDID);
|
||||
|
||||
/* update a wds (4 address) entry */
|
||||
#define WMITLV_TABLE_WMI_PEER_UPDATE_WDS_ENTRY_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_update_wds_entry_cmd_fixed_param, wmi_peer_update_wds_entry_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
|
|
@ -4598,7 +4654,19 @@ WMITLV_CREATE_PARAM_STRUC(WMI_WLM_CONFIG_CMDID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_initial_info, roam_initial_info, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_btm_response_info, roam_btm_response_info, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_msg_info, roam_msg_info, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_btm_request_candidate_info, roam_btm_request_candidate_info, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_btm_request_candidate_info, roam_btm_request_candidate_info, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_reason_cmm, roam_trigger_reason_cmm, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_rssi, roam_trigger_rssi, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_bss_load, roam_trigger_bss_load, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_deauth, roam_trigger_deauth, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_btm, roam_trigger_btm, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_bmiss, roam_trigger_bmiss, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_dense, roam_trigger_dense, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_force, roam_trigger_force, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_kickout, roam_trigger_kickout, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_per, roam_trigger_per, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_periodic, roam_trigger_periodic, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_hi_rssi, roam_trigger_hi_rssi, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_STATS_EVENTID);
|
||||
|
||||
/* Motion detection cmd */
|
||||
|
|
@ -4959,7 +5027,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID
|
|||
#define WMITLV_TABLE_WMI_MLO_LINK_SET_ACTIVE_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_set_active_cmd_fixed_param, wmi_mlo_link_set_active_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_set_active_link_number_param, link_number_param, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_id_bitmap, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_id_bitmap, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_id_bitmap2, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_ACTIVE_CMDID);
|
||||
|
||||
/* Request DPD Status */
|
||||
|
|
@ -4999,6 +5068,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_TEARDOWN_CMDID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tid_to_link_map, tid_to_link_map, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID);
|
||||
|
||||
/** WMI cmd used to setup Tid to Link Mapping for a vdev */
|
||||
#define WMITLV_TABLE_WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_ap_vdev_tid_to_link_map_cmd_fixed_param, wmi_mlo_ap_vdev_tid_to_link_map_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_ap_vdev_tid_to_link_map_ie_info, mlo_vdev_tid_to_link_map_ie_info, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID);
|
||||
|
||||
/* Mcast ipv4 address filter list cmd */
|
||||
#define WMITLV_TABLE_WMI_VDEV_IGMP_OFFLOAD_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_igmp_offload_fixed_param, wmi_igmp_offload_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
|
|
@ -5160,6 +5235,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_WOW_COAP_GET_BUF_INFO_CMDID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_dbam_cmd_fixed_param, wmi_coex_dbam_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_COEX_DBAM_CMDID);
|
||||
|
||||
/* coex TAS power history cmd */
|
||||
#define WMITLV_TABLE_WMI_TAS_POWER_HISTORY_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tas_power_history_cmd_fixed_param, wmi_tas_power_history_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_TAS_POWER_HISTORY_CMDID);
|
||||
|
||||
/* VDEV SR prohibit cmd */
|
||||
#define WMITLV_TABLE_WMI_VDEV_PARAM_ENABLE_SR_PROHIBIT_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_param_enable_sr_prohibit_fixed_param, wmi_vdev_param_enable_sr_prohibit_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
|
|
@ -5175,6 +5255,21 @@ WMITLV_CREATE_PARAM_STRUC(WMI_XGAP_ENABLE_CMDID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_livedump_id_list, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ODD_LIVEDUMP_REQUEST_CMDID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_PEER_SCHED_MODE_DISABLE_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_sched_mode_disable_fixed_param, wmi_peer_sched_mode_disable_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_per_peer_sched_mode_disable, peer_info, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SCHED_MODE_DISABLE_CMDID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_TDMA_SCHEDULE_REQUEST_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdma_schedule_request_cmd_fixed_param, wmi_tdma_schedule_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_TDMA_SCHEDULE_REQUEST_CMDID);
|
||||
|
||||
/* HPA cmd */
|
||||
#define WMITLV_TABLE_WMI_HPA_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hpa_cmd_fixed_param, wmi_hpa_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, data, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_HPA_CMDID);
|
||||
|
||||
|
||||
|
||||
/************************** TLV definitions of WMI events *******************************/
|
||||
|
|
@ -5229,7 +5324,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbs_or_sbs_cap_ext, dbs_or_sbs_cap_ext, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cust_bdf_version_capabilities, cust_bdf_version_capabilities, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sw_cal_ver_cap, sw_cal_ver_cap, WMITLV_SIZE_VAR) \
|
||||
WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_INT32, A_INT32, hw_tx_power_signed, WMITLV_SIZE_FIX, WMI_HW_TX_POWER_CAPS_MAX)
|
||||
WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_INT32, A_INT32, hw_tx_power_signed, WMITLV_SIZE_FIX, WMI_HW_TX_POWER_CAPS_MAX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_COEX_FIX_CHANNEL_CAPABILITIES, coex_fix_channel_caps, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \
|
||||
|
|
@ -5442,7 +5538,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STA_KICKOUT_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_frame_pn_params, pn_params, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mgmt_ml_info, ml_info, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bpcc_bufp, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_is_my_mgmt_frame, my_frame, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_is_my_mgmt_frame, my_frame, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_removal_tbtt_count, link_removal_tbtt_count, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_bcast_t2lm_info, mlo_bcast_t2lm_info, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID);
|
||||
|
||||
/* Management Rx FW Consumed Event */
|
||||
|
|
@ -6604,7 +6702,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_btcoex_stats_struct, ctrl_path_btcoex_stats, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_bmiss_stats_struct, ctrl_path_bmiss_stats, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_odd_addr_read_struct, ctrl_path_odd_addr_read, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_afc_stats_struct, ctrl_path_afc_stats, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_afc_stats_struct, ctrl_path_afc_stats, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pmlo_stats_struct, ctrl_path_pmlo_stats, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_cfr_stats_struct, ctrl_path_cfr_stats, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID);
|
||||
|
||||
/*
|
||||
|
|
@ -7008,6 +7108,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_WOW_COAP_BUF_INFO_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_dbam_complete_event_fixed_param, wmi_coex_dbam_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_COEX_DBAM_COMPLETE_EVENTID);
|
||||
|
||||
/* coex TAS power history cmd complete event */
|
||||
#define WMITLV_TABLE_WMI_TAS_POWER_HISTORY_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tas_power_history_event_fixed_param, wmi_tas_power_history_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_TAS_POWER_HISTORY_EVENTID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_HEALTH_MON_INIT_DONE_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_health_mon_init_done_fixed_param, wmi_health_mon_init_done_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_HEALTH_MON_INIT_DONE_EVENTID);
|
||||
|
|
@ -7022,6 +7127,25 @@ WMITLV_CREATE_PARAM_STRUC(WMI_XGAP_ENABLE_COMPLETE_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_livedump_response_event_fixed_param, wmi_livedump_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ODD_LIVEDUMP_RESPONSE_EVENTID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_MLO_LINK_REMOVAL_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_removal_cmd_fixed_param, wmi_mlo_link_removal_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, reconfig_ml_ie, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_REMOVAL_CMDID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_MLO_LINK_REMOVAL_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_removal_evt_fixed_param, wmi_mlo_link_removal_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_removal_tbtt_update, wmi_mlo_link_removal_tbtt_update, tbtt_update, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_REMOVAL_EVENTID);
|
||||
|
||||
/* WMI MLO T2LM Vdev event */
|
||||
#define WMITLV_TABLE_WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_ap_vdev_tid_to_link_map_evt_fixed_param, wmi_mlo_ap_vdev_tid_to_link_map_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID);
|
||||
|
||||
/* HPA Event */
|
||||
#define WMITLV_TABLE_WMI_HPA_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hpa_evt_fixed_param, wmi_hpa_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_HPA_EVENTID);
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2012-2021 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
#define __WMI_VER_MINOR_ 0
|
||||
/** WMI revision number has to be incremented when there is a
|
||||
* change that may or may not break compatibility. */
|
||||
#define __WMI_REVISION_ 1224
|
||||
#define __WMI_REVISION_ 1260
|
||||
|
||||
/** The Version Namespace should not be normally changed. Only
|
||||
* host and firmware of the same WMI namespace will work
|
||||
|
|
|
|||
|
|
@ -12708,6 +12708,12 @@ out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),m,v,HWIO_REO_R0_C
|
|||
#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000
|
||||
#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23
|
||||
|
||||
#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_BMSK 0x40000
|
||||
#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT 18
|
||||
#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_BMSK 0x400
|
||||
#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT 10
|
||||
|
||||
|
||||
#define HWIO_TCL_R0_CMN_CONFIG_ADDR(x) ((x) + 0x24)
|
||||
#define HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK 0x400000
|
||||
#define HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT 22
|
||||
|
|
|
|||
Loading…
Reference in a new issue