arm64/dts: Update masks in codec Fs clock sequence

qc/LA.UM.9.14.r1-10900-LAHAINA.0, qc/LA.UM.9.16.r1-02100-MANNAR.0
Update masks in codec Fs clock sequence on lahaina target.

Change-Id: I850a3a0cfb527ac595cfa09a30989eafbd431bd7
Signed-off-by: liaohj <liaohj@lenovo.com>
Reviewed-on: https://gerrit.mot.com/1815835
SLTApproved: Slta Waiver
SME-Granted: SME Approvals Granted
Submit-Approved: Jira Key
Tested-by: Jira Key
Reviewed-by: Qinghong Yang <yangqh5@motorola.com>
This commit is contained in:
liaohj 2020-12-02 13:42:04 +08:00 • committed by panyq6
commit 1a34c6518b

View file

@ -67,7 +67,6 @@
qcom,msm-mi2s-tx-lines = <0>;
};
&q6core {
cdc_sec_mi2s_gpios: cdc_sec_mi2s_gpios {
compatible = "qcom,msm-cdc-pinctrl";
@ -87,8 +86,8 @@
#size-cells = <1>;
bolero-clk-rsc-mngr {
compatible = "qcom,bolero-clk-rsc-mngr";
qcom,fs-gen-sequence = <0x3000 0x1>,
<0x3004 0x1>, <0x3080 0x2>;
qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>,
<0x3004 0x3 0x1>, <0x3080 0x2 0x2>;
qcom,rx_mclk_mode_muxsel = <0x0A5640D8>;
qcom,va_mclk_mode_muxsel = <0x0A7A0000>;
clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
@ -131,6 +130,11 @@
<3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>,
<3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>;
qcom,swr-num-dev = <1>;
qcom,swr-phy-dev-addr = <0x0A 0x01170223>,
<0x08 0x58350223>,
<0x08 0x58350222>,
<0x08 0x58350221>,
<0x08 0x58350220>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-mstr-irq-wakeup-capable = <1>;
qcom,is-always-on = <1>;