From 1a49d0914f7d27c2a6fa642053646ff88e5d43b4 Mon Sep 17 00:00:00 2001
From: Satya Durga Srinivasu Prabhala <satyap@quicinc.com>
Date: Thu, 26 Sep 2019 10:27:49 -0700
Subject: [PATCH] ARM: dts: msm: add capacity and DPC properties for Lahaina

The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model which in turn used by EAS to take
placement decisions.

Change-Id: Ia44ffe4fcb799663c4bb47eb18f1ac79952ed12d
---
 qcom/lahaina.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index da9aad2e46f8..5b02ec1fb265 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -37,6 +37,8 @@
 			enable-method = "spin-table";
 			cache-size = <0x8000>;
 			cpu-release-addr = <0x0 0x90000000>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -59,6 +61,8 @@
 			enable-method = "spin-table";
 			cache-size = <0x8000>;
 			cpu-release-addr = <0x0 0x90000000>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -75,6 +79,8 @@
 			enable-method = "spin-table";
 			cache-size = <0x8000>;
 			cpu-release-addr = <0x0 0x90000000>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&L2_2>;
 			L2_2: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -91,6 +97,8 @@
 			enable-method = "spin-table";
 			cache-size = <0x8000>;
 			cpu-release-addr = <0x0 0x90000000>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&L2_3>;
 			L2_3: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -107,6 +115,8 @@
 			enable-method = "spin-table";
 			cache-size = <0x20000>;
 			cpu-release-addr = <0x0 0x90000000>;
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <454>;
 			next-level-cache = <&L2_4>;
 			L2_4: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -123,6 +133,8 @@
 			enable-method = "spin-table";
 			cache-size = <0x20000>;
 			cpu-release-addr = <0x0 0x90000000>;
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <454>;
 			next-level-cache = <&L2_5>;
 			L2_5: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -139,6 +151,8 @@
 			enable-method = "spin-table";
 			cache-size = <0x20000>;
 			cpu-release-addr = <0x0 0x90000000>;
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <454>;
 			next-level-cache = <&L2_6>;
 			L2_6: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -155,6 +169,8 @@
 			enable-method = "spin-table";
 			cache-size = <0x20000>;
 			cpu-release-addr = <0x0 0x90000000>;
+			capacity-dmips-mhz = <2048>;
+			dynamic-power-coefficient = <704>;
 			next-level-cache = <&L2_7>;
 			L2_7: l2-cache {
 			      compatible = "arm,arch-cache";