From 1a4e3a96c7604f3807448edc9c78e03cfcc7b0bf Mon Sep 17 00:00:00 2001 From: Manikanta Pubbisetty Date: Fri, 4 Sep 2020 18:39:47 +0530 Subject: [PATCH] qcacmn: add APIs to access CMEM Adding write/read APIs for accessing the CMEM. Currently in QCA6750, UMAC and CE windows are statically mapped, a new static window for CMEM is added for CMEM transactions. Change-Id: Ie10b33a6f468c6e4db314ea85856414962ef29e3 CRs-Fixed: 2771193 --- hal/wifi3.0/hal_api.h | 64 ++++++++++++++++++++++++++++++++++ hal/wifi3.0/hal_hw_headers.h | 6 ++++ hal/wifi3.0/qca6750/hal_6750.c | 31 ++++++++-------- 3 files changed, 86 insertions(+), 15 deletions(-) diff --git a/hal/wifi3.0/hal_api.h b/hal/wifi3.0/hal_api.h index 06a707e96509..8241085bb884 100644 --- a/hal/wifi3.0/hal_api.h +++ b/hal/wifi3.0/hal_api.h @@ -261,6 +261,8 @@ static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset, #define hal_write32_mb_confirm(_hal_soc, _offset, _value) \ hal_write32_mb(_hal_soc, _offset, _value) + +#define hal_write32_mb_cmem(_hal_soc, _offset, _value) #else static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset, uint32_t value) @@ -386,6 +388,35 @@ static inline void hal_write32_mb_confirm(struct hal_soc *hal_soc, } } } + +static inline void hal_write32_mb_cmem(struct hal_soc *hal_soc, uint32_t offset, + uint32_t value) +{ + unsigned long flags; + qdf_iomem_t new_addr; + + if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC( + hal_soc->hif_handle))) { + hal_err_rl("%s: target access is not allowed", __func__); + return; + } + + if (!hal_soc->use_register_windowing || + offset < MAX_UNWINDOWED_ADDRESS) { + qdf_iowrite32(hal_soc->dev_base_addr + offset, value); + } else if (hal_soc->static_window_map) { + new_addr = hal_get_window_address( + hal_soc, + hal_soc->dev_base_addr + offset); + qdf_iowrite32(new_addr, value); + } else { + hal_lock_reg_access(hal_soc, &flags); + hal_select_window_confirm(hal_soc, offset); + qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START + + (offset & WINDOW_RANGE_MASK), value); + hal_unlock_reg_access(hal_soc, &flags); + } +} #endif /** @@ -481,6 +512,8 @@ static inline uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset) return ret; } + +#define hal_read32_mb_cmem(_hal_soc, _offset) #else static uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset) @@ -531,6 +564,37 @@ uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset) return ret; } + +static inline +uint32_t hal_read32_mb_cmem(struct hal_soc *hal_soc, uint32_t offset) +{ + uint32_t ret; + unsigned long flags; + qdf_iomem_t new_addr; + + if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC( + hal_soc->hif_handle))) { + hal_err_rl("%s: target access is not allowed", __func__); + return 0; + } + + if (!hal_soc->use_register_windowing || + offset < MAX_UNWINDOWED_ADDRESS) { + ret = qdf_ioread32(hal_soc->dev_base_addr + offset); + } else if (hal_soc->static_window_map) { + new_addr = hal_get_window_address( + hal_soc, + hal_soc->dev_base_addr + offset); + ret = qdf_ioread32(new_addr); + } else { + hal_lock_reg_access(hal_soc, &flags); + hal_select_window_confirm(hal_soc, offset); + ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START + + (offset & WINDOW_RANGE_MASK)); + hal_unlock_reg_access(hal_soc, &flags); + } + return ret; +} #endif /* Max times allowed for register writing retry */ diff --git a/hal/wifi3.0/hal_hw_headers.h b/hal/wifi3.0/hal_hw_headers.h index 49aff583a367..3f69e3de4b68 100644 --- a/hal/wifi3.0/hal_hw_headers.h +++ b/hal/wifi3.0/hal_hw_headers.h @@ -122,6 +122,12 @@ #define HAL_REG_READ(_soc, _offset) \ hal_read32_mb(_soc, (_offset)) +#define HAL_CMEM_WRITE(_soc, _reg, _value) \ + hal_write32_mb_cmem(_soc, (_reg), (_value)) + +#define HAL_CMEM_READ(_soc, _offset) \ + hal_read32_mb_cmem(_soc, (_offset)) + #define WBM_IDLE_DESC_LIST 1 /** diff --git a/hal/wifi3.0/qca6750/hal_6750.c b/hal/wifi3.0/qca6750/hal_6750.c index 56b4eafdc062..233ee193d557 100644 --- a/hal/wifi3.0/qca6750/hal_6750.c +++ b/hal/wifi3.0/qca6750/hal_6750.c @@ -1323,6 +1323,7 @@ uint16_t hal_rx_get_rx_sequence_6750(uint8_t *buf) #define UMAC_WINDOW_REMAP_RANGE 0x14 #define CE_WINDOW_REMAP_RANGE 0x37 +#define CMEM_WINDOW_REMAP_RANGE 0x2 /** * hal_get_window_address_6750(): Function to get hp/tp address @@ -1334,33 +1335,33 @@ uint16_t hal_rx_get_rx_sequence_6750(uint8_t *buf) static inline qdf_iomem_t hal_get_window_address_6750(struct hal_soc *hal_soc, qdf_iomem_t addr) { - qdf_iomem_t new_addr; uint32_t offset; uint32_t window; + uint8_t scale; offset = addr - hal_soc->dev_base_addr; window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK; - /* - * If offset lies within UMAC register range, use 2nd window - */ - if (window == UMAC_WINDOW_REMAP_RANGE) { - new_addr = (hal_soc->dev_base_addr + WINDOW_START + - (offset & WINDOW_RANGE_MASK)); - /* - * If offset lies within CE register range, use 3rd window - */ - } else if (window == CE_WINDOW_REMAP_RANGE) { - new_addr = (hal_soc->dev_base_addr + (2 * WINDOW_START) + - (offset & WINDOW_RANGE_MASK)); - } else { + /* UMAC: 2nd window, CE: 3rd window, CMEM: 4th window */ + switch (window) { + case UMAC_WINDOW_REMAP_RANGE: + scale = 1; + break; + case CE_WINDOW_REMAP_RANGE: + scale = 2; + break; + case CMEM_WINDOW_REMAP_RANGE: + scale = 3; + break; + default: QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, "%s: ERROR: Accessing Wrong register\n", __func__); qdf_assert_always(0); return 0; } - return new_addr; + return hal_soc->dev_base_addr + (scale * WINDOW_START) + + (offset & WINDOW_RANGE_MASK); } /**