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ARM: dts: msm: Enable CPU cooling device for lahaina

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Enable CPU cooling device to mitigate the CPU frequency in lahaina.
Adding the #cooling-cells property will enable the cpufreq driver to
register CPU cooling device.

Change-Id: I50e2fcdcc259337d2f4501a75b1a756546cbbbd0
This commit is contained in:
Ram Chandrasekar 2020-03-19 14:47:08 -07:00
commit 1aaeb67b73
1 changed files with 8 additions and 0 deletions
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8
qcom/lahaina.dtsi
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@ -71,6 +71,7 @@
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@ -97,6 +98,7 @@
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@ -117,6 +119,7 @@
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@ -137,6 +140,7 @@
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_3>;
#cooling-cells = <2>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@ -157,6 +161,7 @@
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_4>;
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@ -177,6 +182,7 @@
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_5>;
#cooling-cells = <2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@ -197,6 +203,7 @@
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_6>;
#cooling-cells = <2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@ -217,6 +224,7 @@
dynamic-power-coefficient = <845>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_7>;
#cooling-cells = <2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;