From c8834d9bcc4728b2f2c7b0b9f64371a68dfdef20 Mon Sep 17 00:00:00 2001 From: Manikandan Mohan Date: Fri, 3 Apr 2020 16:30:20 -0700 Subject: [PATCH] cnss2: Add SRAM mem dump for debug Add SRAM region memory dump for debugging purposes on crash. Change-Id: Ie6e09322876ebdc020a5c8962068db761732d00c CRs-fixed: 2646824 Signed-off-by: Manikandan Mohan --- drivers/net/wireless/cnss2/pci.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c index 5bcb2cfe1685..28f0d70e9aa5 100644 --- a/drivers/net/wireless/cnss2/pci.c +++ b/drivers/net/wireless/cnss2/pci.c @@ -74,6 +74,9 @@ static DEFINE_SPINLOCK(time_sync_lock); #define LINK_TRAINING_RETRY_MAX_TIMES 3 +#define CNSS_DEBUG_DUMP_SRAM_START 0x1403D58 +#define CNSS_DEBUG_DUMP_SRAM_SIZE 10 + static struct cnss_pci_reg ce_src[] = { { "SRC_RING_BASE_LSB", QCA6390_CE_SRC_RING_BASE_LSB_OFFSET }, { "SRC_RING_BASE_MSB", QCA6390_CE_SRC_RING_BASE_MSB_OFFSET }, @@ -3734,6 +3737,19 @@ static void cnss_pci_dump_ce_reg(struct cnss_pci_data *pci_priv, } } +static void cnss_pci_dump_sram_mem(struct cnss_pci_data *pci_priv) +{ + int i; + u32 mem_addr, val; + + for (i = 0; i < CNSS_DEBUG_DUMP_SRAM_SIZE; i++) { + mem_addr = CNSS_DEBUG_DUMP_SRAM_START + i * 4; + if (cnss_pci_reg_read(pci_priv, mem_addr, &val)) + return; + cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val); + } +} + static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv) { cnss_pr_dbg("Start to dump debug registers\n"); @@ -3742,6 +3758,7 @@ static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv) return; mhi_debug_reg_dump(pci_priv->mhi_ctrl); + cnss_pci_dump_sram_mem(pci_priv); cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_COMMON); cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_09); cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_10);