From 1b25bc86023f9a350250459c5e2d06d859cd5557 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 26 Oct 2020 15:39:06 -0700 Subject: [PATCH] ARM: dts: msm: add MX entries to qcom,bw-scale for PCIe on lahaina Explicit MX voting and scaling is required for PCIe on some chipsets and there are updates to PCIe bus driver to support this. Although PCIe on lahaina does not need to explicitly vote for MX, updates to lahaina PCIe DT nodes are required to be compatible with the new qcom,bw-scale structure. Therefore, add MX entries to qcom,bw-scale for both PCIe nodes on lahaina. Change-Id: If707f61f78e4d99df118ebbfb516d639e5b4f851 --- qcom/lahaina-pcie.dtsi | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 9c106f0bd059..c72e6031377f 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -53,10 +53,18 @@ qcom,vreg-0p9-voltage-level = <880000 880000 47900>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen3 */ + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; @@ -284,10 +292,18 @@ qcom,vreg-0p9-voltage-level = <880000 880000 99000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen3 */ + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;