From ca7c75e5844a774ea6d9bb1da496cb5c7ba73774 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Sat, 26 Dec 2020 17:12:41 +0530 Subject: [PATCH] pinctrl: qcom: Enable clock while configuring slpi tlmm registers On some targets, the slpi pin controller seems to be un-clocked while trying to configure it. Enable clocked access while configuring the slpi tlmm registers. Also, move the initialization from arch_initcall to module_initcall due to the dependency with clock initialization. Change-Id: I678fbb790b3200c28227c58ee3611b37d655bb9f Signed-off-by: Yadu MG Signed-off-by: Shreyas K K --- drivers/pinctrl/qcom/pinctrl-slpi.c | 30 ++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-slpi.c b/drivers/pinctrl/qcom/pinctrl-slpi.c index 08a52dd182c7..8bb32ef8c4d0 100644 --- a/drivers/pinctrl/qcom/pinctrl-slpi.c +++ b/drivers/pinctrl/qcom/pinctrl-slpi.c @@ -13,10 +13,13 @@ #include #include #include +#include #include "../core.h" #include "../pinctrl-utils.h" +static struct clk *clk_ssc; + /** * struct slpi_pin - SLPI pin definition * @name: Name of the pin. @@ -146,6 +149,11 @@ static int slpi_pinmux_set_mux(struct pinctrl_dev *pctldev, { struct slpi_pin *pin; u32 val; + int ret; + + ret = clk_prepare_enable(clk_ssc); + if (ret) + return ret; pin = pctldev->desc->pins[pin_index].drv_data; @@ -157,6 +165,8 @@ static int slpi_pinmux_set_mux(struct pinctrl_dev *pctldev, val |= function << pin->mux_bit; slpi_write(val, pin, pin->ctl_reg); + clk_disable_unprepare(clk_ssc); + return 0; } @@ -218,6 +228,10 @@ static int slpi_config_group_get(struct pinctrl_dev *pctldev, int ret; u32 val; + ret = clk_prepare_enable(clk_ssc); + if (ret) + return ret; + pin = pctldev->desc->pins[pin_index].drv_data; ret = slpi_config_reg(pin, param, &mask, &bit); if (ret < 0) @@ -263,6 +277,8 @@ static int slpi_config_group_get(struct pinctrl_dev *pctldev, *config = pinconf_to_config_packed(param, arg); + clk_disable_unprepare(clk_ssc); + return 0; } @@ -280,6 +296,10 @@ static int slpi_config_group_set(struct pinctrl_dev *pctldev, u32 val; int i; + ret = clk_prepare_enable(clk_ssc); + if (ret) + return ret; + pin = pctldev->desc->pins[pin_index].drv_data; for (i = 0; i < num_configs; i++) { @@ -346,6 +366,8 @@ static int slpi_config_group_set(struct pinctrl_dev *pctldev, slpi_write(val, pin, pin->ctl_reg); } + clk_disable_unprepare(clk_ssc); + return 0; } @@ -372,6 +394,12 @@ static int slpi_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); + clk_ssc = devm_clk_get(dev, "ssc-clk"); + if (IS_ERR_OR_NULL(clk_ssc)) { + dev_err(dev, "Error in getting ssc-clk\n"); + return -EPROBE_DEFER; + } + ret = of_property_read_u32(dev->of_node, "qcom,num-pins", &npins); if (ret < 0) return ret; @@ -445,7 +473,7 @@ static int __init slpi_pinctrl_init(void) { return platform_driver_register(&slpi_pinctrl_driver); } -arch_initcall(slpi_pinctrl_init); +module_init(slpi_pinctrl_init); static void __exit slpi_pinctrl_exit(void) {