From 1b9adac1ff8e0a0e920b4d4e6cf8ca5fce507bfb Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 29 Jan 2020 22:21:12 -0800 Subject: [PATCH] msm: pcie: add support for gcc_aggre_noc_pcie_*_axi_clk PCIe root complex driver needs to support enable/disable gcc_aggre_noc_pcie*_axi_clk. Change-Id: I044d5081692d50ae82d5ab29c4913359719e5031 Signed-off-by: Tony Truong --- drivers/pci/controller/pci-msm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index 86a1f6f63c97..73907a7b2e35 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -167,7 +167,7 @@ #define MAX_PROP_SIZE (32) #define MAX_RC_NAME_LEN (15) #define MSM_PCIE_MAX_VREG (4) -#define MSM_PCIE_MAX_CLK (14) +#define MSM_PCIE_MAX_CLK (16) #define MSM_PCIE_MAX_PIPE_CLK (1) #define MAX_RC_NUM (3) #define MAX_DEVICE_NUM (20) @@ -858,6 +858,8 @@ static struct msm_pcie_clk_info_t {NULL, "pcie_phy_refgen_clk", 0, false, true}, {NULL, "pcie_tbu_clk", 0, false, true}, {NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true}, + {NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false}, + {NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false}, {NULL, "pcie_phy_cfg_ahb_clk", 0, false, false}, {NULL, "pcie_phy_aux_clk", 0, false, false} }, @@ -873,6 +875,8 @@ static struct msm_pcie_clk_info_t {NULL, "pcie_1_sleep_clk", 0, false, false}, {NULL, "pcie_phy_refgen_clk", 0, false, true}, {NULL, "pcie_tbu_clk", 0, false, true}, + {NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false}, + {NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false}, {NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true}, {NULL, "pcie_phy_cfg_ahb_clk", 0, false, false}, {NULL, "pcie_phy_aux_clk", 0, false, false} @@ -889,6 +893,8 @@ static struct msm_pcie_clk_info_t {NULL, "pcie_2_sleep_clk", 0, false, false}, {NULL, "pcie_phy_refgen_clk", 0, false, true}, {NULL, "pcie_tbu_clk", 0, false, true}, + {NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false}, + {NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false}, {NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true}, {NULL, "pcie_phy_cfg_ahb_clk", 0, false, false}, {NULL, "pcie_phy_aux_clk", 0, false, false}