mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
[PATCH] FRV: Use the generic IRQ stuff
Make the FRV arch use the generic IRQ code rather than having its own routines for doing so. Signed-off-by: David Howells <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
This commit is contained in:
David Howells
Linus Torvalds
parent
8d6b5eeea5
commit
1bcbba3060
18 changed files with 450 additions and 1221 deletions
|
|
@ -14,36 +14,6 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/irq-routing.h>
|
||||
|
||||
#define IRQ_BASE_CPU (NR_IRQ_ACTIONS_PER_GROUP * 0)
|
||||
|
||||
/* IRQ IDs presented to drivers */
|
||||
enum {
|
||||
IRQ_CPU__UNUSED = IRQ_BASE_CPU,
|
||||
IRQ_CPU_UART0,
|
||||
IRQ_CPU_UART1,
|
||||
IRQ_CPU_TIMER0,
|
||||
IRQ_CPU_TIMER1,
|
||||
IRQ_CPU_TIMER2,
|
||||
IRQ_CPU_DMA0,
|
||||
IRQ_CPU_DMA1,
|
||||
IRQ_CPU_DMA2,
|
||||
IRQ_CPU_DMA3,
|
||||
IRQ_CPU_DMA4,
|
||||
IRQ_CPU_DMA5,
|
||||
IRQ_CPU_DMA6,
|
||||
IRQ_CPU_DMA7,
|
||||
IRQ_CPU_EXTERNAL0,
|
||||
IRQ_CPU_EXTERNAL1,
|
||||
IRQ_CPU_EXTERNAL2,
|
||||
IRQ_CPU_EXTERNAL3,
|
||||
IRQ_CPU_EXTERNAL4,
|
||||
IRQ_CPU_EXTERNAL5,
|
||||
IRQ_CPU_EXTERNAL6,
|
||||
IRQ_CPU_EXTERNAL7,
|
||||
};
|
||||
|
||||
/* IRQ to level mappings */
|
||||
#define IRQ_GDBSTUB_LEVEL 15
|
||||
#define IRQ_UART_LEVEL 13
|
||||
|
|
@ -82,6 +52,30 @@ enum {
|
|||
#define IRQ_XIRQ6_LEVEL 7
|
||||
#define IRQ_XIRQ7_LEVEL 8
|
||||
|
||||
/* IRQ IDs presented to drivers */
|
||||
#define IRQ_CPU__UNUSED IRQ_BASE_CPU
|
||||
#define IRQ_CPU_UART0 (IRQ_BASE_CPU + IRQ_UART0_LEVEL)
|
||||
#define IRQ_CPU_UART1 (IRQ_BASE_CPU + IRQ_UART1_LEVEL)
|
||||
#define IRQ_CPU_TIMER0 (IRQ_BASE_CPU + IRQ_TIMER0_LEVEL)
|
||||
#define IRQ_CPU_TIMER1 (IRQ_BASE_CPU + IRQ_TIMER1_LEVEL)
|
||||
#define IRQ_CPU_TIMER2 (IRQ_BASE_CPU + IRQ_TIMER2_LEVEL)
|
||||
#define IRQ_CPU_DMA0 (IRQ_BASE_CPU + IRQ_DMA0_LEVEL)
|
||||
#define IRQ_CPU_DMA1 (IRQ_BASE_CPU + IRQ_DMA1_LEVEL)
|
||||
#define IRQ_CPU_DMA2 (IRQ_BASE_CPU + IRQ_DMA2_LEVEL)
|
||||
#define IRQ_CPU_DMA3 (IRQ_BASE_CPU + IRQ_DMA3_LEVEL)
|
||||
#define IRQ_CPU_DMA4 (IRQ_BASE_CPU + IRQ_DMA4_LEVEL)
|
||||
#define IRQ_CPU_DMA5 (IRQ_BASE_CPU + IRQ_DMA5_LEVEL)
|
||||
#define IRQ_CPU_DMA6 (IRQ_BASE_CPU + IRQ_DMA6_LEVEL)
|
||||
#define IRQ_CPU_DMA7 (IRQ_BASE_CPU + IRQ_DMA7_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL0 (IRQ_BASE_CPU + IRQ_XIRQ0_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL1 (IRQ_BASE_CPU + IRQ_XIRQ1_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL2 (IRQ_BASE_CPU + IRQ_XIRQ2_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL3 (IRQ_BASE_CPU + IRQ_XIRQ3_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL4 (IRQ_BASE_CPU + IRQ_XIRQ4_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL5 (IRQ_BASE_CPU + IRQ_XIRQ5_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL6 (IRQ_BASE_CPU + IRQ_XIRQ6_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL7 (IRQ_BASE_CPU + IRQ_XIRQ7_LEVEL)
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_CPU_IRQS_H */
|
||||
|
|
|
|||
|
|
@ -26,5 +26,10 @@ typedef struct {
|
|||
#error SMP not available on FR-V
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
extern atomic_t irq_err_count;
|
||||
static inline void ack_bad_irq(int irq)
|
||||
{
|
||||
atomic_inc(&irq_err_count);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,70 +0,0 @@
|
|||
/* irq-routing.h: multiplexed IRQ routing
|
||||
*
|
||||
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
|
||||
* Written by David Howells (dhowells@redhat.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_IRQ_ROUTING_H
|
||||
#define _ASM_IRQ_ROUTING_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
struct irq_source;
|
||||
struct irq_level;
|
||||
|
||||
/*
|
||||
* IRQ action distribution sets
|
||||
*/
|
||||
struct irq_group {
|
||||
int first_irq; /* first IRQ distributed here */
|
||||
void (*control)(struct irq_group *group, int index, int on);
|
||||
|
||||
struct irqaction *actions[NR_IRQ_ACTIONS_PER_GROUP]; /* IRQ action chains */
|
||||
struct irq_source *sources[NR_IRQ_ACTIONS_PER_GROUP]; /* IRQ sources */
|
||||
int disable_cnt[NR_IRQ_ACTIONS_PER_GROUP]; /* disable counts */
|
||||
};
|
||||
|
||||
/*
|
||||
* IRQ source manager
|
||||
*/
|
||||
struct irq_source {
|
||||
struct irq_source *next;
|
||||
struct irq_level *level;
|
||||
const char *muxname;
|
||||
volatile void __iomem *muxdata;
|
||||
unsigned long irqmask;
|
||||
|
||||
void (*doirq)(struct irq_source *source);
|
||||
};
|
||||
|
||||
/*
|
||||
* IRQ level management (per CPU IRQ priority / entry vector)
|
||||
*/
|
||||
struct irq_level {
|
||||
int usage;
|
||||
int disable_count;
|
||||
unsigned long flags; /* current IRQF_DISABLED and IRQF_SHARED settings */
|
||||
spinlock_t lock;
|
||||
struct irq_source *sources;
|
||||
};
|
||||
|
||||
extern struct irq_level frv_irq_levels[16];
|
||||
extern struct irq_group *irq_groups[NR_IRQ_GROUPS];
|
||||
|
||||
extern void frv_irq_route(struct irq_source *source, int irqlevel);
|
||||
extern void frv_irq_route_external(struct irq_source *source, int irq);
|
||||
extern void frv_irq_set_group(struct irq_group *group);
|
||||
extern void distribute_irqs(struct irq_group *group, unsigned long irqmask);
|
||||
extern void route_cpu_irqs(void);
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_IRQ_ROUTING_H */
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/* irq.h: FRV IRQ definitions
|
||||
*
|
||||
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
|
||||
* Written by David Howells (dhowells@redhat.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
|
@ -12,32 +12,22 @@
|
|||
#ifndef _ASM_IRQ_H_
|
||||
#define _ASM_IRQ_H_
|
||||
|
||||
|
||||
/*
|
||||
* the system has an on-CPU PIC and another PIC on the FPGA and other PICs on other peripherals,
|
||||
* so we do some routing in irq-routing.[ch] to reduce the number of false-positives seen by
|
||||
* drivers
|
||||
*/
|
||||
|
||||
/* this number is used when no interrupt has been assigned */
|
||||
#define NO_IRQ (-1)
|
||||
|
||||
#define NR_IRQ_LOG2_ACTIONS_PER_GROUP 5
|
||||
#define NR_IRQ_ACTIONS_PER_GROUP (1 << NR_IRQ_LOG2_ACTIONS_PER_GROUP)
|
||||
#define NR_IRQ_GROUPS 4
|
||||
#define NR_IRQS (NR_IRQ_ACTIONS_PER_GROUP * NR_IRQ_GROUPS)
|
||||
#define NR_IRQS 48
|
||||
#define IRQ_BASE_CPU (0 * 16)
|
||||
#define IRQ_BASE_FPGA (1 * 16)
|
||||
#define IRQ_BASE_MB93493 (2 * 16)
|
||||
|
||||
/* probe returns a 32-bit IRQ mask:-/ */
|
||||
#define MIN_PROBE_IRQ (NR_IRQS - 32)
|
||||
#define MIN_PROBE_IRQ (NR_IRQS - 32)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
static inline int irq_canonicalize(int irq)
|
||||
{
|
||||
return irq;
|
||||
}
|
||||
|
||||
extern void disable_irq_nosync(unsigned int irq);
|
||||
extern void disable_irq(unsigned int irq);
|
||||
extern void enable_irq(unsigned int irq);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_IRQ_H_ */
|
||||
|
|
|
|||
|
|
@ -12,12 +12,10 @@
|
|||
#ifndef _ASM_MB93091_FPGA_IRQS_H
|
||||
#define _ASM_MB93091_FPGA_IRQS_H
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/irq-routing.h>
|
||||
|
||||
#define IRQ_BASE_FPGA (NR_IRQ_ACTIONS_PER_GROUP * 1)
|
||||
|
||||
/* IRQ IDs presented to drivers */
|
||||
enum {
|
||||
IRQ_FPGA__UNUSED = IRQ_BASE_FPGA,
|
||||
|
|
|
|||
|
|
@ -12,12 +12,10 @@
|
|||
#ifndef _ASM_MB93093_FPGA_IRQS_H
|
||||
#define _ASM_MB93093_FPGA_IRQS_H
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/irq-routing.h>
|
||||
|
||||
#define IRQ_BASE_FPGA (NR_IRQ_ACTIONS_PER_GROUP * 1)
|
||||
|
||||
/* IRQ IDs presented to drivers */
|
||||
enum {
|
||||
IRQ_FPGA_PUSH_BUTTON_SW1_5 = IRQ_BASE_FPGA + 8,
|
||||
|
|
|
|||
|
|
@ -12,12 +12,10 @@
|
|||
#ifndef _ASM_MB93493_IRQS_H
|
||||
#define _ASM_MB93493_IRQS_H
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/irq-routing.h>
|
||||
|
||||
#define IRQ_BASE_MB93493 (NR_IRQ_ACTIONS_PER_GROUP * 2)
|
||||
|
||||
/* IRQ IDs presented to drivers */
|
||||
enum {
|
||||
IRQ_MB93493_VDC = IRQ_BASE_MB93493 + 0,
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include <asm/mb-regs.h>
|
||||
#include <asm/mb93493-irqs.h>
|
||||
|
||||
#define __addr_MB93493(X) ((volatile unsigned long *)(__region_CS3 + (X)))
|
||||
#define __get_MB93493(X) ({ *(volatile unsigned long *)(__region_CS3 + (X)); })
|
||||
|
||||
#define __set_MB93493(X,V) \
|
||||
|
|
@ -26,6 +27,7 @@ do { \
|
|||
#define __set_MB93493_STSR(X,V) __set_MB93493(0x3c0 + (X) * 4, (V))
|
||||
#define MB93493_STSR_EN
|
||||
|
||||
#define __addr_MB93493_IQSR(X) __addr_MB93493(0x3d0 + (X) * 4)
|
||||
#define __get_MB93493_IQSR(X) __get_MB93493(0x3d0 + (X) * 4)
|
||||
#define __set_MB93493_IQSR(X,V) __set_MB93493(0x3d0 + (X) * 4, (V))
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue