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msm: camera: isp: Add header files and hardware updates

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For lagoon, few changes in CSID and IFE  to handle the
dual vfe sync and halt.
For CSID, while handling the halt, external and internal
core configuration is changed.
For VFE, 3 IFE support is possible with the combinations:
0-1, 1-2, 0-2. This requires changes in dual vfe sync handling.
Also, CSID and IFE versions are updated.
This commit adds the driver header files for the version and
handles the hardware changes in the driver.

CRs-Fixed: 2571273
Change-Id: I48fd3319692cc1044beb20c278cc2fe5676cb668
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
Signed-off-by: Vishalsingh Hajeri <vhajeri@codeaurora.org>
This commit is contained in:
Gaurav Jindal 2019-12-10 18:45:03 +05:30 • committed by Gerrit - the friendly Code Review server
commit 1befcf3a1a
9 changed files with 1330 additions and 66 deletions
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368
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170_200.h Normal file
View file

@ -0,0 +1,368 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_IFE_CSID_170_200_H_
#define _CAM_IFE_CSID_170_200_H_
#include "cam_ife_csid_core.h"
static struct cam_ife_csid_pxl_reg_offset
cam_ife_csid_170_200_ipp_reg_offset = {
.csid_pxl_irq_status_addr = 0x30,
.csid_pxl_irq_mask_addr = 0x34,
.csid_pxl_irq_clear_addr = 0x38,
.csid_pxl_irq_set_addr = 0x3c,
.csid_pxl_cfg0_addr = 0x200,
.csid_pxl_cfg1_addr = 0x204,
.csid_pxl_ctrl_addr = 0x208,
.csid_pxl_frm_drop_pattern_addr = 0x20c,
.csid_pxl_frm_drop_period_addr = 0x210,
.csid_pxl_irq_subsample_pattern_addr = 0x214,
.csid_pxl_irq_subsample_period_addr = 0x218,
.csid_pxl_hcrop_addr = 0x21c,
.csid_pxl_vcrop_addr = 0x220,
.csid_pxl_pix_drop_pattern_addr = 0x224,
.csid_pxl_pix_drop_period_addr = 0x228,
.csid_pxl_line_drop_pattern_addr = 0x22c,
.csid_pxl_line_drop_period_addr = 0x230,
.csid_pxl_rst_strobes_addr = 0x240,
.csid_pxl_status_addr = 0x254,
.csid_pxl_misr_val_addr = 0x258,
.csid_pxl_format_measure_cfg0_addr = 0x270,
.csid_pxl_format_measure_cfg1_addr = 0x274,
.csid_pxl_format_measure0_addr = 0x278,
.csid_pxl_format_measure1_addr = 0x27c,
.csid_pxl_format_measure2_addr = 0x280,
.csid_pxl_timestamp_curr0_sof_addr = 0x290,
.csid_pxl_timestamp_curr1_sof_addr = 0x294,
.csid_pxl_timestamp_perv0_sof_addr = 0x298,
.csid_pxl_timestamp_perv1_sof_addr = 0x29c,
.csid_pxl_timestamp_curr0_eof_addr = 0x2a0,
.csid_pxl_timestamp_curr1_eof_addr = 0x2a4,
.csid_pxl_timestamp_perv0_eof_addr = 0x2a8,
.csid_pxl_timestamp_perv1_eof_addr = 0x2ac,
/* configurations */
.pix_store_en_shift_val = 7,
.early_eof_en_shift_val = 29,
.quad_cfa_bin_en_shift_val = 30,
.ccif_violation_en = 1,
.halt_master_sel_en = 1,
.halt_sel_internal_master_val = 3,
};
static struct cam_ife_csid_pxl_reg_offset
cam_ife_csid_170_200_ppp_reg_offset = {
.csid_pxl_irq_status_addr = 0xa0,
.csid_pxl_irq_mask_addr = 0xa4,
.csid_pxl_irq_clear_addr = 0xa8,
.csid_pxl_irq_set_addr = 0xac,
.csid_pxl_cfg0_addr = 0x700,
.csid_pxl_cfg1_addr = 0x704,
.csid_pxl_ctrl_addr = 0x708,
.csid_pxl_frm_drop_pattern_addr = 0x70c,
.csid_pxl_frm_drop_period_addr = 0x710,
.csid_pxl_irq_subsample_pattern_addr = 0x714,
.csid_pxl_irq_subsample_period_addr = 0x718,
.csid_pxl_hcrop_addr = 0x71c,
.csid_pxl_vcrop_addr = 0x720,
.csid_pxl_pix_drop_pattern_addr = 0x724,
.csid_pxl_pix_drop_period_addr = 0x728,
.csid_pxl_line_drop_pattern_addr = 0x72c,
.csid_pxl_line_drop_period_addr = 0x730,
.csid_pxl_rst_strobes_addr = 0x740,
.csid_pxl_status_addr = 0x754,
.csid_pxl_misr_val_addr = 0x758,
.csid_pxl_format_measure_cfg0_addr = 0x770,
.csid_pxl_format_measure_cfg1_addr = 0x774,
.csid_pxl_format_measure0_addr = 0x778,
.csid_pxl_format_measure1_addr = 0x77c,
.csid_pxl_format_measure2_addr = 0x780,
.csid_pxl_timestamp_curr0_sof_addr = 0x790,
.csid_pxl_timestamp_curr1_sof_addr = 0x794,
.csid_pxl_timestamp_perv0_sof_addr = 0x798,
.csid_pxl_timestamp_perv1_sof_addr = 0x79c,
.csid_pxl_timestamp_curr0_eof_addr = 0x7a0,
.csid_pxl_timestamp_curr1_eof_addr = 0x7a4,
.csid_pxl_timestamp_perv0_eof_addr = 0x7a8,
.csid_pxl_timestamp_perv1_eof_addr = 0x7ac,
/* configurations */
.pix_store_en_shift_val = 7,
.early_eof_en_shift_val = 29,
.ccif_violation_en = 1,
.halt_master_sel_en = 1,
.halt_sel_internal_master_val = 3,
};
static struct cam_ife_csid_rdi_reg_offset
cam_ife_csid_170_200_rdi_0_reg_offset = {
.csid_rdi_irq_status_addr = 0x40,
.csid_rdi_irq_mask_addr = 0x44,
.csid_rdi_irq_clear_addr = 0x48,
.csid_rdi_irq_set_addr = 0x4c,
.csid_rdi_cfg0_addr = 0x300,
.csid_rdi_cfg1_addr = 0x304,
.csid_rdi_ctrl_addr = 0x308,
.csid_rdi_frm_drop_pattern_addr = 0x30c,
.csid_rdi_frm_drop_period_addr = 0x310,
.csid_rdi_irq_subsample_pattern_addr = 0x314,
.csid_rdi_irq_subsample_period_addr = 0x318,
.csid_rdi_rpp_hcrop_addr = 0x31c,
.csid_rdi_rpp_vcrop_addr = 0x320,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x324,
.csid_rdi_rpp_pix_drop_period_addr = 0x328,
.csid_rdi_rpp_line_drop_pattern_addr = 0x32c,
.csid_rdi_rpp_line_drop_period_addr = 0x330,
.csid_rdi_rst_strobes_addr = 0x340,
.csid_rdi_status_addr = 0x350,
.csid_rdi_misr_val0_addr = 0x354,
.csid_rdi_misr_val1_addr = 0x358,
.csid_rdi_misr_val2_addr = 0x35c,
.csid_rdi_misr_val3_addr = 0x360,
.csid_rdi_format_measure_cfg0_addr = 0x370,
.csid_rdi_format_measure_cfg1_addr = 0x374,
.csid_rdi_format_measure0_addr = 0x378,
.csid_rdi_format_measure1_addr = 0x37c,
.csid_rdi_format_measure2_addr = 0x380,
.csid_rdi_timestamp_curr0_sof_addr = 0x390,
.csid_rdi_timestamp_curr1_sof_addr = 0x394,
.csid_rdi_timestamp_prev0_sof_addr = 0x398,
.csid_rdi_timestamp_prev1_sof_addr = 0x39c,
.csid_rdi_timestamp_curr0_eof_addr = 0x3a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x3a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x3a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x3ac,
.csid_rdi_byte_cntr_ping_addr = 0x3e0,
.csid_rdi_byte_cntr_pong_addr = 0x3e4,
.ccif_violation_en = 1,
};
static struct cam_ife_csid_rdi_reg_offset
cam_ife_csid_170_200_rdi_1_reg_offset = {
.csid_rdi_irq_status_addr = 0x50,
.csid_rdi_irq_mask_addr = 0x54,
.csid_rdi_irq_clear_addr = 0x58,
.csid_rdi_irq_set_addr = 0x5c,
.csid_rdi_cfg0_addr = 0x400,
.csid_rdi_cfg1_addr = 0x404,
.csid_rdi_ctrl_addr = 0x408,
.csid_rdi_frm_drop_pattern_addr = 0x40c,
.csid_rdi_frm_drop_period_addr = 0x410,
.csid_rdi_irq_subsample_pattern_addr = 0x414,
.csid_rdi_irq_subsample_period_addr = 0x418,
.csid_rdi_rpp_hcrop_addr = 0x41c,
.csid_rdi_rpp_vcrop_addr = 0x420,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x424,
.csid_rdi_rpp_pix_drop_period_addr = 0x428,
.csid_rdi_rpp_line_drop_pattern_addr = 0x42c,
.csid_rdi_rpp_line_drop_period_addr = 0x430,
.csid_rdi_rst_strobes_addr = 0x440,
.csid_rdi_status_addr = 0x450,
.csid_rdi_misr_val0_addr = 0x454,
.csid_rdi_misr_val1_addr = 0x458,
.csid_rdi_misr_val2_addr = 0x45c,
.csid_rdi_misr_val3_addr = 0x460,
.csid_rdi_format_measure_cfg0_addr = 0x470,
.csid_rdi_format_measure_cfg1_addr = 0x474,
.csid_rdi_format_measure0_addr = 0x478,
.csid_rdi_format_measure1_addr = 0x47c,
.csid_rdi_format_measure2_addr = 0x480,
.csid_rdi_timestamp_curr0_sof_addr = 0x490,
.csid_rdi_timestamp_curr1_sof_addr = 0x494,
.csid_rdi_timestamp_prev0_sof_addr = 0x498,
.csid_rdi_timestamp_prev1_sof_addr = 0x49c,
.csid_rdi_timestamp_curr0_eof_addr = 0x4a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x4a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x4a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x4ac,
.csid_rdi_byte_cntr_ping_addr = 0x4e0,
.csid_rdi_byte_cntr_pong_addr = 0x4e4,
.ccif_violation_en = 1,
};
static struct cam_ife_csid_rdi_reg_offset
cam_ife_csid_170_200_rdi_2_reg_offset = {
.csid_rdi_irq_status_addr = 0x60,
.csid_rdi_irq_mask_addr = 0x64,
.csid_rdi_irq_clear_addr = 0x68,
.csid_rdi_irq_set_addr = 0x6c,
.csid_rdi_cfg0_addr = 0x500,
.csid_rdi_cfg1_addr = 0x504,
.csid_rdi_ctrl_addr = 0x508,
.csid_rdi_frm_drop_pattern_addr = 0x50c,
.csid_rdi_frm_drop_period_addr = 0x510,
.csid_rdi_irq_subsample_pattern_addr = 0x514,
.csid_rdi_irq_subsample_period_addr = 0x518,
.csid_rdi_rpp_hcrop_addr = 0x51c,
.csid_rdi_rpp_vcrop_addr = 0x520,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x524,
.csid_rdi_rpp_pix_drop_period_addr = 0x528,
.csid_rdi_rpp_line_drop_pattern_addr = 0x52c,
.csid_rdi_rpp_line_drop_period_addr = 0x530,
.csid_rdi_yuv_chroma_conversion_addr = 0x534,
.csid_rdi_rst_strobes_addr = 0x540,
.csid_rdi_status_addr = 0x550,
.csid_rdi_misr_val0_addr = 0x554,
.csid_rdi_misr_val1_addr = 0x558,
.csid_rdi_misr_val2_addr = 0x55c,
.csid_rdi_misr_val3_addr = 0x560,
.csid_rdi_format_measure_cfg0_addr = 0x570,
.csid_rdi_format_measure_cfg1_addr = 0x574,
.csid_rdi_format_measure0_addr = 0x578,
.csid_rdi_format_measure1_addr = 0x57c,
.csid_rdi_format_measure2_addr = 0x580,
.csid_rdi_timestamp_curr0_sof_addr = 0x590,
.csid_rdi_timestamp_curr1_sof_addr = 0x594,
.csid_rdi_timestamp_prev0_sof_addr = 0x598,
.csid_rdi_timestamp_prev1_sof_addr = 0x59c,
.csid_rdi_timestamp_curr0_eof_addr = 0x5a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x5a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x5a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x5ac,
.csid_rdi_byte_cntr_ping_addr = 0x5e0,
.csid_rdi_byte_cntr_pong_addr = 0x5e4,
.ccif_violation_en = 1,
};
static struct cam_ife_csid_csi2_rx_reg_offset
cam_ife_csid_170_200_csi2_reg_offset = {
.csid_csi2_rx_irq_status_addr = 0x20,
.csid_csi2_rx_irq_mask_addr = 0x24,
.csid_csi2_rx_irq_clear_addr = 0x28,
.csid_csi2_rx_irq_set_addr = 0x2c,
/*CSI2 rx control */
.csid_csi2_rx_cfg0_addr = 0x100,
.csid_csi2_rx_cfg1_addr = 0x104,
.csid_csi2_rx_capture_ctrl_addr = 0x108,
.csid_csi2_rx_rst_strobes_addr = 0x110,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124,
.csid_csi2_rx_captured_short_pkt_0_addr = 0x128,
.csid_csi2_rx_captured_short_pkt_1_addr = 0x12c,
.csid_csi2_rx_captured_long_pkt_0_addr = 0x130,
.csid_csi2_rx_captured_long_pkt_1_addr = 0x134,
.csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138,
.csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c,
.csid_csi2_rx_lane0_misr_addr = 0x150,
.csid_csi2_rx_lane1_misr_addr = 0x154,
.csid_csi2_rx_lane2_misr_addr = 0x158,
.csid_csi2_rx_lane3_misr_addr = 0x15c,
.csid_csi2_rx_total_pkts_rcvd_addr = 0x160,
.csid_csi2_rx_stats_ecc_addr = 0x164,
.csid_csi2_rx_total_crc_err_addr = 0x168,
.csid_csi2_rx_de_scramble_type3_cfg0_addr = 0x170,
.csid_csi2_rx_de_scramble_type3_cfg1_addr = 0x174,
.csid_csi2_rx_de_scramble_type2_cfg0_addr = 0x178,
.csid_csi2_rx_de_scramble_type2_cfg1_addr = 0x17c,
.csid_csi2_rx_de_scramble_type1_cfg0_addr = 0x180,
.csid_csi2_rx_de_scramble_type1_cfg1_addr = 0x184,
.csid_csi2_rx_de_scramble_type0_cfg0_addr = 0x188,
.csid_csi2_rx_de_scramble_type0_cfg1_addr = 0x18c,
.csi2_rst_srb_all = 0x3FFF,
.csi2_rst_done_shift_val = 27,
.csi2_irq_mask_all = 0xFFFFFFF,
.csi2_misr_enable_shift_val = 6,
.csi2_vc_mode_shift_val = 2,
.csi2_capture_long_pkt_en_shift = 0,
.csi2_capture_short_pkt_en_shift = 1,
.csi2_capture_cphy_pkt_en_shift = 2,
.csi2_capture_long_pkt_dt_shift = 4,
.csi2_capture_long_pkt_vc_shift = 10,
.csi2_capture_short_pkt_vc_shift = 15,
.csi2_capture_cphy_pkt_dt_shift = 20,
.csi2_capture_cphy_pkt_vc_shift = 26,
.csi2_rx_phy_num_mask = 0x7,
};
static struct cam_ife_csid_csi2_tpg_reg_offset
cam_ife_csid_170_200_tpg_reg_offset = {
/*CSID TPG control */
.csid_tpg_ctrl_addr = 0x600,
.csid_tpg_vc_cfg0_addr = 0x604,
.csid_tpg_vc_cfg1_addr = 0x608,
.csid_tpg_lfsr_seed_addr = 0x60c,
.csid_tpg_dt_n_cfg_0_addr = 0x610,
.csid_tpg_dt_n_cfg_1_addr = 0x614,
.csid_tpg_dt_n_cfg_2_addr = 0x618,
.csid_tpg_color_bars_cfg_addr = 0x640,
.csid_tpg_color_box_cfg_addr = 0x644,
.csid_tpg_common_gen_cfg_addr = 0x648,
.csid_tpg_cgen_n_cfg_addr = 0x650,
.csid_tpg_cgen_n_x0_addr = 0x654,
.csid_tpg_cgen_n_x1_addr = 0x658,
.csid_tpg_cgen_n_x2_addr = 0x65c,
.csid_tpg_cgen_n_xy_addr = 0x660,
.csid_tpg_cgen_n_y1_addr = 0x664,
.csid_tpg_cgen_n_y2_addr = 0x668,
/* configurations */
.tpg_dtn_cfg_offset = 0xc,
.tpg_cgen_cfg_offset = 0x20,
.tpg_cpas_ife_reg_offset = 0x28,
};
static struct cam_ife_csid_common_reg_offset
cam_ife_csid_170_200_cmn_reg_offset = {
.csid_hw_version_addr = 0x0,
.csid_cfg0_addr = 0x4,
.csid_ctrl_addr = 0x8,
.csid_reset_addr = 0xc,
.csid_rst_strobes_addr = 0x10,
.csid_test_bus_ctrl_addr = 0x14,
.csid_top_irq_status_addr = 0x70,
.csid_top_irq_mask_addr = 0x74,
.csid_top_irq_clear_addr = 0x78,
.csid_top_irq_set_addr = 0x7c,
.csid_irq_cmd_addr = 0x80,
/*configurations */
.major_version = 1,
.minor_version = 7,
.version_incr = 0,
.num_rdis = 3,
.num_pix = 1,
.num_ppp = 1,
.csid_reg_rst_stb = 1,
.csid_rst_stb = 0x1e,
.csid_rst_stb_sw_all = 0x1f,
.path_rst_stb_all = 0x7f,
.path_rst_done_shift_val = 1,
.path_en_shift_val = 31,
.packing_fmt_shift_val = 30,
.dt_id_shift_val = 27,
.vc_shift_val = 22,
.dt_shift_val = 16,
.fmt_shift_val = 12,
.plain_fmt_shit_val = 10,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.crop_shift = 16,
.ipp_irq_mask_all = 0xFFFF,
.rdi_irq_mask_all = 0xFFFF,
.ppp_irq_mask_all = 0xFFFF,
.measure_en_hbi_vbi_cnt_mask = 0xC,
.format_measure_en_val = 1,
};
static struct cam_ife_csid_reg_offset cam_ife_csid_170_200_reg_offset = {
.cmn_reg = &cam_ife_csid_170_200_cmn_reg_offset,
.csi2_reg = &cam_ife_csid_170_200_csi2_reg_offset,
.ipp_reg = &cam_ife_csid_170_200_ipp_reg_offset,
.ppp_reg = &cam_ife_csid_170_200_ppp_reg_offset,
.rdi_reg = {
&cam_ife_csid_170_200_rdi_0_reg_offset,
&cam_ife_csid_170_200_rdi_1_reg_offset,
&cam_ife_csid_170_200_rdi_2_reg_offset,
NULL,
},
.tpg_reg = &cam_ife_csid_170_200_tpg_reg_offset,
};
#endif /*_CAM_IFE_CSID_170_200_H_ */

10
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid17x.c
View file

@ -7,6 +7,7 @@
#include <linux/module.h>
#include "cam_ife_csid_core.h"
#include "cam_ife_csid170.h"
#include "cam_ife_csid170_200.h"
#include "cam_ife_csid175.h"
#include "cam_ife_csid175_200.h"
#include "cam_ife_csid480.h"
@ -23,6 +24,11 @@ static struct cam_ife_csid_hw_info cam_ife_csid170_hw_info = {
.hw_dts_version = CAM_CSID_VERSION_V170,
};
static struct cam_ife_csid_hw_info cam_ife_csid170_200_hw_info = {
.csid_reg = &cam_ife_csid_170_200_reg_offset,
.hw_dts_version = CAM_CSID_VERSION_V170,
};
static struct cam_ife_csid_hw_info cam_ife_csid175_hw_info = {
.csid_reg = &cam_ife_csid_175_reg_offset,
.hw_dts_version = CAM_CSID_VERSION_V175,
@ -43,6 +49,10 @@ static const struct of_device_id cam_ife_csid17x_dt_match[] = {
.compatible = "qcom,csid170",
.data = &cam_ife_csid170_hw_info,
},
{
.compatible = "qcom,csid170_200",
.data = &cam_ife_csid170_200_hw_info,
},
{
.compatible = "qcom,csid175",
.data = &cam_ife_csid175_hw_info,

140
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
View file

@ -772,6 +772,7 @@ int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw,
case CAM_CPAS_TITAN_170_V100:
case CAM_CPAS_TITAN_170_V110:
case CAM_CPAS_TITAN_170_V120:
case CAM_CPAS_TITAN_170_V200:
if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_PHY_3 &&
csid_hw->hw_intf->hw_idx != 2) {
rc = -EINVAL;
@ -828,28 +829,31 @@ int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw,
goto end;
}
if (cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) {
if (csid_hw->csi2_rx_cfg.lane_cfg !=
cid_reserv->in_port->lane_cfg ||
csid_hw->csi2_rx_cfg.lane_type !=
cid_reserv->in_port->lane_type ||
csid_hw->csi2_rx_cfg.lane_num !=
cid_reserv->in_port->lane_num) {
rc = -EINVAL;
goto end;
}
} else {
if (csid_hw->tpg_cfg.in_format !=
cid_reserv->in_port->format ||
csid_hw->tpg_cfg.width !=
cid_reserv->in_port->left_width ||
csid_hw->tpg_cfg.height !=
cid_reserv->in_port->height ||
csid_hw->tpg_cfg.test_pattern !=
cid_reserv->in_port->test_pattern) {
rc = -EINVAL;
goto end;
}
if ((cid_reserv->in_port->res_type !=
CAM_ISP_IFE_IN_RES_TPG) &&
(csid_hw->csi2_rx_cfg.lane_cfg !=
cid_reserv->in_port->lane_cfg ||
csid_hw->csi2_rx_cfg.lane_type !=
cid_reserv->in_port->lane_type ||
csid_hw->csi2_rx_cfg.lane_num !=
cid_reserv->in_port->lane_num)) {
rc = -EINVAL;
goto end;
}
if ((cid_reserv->in_port->res_type ==
CAM_ISP_IFE_IN_RES_TPG) &&
(csid_hw->tpg_cfg.in_format !=
cid_reserv->in_port->format ||
csid_hw->tpg_cfg.width !=
cid_reserv->in_port->left_width ||
csid_hw->tpg_cfg.height !=
cid_reserv->in_port->height ||
csid_hw->tpg_cfg.test_pattern !=
cid_reserv->in_port->test_pattern)) {
rc = -EINVAL;
goto end;
}
}
@ -934,45 +938,45 @@ int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw,
csid_hw->csi2_rx_cfg.lane_num =
cid_reserv->in_port->lane_num;
if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_TPG) {
csid_hw->csi2_rx_cfg.phy_sel = 0;
if (cid_reserv->in_port->format >
CAM_FORMAT_MIPI_RAW_16) {
CAM_ERR(CAM_ISP, " Wrong TPG format");
rc = -EINVAL;
goto end;
}
csid_hw->tpg_cfg.in_format =
cid_reserv->in_port->format;
csid_hw->tpg_cfg.usage_type =
cid_reserv->in_port->usage_type;
if (cid_reserv->in_port->usage_type)
csid_hw->tpg_cfg.width =
(cid_reserv->in_port->right_stop + 1);
else
csid_hw->tpg_cfg.width =
cid_reserv->in_port->left_width;
csid_hw->tpg_cfg.height = cid_reserv->in_port->height;
csid_hw->tpg_cfg.test_pattern =
cid_reserv->in_port->test_pattern;
CAM_DBG(CAM_ISP, "CSID:%d TPG width:%d height:%d",
csid_hw->hw_intf->hw_idx,
csid_hw->tpg_cfg.width,
csid_hw->tpg_cfg.height);
cid_data->tpg_set = 1;
} else if (cid_reserv->in_port->res_type ==
CAM_ISP_IFE_IN_RES_CPHY_TPG_0) {
csid_hw->csi2_rx_cfg.phy_sel = 0;
} else if (cid_reserv->in_port->res_type ==
CAM_ISP_IFE_IN_RES_CPHY_TPG_1) {
csid_hw->csi2_rx_cfg.phy_sel = 1;
} else {
if (cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) {
csid_hw->csi2_rx_cfg.phy_sel =
(cid_reserv->in_port->res_type & 0xFF) - 1;
csid_hw->csi2_reserve_cnt++;
CAM_DBG(CAM_ISP, "CSID:%d CID:%d acquired",
csid_hw->hw_intf->hw_idx,
cid_reserv->node_res->res_id);
goto end;
}
/* Below code is executed only for TPG in_res type */
csid_hw->csi2_rx_cfg.phy_sel = 0;
if (cid_reserv->in_port->format >
CAM_FORMAT_MIPI_RAW_16) {
CAM_ERR(CAM_ISP, " Wrong TPG format");
rc = -EINVAL;
goto end;
}
csid_hw->tpg_cfg.in_format =
cid_reserv->in_port->format;
csid_hw->tpg_cfg.usage_type =
cid_reserv->in_port->usage_type;
if (cid_reserv->in_port->usage_type)
csid_hw->tpg_cfg.width =
(cid_reserv->in_port->right_stop + 1);
else
csid_hw->tpg_cfg.width =
cid_reserv->in_port->left_width;
csid_hw->tpg_cfg.height = cid_reserv->in_port->height;
csid_hw->tpg_cfg.test_pattern =
cid_reserv->in_port->test_pattern;
CAM_DBG(CAM_ISP, "CSID:%d TPG width:%d height:%d",
csid_hw->hw_intf->hw_idx,
csid_hw->tpg_cfg.width,
csid_hw->tpg_cfg.height);
cid_data->tpg_set = 1;
}
csid_hw->csi2_reserve_cnt++;
@ -2023,16 +2027,24 @@ static int cam_ife_csid_enable_pxl_path(
CAM_DBG(CAM_ISP, "Enable %s path", (is_ipp) ? "IPP" : "PPP");
/* Set master or slave path */
if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER)
if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER) {
/*Set halt mode as master */
val = CSID_HALT_MODE_MASTER << 2;
else if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE)
if (pxl_reg->halt_master_sel_en)
val = pxl_reg->halt_sel_internal_master_val << 4 |
CSID_HALT_MODE_MASTER << 2;
else
val = CSID_HALT_MODE_MASTER << 2;
} else if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) {
/*Set halt mode as slave and set master idx */
val = path_data->master_idx << 4 | CSID_HALT_MODE_SLAVE << 2;
else
if (pxl_reg->halt_master_sel_en)
val = CSID_HALT_MODE_SLAVE << 2;
else
val = path_data->master_idx << 4 |
CSID_HALT_MODE_SLAVE << 2;
} else {
/* Default is internal halt mode */
val = 0;
}
/*
* Resume at frame boundary if Master or No Sync.
* Slave will get resume command from Master.

4
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_IFE_CSID_HW_H_
@ -139,6 +139,8 @@ struct cam_ife_csid_pxl_reg_offset {
uint32_t quad_cfa_bin_en_shift_val;
uint32_t ccif_violation_en;
uint32_t overflow_ctrl_en;
uint32_t halt_master_sel_en;
uint32_t halt_sel_internal_master_val;
};
struct cam_ife_csid_rdi_reg_offset {

5
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c
View file

@ -5,6 +5,7 @@
#include <linux/module.h>
#include "cam_vfe170.h"
#include "cam_vfe170_150.h"
#include "cam_vfe175.h"
#include "cam_vfe175_130.h"
#include "cam_vfe480.h"
@ -21,6 +22,10 @@ static const struct of_device_id cam_vfe_dt_match[] = {
.compatible = "qcom,vfe170",
.data = &cam_vfe170_hw_info,
},
{
.compatible = "qcom,vfe170_150",
.data = &cam_vfe170_150_hw_info,
},
{
.compatible = "qcom,vfe175",
.data = &cam_vfe175_hw_info,

850
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe170_150.h Normal file
View file

@ -0,0 +1,850 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_VFE170_150_H_
#define _CAM_VFE170_150_H_
#include "cam_vfe_camif_ver2.h"
#include "cam_vfe_bus_ver2.h"
#include "cam_irq_controller.h"
#include "cam_vfe_top_ver2.h"
#include "cam_vfe_core.h"
static struct cam_irq_register_set vfe170_150_top_irq_reg_set[2] = {
{
.mask_reg_offset = 0x0000005C,
.clear_reg_offset = 0x00000064,
.status_reg_offset = 0x0000006C,
},
{
.mask_reg_offset = 0x00000060,
.clear_reg_offset = 0x00000068,
.status_reg_offset = 0x00000070,
},
};
static struct cam_irq_controller_reg_info vfe170_150_top_irq_reg_info = {
.num_registers = 2,
.irq_reg_set = vfe170_150_top_irq_reg_set,
.global_clear_offset = 0x00000058,
.global_clear_bitmask = 0x00000001,
};
static struct cam_vfe_camif_ver2_reg vfe170_150_camif_reg = {
.dual_vfe_sync = 0x00000100,
.camif_cmd = 0x00000478,
.camif_config = 0x0000047C,
.line_skip_pattern = 0x00000488,
.pixel_skip_pattern = 0x0000048C,
.skip_period = 0x00000490,
.irq_subsample_pattern = 0x0000049C,
.epoch_irq = 0x000004A0,
.raw_crop_width_cfg = 0x00000CE4,
.raw_crop_height_cfg = 0x00000CE8,
.reg_update_cmd = 0x000004AC,
.vfe_diag_config = 0x00000C48,
.vfe_diag_sensor_status = 0x00000C4C,
};
static struct cam_vfe_camif_reg_data vfe_170_150_camif_reg_data = {
.raw_crop_first_pixel_shift = 16,
.raw_crop_first_pixel_mask = 0xFFFF,
.raw_crop_last_pixel_shift = 0x0,
.raw_crop_last_pixel_mask = 0x3FFF,
.raw_crop_first_line_shift = 16,
.raw_crop_first_line_mask = 0xFFFF,
.raw_crop_last_line_shift = 0,
.raw_crop_last_line_mask = 0x3FFF,
.input_mux_sel_shift = 5,
.input_mux_sel_mask = 0x3,
.extern_reg_update_shift = 4,
.extern_reg_update_mask = 1,
.pixel_pattern_shift = 0,
.pixel_pattern_mask = 0x7,
.dsp_mode_shift = 23,
.dsp_mode_mask = 0x1,
.dsp_en_shift = 3,
.dsp_en_mask = 0x1,
.reg_update_cmd_data = 0x1,
.epoch_line_cfg = 0x00140014,
.sof_irq_mask = 0x00000001,
.epoch0_irq_mask = 0x00000004,
.reg_update_irq_mask = 0x00000010,
.eof_irq_mask = 0x00000002,
.error_irq_mask0 = 0x0003FC00,
.error_irq_mask1 = 0x0FFF7E80,
.enable_diagnostic_hw = 0x1,
.dual_vfe_sync_mask = 0x3,
};
struct cam_vfe_top_ver2_reg_offset_module_ctrl lens_170_150_reg = {
.reset = 0x0000001C,
.cgc_ovd = 0x0000002C,
.enable = 0x00000040,
};
struct cam_vfe_top_ver2_reg_offset_module_ctrl stats_170_150_reg = {
.reset = 0x00000020,
.cgc_ovd = 0x00000030,
.enable = 0x00000044,
};
struct cam_vfe_top_ver2_reg_offset_module_ctrl color_170_150_reg = {
.reset = 0x00000024,
.cgc_ovd = 0x00000034,
.enable = 0x00000048,
};
struct cam_vfe_top_ver2_reg_offset_module_ctrl zoom_170_150_reg = {
.reset = 0x00000028,
.cgc_ovd = 0x00000038,
.enable = 0x0000004C,
};
static struct cam_vfe_top_ver2_reg_offset_common vfe170_150_top_common_reg = {
.hw_version = 0x00000000,
.hw_capability = 0x00000004,
.lens_feature = 0x00000008,
.stats_feature = 0x0000000C,
.color_feature = 0x00000010,
.zoom_feature = 0x00000014,
.global_reset_cmd = 0x00000018,
.module_ctrl = {
&lens_170_150_reg,
&stats_170_150_reg,
&color_170_150_reg,
&zoom_170_150_reg,
},
.bus_cgc_ovd = 0x0000003C,
.core_cfg = 0x00000050,
.three_D_cfg = 0x00000054,
.violation_status = 0x0000007C,
.reg_update_cmd = 0x000004AC,
};
static struct cam_vfe_rdi_ver2_reg vfe170_150_rdi_reg = {
.reg_update_cmd = 0x000004AC,
};
static struct cam_vfe_rdi_reg_data vfe_170_150_rdi_0_data = {
.reg_update_cmd_data = 0x2,
.sof_irq_mask = 0x8000000,
.reg_update_irq_mask = 0x20,
};
static struct cam_vfe_rdi_reg_data vfe_170_150_rdi_1_data = {
.reg_update_cmd_data = 0x4,
.sof_irq_mask = 0x10000000,
.reg_update_irq_mask = 0x40,
};
static struct cam_vfe_rdi_reg_data vfe_170_150_rdi_2_data = {
.reg_update_cmd_data = 0x8,
.sof_irq_mask = 0x20000000,
.reg_update_irq_mask = 0x80,
};
static struct cam_vfe_top_ver2_hw_info vfe170_150_top_hw_info = {
.common_reg = &vfe170_150_top_common_reg,
.camif_hw_info = {
.common_reg = &vfe170_150_top_common_reg,
.camif_reg = &vfe170_150_camif_reg,
.reg_data = &vfe_170_150_camif_reg_data,
},
.camif_lite_hw_info = {
.common_reg = NULL,
.camif_lite_reg = NULL,
.reg_data = NULL,
},
.rdi_hw_info = {
.common_reg = &vfe170_150_top_common_reg,
.rdi_reg = &vfe170_150_rdi_reg,
.reg_data = {
&vfe_170_150_rdi_0_data,
&vfe_170_150_rdi_1_data,
&vfe_170_150_rdi_2_data,
NULL,
},
},
.num_mux = 4,
.mux_type = {
CAM_VFE_CAMIF_VER_2_0,
CAM_VFE_RDI_VER_1_0,
CAM_VFE_RDI_VER_1_0,
CAM_VFE_RDI_VER_1_0,
},
};
static struct cam_irq_register_set vfe170_150_bus_irq_reg[3] = {
{
.mask_reg_offset = 0x00002044,
.clear_reg_offset = 0x00002050,
.status_reg_offset = 0x0000205C,
},
{
.mask_reg_offset = 0x00002048,
.clear_reg_offset = 0x00002054,
.status_reg_offset = 0x00002060,
},
{
.mask_reg_offset = 0x0000204C,
.clear_reg_offset = 0x00002058,
.status_reg_offset = 0x00002064,
},
};
static struct cam_vfe_bus_ver2_reg_offset_ubwc_client
vfe_170_150_ubwc_regs_client_3 = {
.tile_cfg = 0x0000252C,
.h_init = 0x00002530,
.v_init = 0x00002534,
.meta_addr = 0x00002538,
.meta_offset = 0x0000253C,
.meta_stride = 0x00002540,
.mode_cfg_0 = 0x00002544,
.bw_limit = 0x000025A0,
};
static struct cam_vfe_bus_ver2_reg_offset_ubwc_client
vfe_170_150_ubwc_regs_client_4 = {
.tile_cfg = 0x0000262C,
.h_init = 0x00002630,
.v_init = 0x00002634,
.meta_addr = 0x00002638,
.meta_offset = 0x0000263C,
.meta_stride = 0x00002640,
.mode_cfg_0 = 0x00002644,
.bw_limit = 0x000026A0,
};
static struct cam_vfe_bus_ver2_hw_info vfe170_150_bus_hw_info = {
.common_reg = {
.hw_version = 0x00002000,
.hw_capability = 0x00002004,
.sw_reset = 0x00002008,
.cgc_ovd = 0x0000200C,
.pwr_iso_cfg = 0x000020CC,
.dual_master_comp_cfg = 0x00002028,
.irq_reg_info = {
.num_registers = 3,
.irq_reg_set = vfe170_150_bus_irq_reg,
.global_clear_offset = 0x00002068,
.global_clear_bitmask = 0x00000001,
},
.comp_error_status = 0x0000206C,
.comp_ovrwr_status = 0x00002070,
.dual_comp_error_status = 0x00002074,
.dual_comp_ovrwr_status = 0x00002078,
.addr_sync_cfg = 0x0000207C,
.addr_sync_frame_hdr = 0x00002080,
.addr_sync_no_sync = 0x00002084,
.debug_status_cfg = 0x0000226C,
.debug_status_0 = 0x00002270,
},
.num_client = 20,
.bus_client_reg = {
/* BUS Client 0 */
{
.status0 = 0x00002200,
.status1 = 0x00002204,
.cfg = 0x00002208,
.header_addr = 0x0000220C,
.header_cfg = 0x00002210,
.image_addr = 0x00002214,
.image_addr_offset = 0x00002218,
.buffer_width_cfg = 0x0000221C,
.buffer_height_cfg = 0x00002220,
.packer_cfg = 0x00002224,
.stride = 0x00002228,
.irq_subsample_period = 0x00002248,
.irq_subsample_pattern = 0x0000224C,
.framedrop_period = 0x00002250,
.framedrop_pattern = 0x00002254,
.frame_inc = 0x00002258,
.burst_limit = 0x0000225C,
.ubwc_regs = NULL,
},
/* BUS Client 1 */
{
.status0 = 0x00002300,
.status1 = 0x00002304,
.cfg = 0x00002308,
.header_addr = 0x0000230C,
.header_cfg = 0x00002310,
.image_addr = 0x00002314,
.image_addr_offset = 0x00002318,
.buffer_width_cfg = 0x0000231C,
.buffer_height_cfg = 0x00002320,
.packer_cfg = 0x00002324,
.stride = 0x00002328,
.irq_subsample_period = 0x00002348,
.irq_subsample_pattern = 0x0000234C,
.framedrop_period = 0x00002350,
.framedrop_pattern = 0x00002354,
.frame_inc = 0x00002358,
.burst_limit = 0x0000235C,
.ubwc_regs = NULL,
},
/* BUS Client 2 */
{
.status0 = 0x00002400,
.status1 = 0x00002404,
.cfg = 0x00002408,
.header_addr = 0x0000240C,
.header_cfg = 0x00002410,
.image_addr = 0x00002414,
.image_addr_offset = 0x00002418,
.buffer_width_cfg = 0x0000241C,
.buffer_height_cfg = 0x00002420,
.packer_cfg = 0x00002424,
.stride = 0x00002428,
.irq_subsample_period = 0x00002448,
.irq_subsample_pattern = 0x0000244C,
.framedrop_period = 0x00002450,
.framedrop_pattern = 0x00002454,
.frame_inc = 0x00002458,
.burst_limit = 0x0000245C,
.ubwc_regs = NULL,
},
/* BUS Client 3 */
{
.status0 = 0x00002500,
.status1 = 0x00002504,
.cfg = 0x00002508,
.header_addr = 0x0000250C,
.header_cfg = 0x00002510,
.image_addr = 0x00002514,
.image_addr_offset = 0x00002518,
.buffer_width_cfg = 0x0000251C,
.buffer_height_cfg = 0x00002520,
.packer_cfg = 0x00002524,
.stride = 0x00002528,
.irq_subsample_period = 0x00002548,
.irq_subsample_pattern = 0x0000254C,
.framedrop_period = 0x00002550,
.framedrop_pattern = 0x00002554,
.frame_inc = 0x00002558,
.burst_limit = 0x0000255C,
.ubwc_regs =
&vfe_170_150_ubwc_regs_client_3,
},
/* BUS Client 4 */
{
.status0 = 0x00002600,
.status1 = 0x00002604,
.cfg = 0x00002608,
.header_addr = 0x0000260C,
.header_cfg = 0x00002610,
.image_addr = 0x00002614,
.image_addr_offset = 0x00002618,
.buffer_width_cfg = 0x0000261C,
.buffer_height_cfg = 0x00002620,
.packer_cfg = 0x00002624,
.stride = 0x00002628,
.irq_subsample_period = 0x00002648,
.irq_subsample_pattern = 0x0000264C,
.framedrop_period = 0x00002650,
.framedrop_pattern = 0x00002654,
.frame_inc = 0x00002658,
.burst_limit = 0x0000265C,
.ubwc_regs =
&vfe_170_150_ubwc_regs_client_4,
},
/* BUS Client 5 */
{
.status0 = 0x00002700,
.status1 = 0x00002704,
.cfg = 0x00002708,
.header_addr = 0x0000270C,
.header_cfg = 0x00002710,
.image_addr = 0x00002714,
.image_addr_offset = 0x00002718,
.buffer_width_cfg = 0x0000271C,
.buffer_height_cfg = 0x00002720,
.packer_cfg = 0x00002724,
.stride = 0x00002728,
.irq_subsample_period = 0x00002748,
.irq_subsample_pattern = 0x0000274C,
.framedrop_period = 0x00002750,
.framedrop_pattern = 0x00002754,
.frame_inc = 0x00002758,
.burst_limit = 0x0000275C,
.ubwc_regs = NULL,
},
/* BUS Client 6 */
{
.status0 = 0x00002800,
.status1 = 0x00002804,
.cfg = 0x00002808,
.header_addr = 0x0000280C,
.header_cfg = 0x00002810,
.image_addr = 0x00002814,
.image_addr_offset = 0x00002818,
.buffer_width_cfg = 0x0000281C,
.buffer_height_cfg = 0x00002820,
.packer_cfg = 0x00002824,
.stride = 0x00002828,
.irq_subsample_period = 0x00002848,
.irq_subsample_pattern = 0x0000284C,
.framedrop_period = 0x00002850,
.framedrop_pattern = 0x00002854,
.frame_inc = 0x00002858,
.burst_limit = 0x0000285C,
.ubwc_regs = NULL,
},
/* BUS Client 7 */
{
.status0 = 0x00002900,
.status1 = 0x00002904,
.cfg = 0x00002908,
.header_addr = 0x0000290C,
.header_cfg = 0x00002910,
.image_addr = 0x00002914,
.image_addr_offset = 0x00002918,
.buffer_width_cfg = 0x0000291C,
.buffer_height_cfg = 0x00002920,
.packer_cfg = 0x00002924,
.stride = 0x00002928,
.irq_subsample_period = 0x00002948,
.irq_subsample_pattern = 0x0000294C,
.framedrop_period = 0x00002950,
.framedrop_pattern = 0x00002954,
.frame_inc = 0x00002958,
.burst_limit = 0x0000295C,
.ubwc_regs = NULL,
},
/* BUS Client 8 */
{
.status0 = 0x00002A00,
.status1 = 0x00002A04,
.cfg = 0x00002A08,
.header_addr = 0x00002A0C,
.header_cfg = 0x00002A10,
.image_addr = 0x00002A14,
.image_addr_offset = 0x00002A18,
.buffer_width_cfg = 0x00002A1C,
.buffer_height_cfg = 0x00002A20,
.packer_cfg = 0x00002A24,
.stride = 0x00002A28,
.irq_subsample_period = 0x00002A48,
.irq_subsample_pattern = 0x00002A4C,
.framedrop_period = 0x00002A50,
.framedrop_pattern = 0x00002A54,
.frame_inc = 0x00002A58,
.burst_limit = 0x00002A5C,
.ubwc_regs = NULL,
},
/* BUS Client 9 */
{
.status0 = 0x00002B00,
.status1 = 0x00002B04,
.cfg = 0x00002B08,
.header_addr = 0x00002B0C,
.header_cfg = 0x00002B10,
.image_addr = 0x00002B14,
.image_addr_offset = 0x00002B18,
.buffer_width_cfg = 0x00002B1C,
.buffer_height_cfg = 0x00002B20,
.packer_cfg = 0x00002B24,
.stride = 0x00002B28,
.irq_subsample_period = 0x00002B48,
.irq_subsample_pattern = 0x00002B4C,
.framedrop_period = 0x00002B50,
.framedrop_pattern = 0x00002B54,
.frame_inc = 0x00002B58,
.burst_limit = 0x00002B5C,
.ubwc_regs = NULL,
},
/* BUS Client 10 */
{
.status0 = 0x00002C00,
.status1 = 0x00002C04,
.cfg = 0x00002C08,
.header_addr = 0x00002C0C,
.header_cfg = 0x00002C10,
.image_addr = 0x00002C14,
.image_addr_offset = 0x00002C18,
.buffer_width_cfg = 0x00002C1C,
.buffer_height_cfg = 0x00002C20,
.packer_cfg = 0x00002C24,
.stride = 0x00002C28,
.irq_subsample_period = 0x00002C48,
.irq_subsample_pattern = 0x00002C4C,
.framedrop_period = 0x00002C50,
.framedrop_pattern = 0x00002C54,
.frame_inc = 0x00002C58,
.burst_limit = 0x00002C5C,
.ubwc_regs = NULL,
},
/* BUS Client 11 */
{
.status0 = 0x00002D00,
.status1 = 0x00002D04,
.cfg = 0x00002D08,
.header_addr = 0x00002D0C,
.header_cfg = 0x00002D10,
.image_addr = 0x00002D14,
.image_addr_offset = 0x00002D18,
.buffer_width_cfg = 0x00002D1C,
.buffer_height_cfg = 0x00002D20,
.packer_cfg = 0x00002D24,
.stride = 0x00002D28,
.irq_subsample_period = 0x00002D48,
.irq_subsample_pattern = 0x00002D4C,
.framedrop_period = 0x00002D50,
.framedrop_pattern = 0x00002D54,
.frame_inc = 0x00002D58,
.burst_limit = 0x00002D5C,
.ubwc_regs = NULL,
},
/* BUS Client 12 */
{
.status0 = 0x00002E00,
.status1 = 0x00002E04,
.cfg = 0x00002E08,
.header_addr = 0x00002E0C,
.header_cfg = 0x00002E10,
.image_addr = 0x00002E14,
.image_addr_offset = 0x00002E18,
.buffer_width_cfg = 0x00002E1C,
.buffer_height_cfg = 0x00002E20,
.packer_cfg = 0x00002E24,
.stride = 0x00002E28,
.irq_subsample_period = 0x00002E48,
.irq_subsample_pattern = 0x00002E4C,
.framedrop_period = 0x00002E50,
.framedrop_pattern = 0x00002E54,
.frame_inc = 0x00002E58,
.burst_limit = 0x00002E5C,
.ubwc_regs = NULL,
},
/* BUS Client 13 */
{
.status0 = 0x00002F00,
.status1 = 0x00002F04,
.cfg = 0x00002F08,
.header_addr = 0x00002F0C,
.header_cfg = 0x00002F10,
.image_addr = 0x00002F14,
.image_addr_offset = 0x00002F18,
.buffer_width_cfg = 0x00002F1C,
.buffer_height_cfg = 0x00002F20,
.packer_cfg = 0x00002F24,
.stride = 0x00002F28,
.irq_subsample_period = 0x00002F48,
.irq_subsample_pattern = 0x00002F4C,
.framedrop_period = 0x00002F50,
.framedrop_pattern = 0x00002F54,
.frame_inc = 0x00002F58,
.burst_limit = 0x00002F5C,
.ubwc_regs = NULL,
},
/* BUS Client 14 */
{
.status0 = 0x00003000,
.status1 = 0x00003004,
.cfg = 0x00003008,
.header_addr = 0x0000300C,
.header_cfg = 0x00003010,
.image_addr = 0x00003014,
.image_addr_offset = 0x00003018,
.buffer_width_cfg = 0x0000301C,
.buffer_height_cfg = 0x00003020,
.packer_cfg = 0x00003024,
.stride = 0x00003028,
.irq_subsample_period = 0x00003048,
.irq_subsample_pattern = 0x0000304C,
.framedrop_period = 0x00003050,
.framedrop_pattern = 0x00003054,
.frame_inc = 0x00003058,
.burst_limit = 0x0000305C,
.ubwc_regs = NULL,
},
/* BUS Client 15 */
{
.status0 = 0x00003100,
.status1 = 0x00003104,
.cfg = 0x00003108,
.header_addr = 0x0000310C,
.header_cfg = 0x00003110,
.image_addr = 0x00003114,
.image_addr_offset = 0x00003118,
.buffer_width_cfg = 0x0000311C,
.buffer_height_cfg = 0x00003120,
.packer_cfg = 0x00003124,
.stride = 0x00003128,
.irq_subsample_period = 0x00003148,
.irq_subsample_pattern = 0x0000314C,
.framedrop_period = 0x00003150,
.framedrop_pattern = 0x00003154,
.frame_inc = 0x00003158,
.burst_limit = 0x0000315C,
.ubwc_regs = NULL,
},
/* BUS Client 16 */
{
.status0 = 0x00003200,
.status1 = 0x00003204,
.cfg = 0x00003208,
.header_addr = 0x0000320C,
.header_cfg = 0x00003210,
.image_addr = 0x00003214,
.image_addr_offset = 0x00003218,
.buffer_width_cfg = 0x0000321C,
.buffer_height_cfg = 0x00003220,
.packer_cfg = 0x00003224,
.stride = 0x00003228,
.irq_subsample_period = 0x00003248,
.irq_subsample_pattern = 0x0000324C,
.framedrop_period = 0x00003250,
.framedrop_pattern = 0x00003254,
.frame_inc = 0x00003258,
.burst_limit = 0x0000325C,
.ubwc_regs = NULL,
},
/* BUS Client 17 */
{
.status0 = 0x00003300,
.status1 = 0x00003304,
.cfg = 0x00003308,
.header_addr = 0x0000330C,
.header_cfg = 0x00003310,
.image_addr = 0x00003314,
.image_addr_offset = 0x00003318,
.buffer_width_cfg = 0x0000331C,
.buffer_height_cfg = 0x00003320,
.packer_cfg = 0x00003324,
.stride = 0x00003328,
.irq_subsample_period = 0x00003348,
.irq_subsample_pattern = 0x0000334C,
.framedrop_period = 0x00003350,
.framedrop_pattern = 0x00003354,
.frame_inc = 0x00003358,
.burst_limit = 0x0000335C,
.ubwc_regs = NULL,
},
/* BUS Client 18 */
{
.status0 = 0x00003400,
.status1 = 0x00003404,
.cfg = 0x00003408,
.header_addr = 0x0000340C,
.header_cfg = 0x00003410,
.image_addr = 0x00003414,
.image_addr_offset = 0x00003418,
.buffer_width_cfg = 0x0000341C,
.buffer_height_cfg = 0x00003420,
.packer_cfg = 0x00003424,
.stride = 0x00003428,
.irq_subsample_period = 0x00003448,
.irq_subsample_pattern = 0x0000344C,
.framedrop_period = 0x00003450,
.framedrop_pattern = 0x00003454,
.frame_inc = 0x00003458,
.burst_limit = 0x0000345C,
.ubwc_regs = NULL,
},
/* BUS Client 19 */
{
.status0 = 0x00003500,
.status1 = 0x00003504,
.cfg = 0x00003508,
.header_addr = 0x0000350C,
.header_cfg = 0x00003510,
.image_addr = 0x00003514,
.image_addr_offset = 0x00003518,
.buffer_width_cfg = 0x0000351C,
.buffer_height_cfg = 0x00003520,
.packer_cfg = 0x00003524,
.stride = 0x00003528,
.irq_subsample_period = 0x00003548,
.irq_subsample_pattern = 0x0000354C,
.framedrop_period = 0x00003550,
.framedrop_pattern = 0x00003554,
.frame_inc = 0x00003558,
.burst_limit = 0x0000355C,
.ubwc_regs = NULL,
},
},
.comp_grp_reg = {
/* CAM_VFE_BUS_VER2_COMP_GRP_0 */
{
.comp_mask = 0x00002010,
},
/* CAM_VFE_BUS_VER2_COMP_GRP_1 */
{
.comp_mask = 0x00002014,
},
/* CAM_VFE_BUS_VER2_COMP_GRP_2 */
{
.comp_mask = 0x00002018,
},
/* CAM_VFE_BUS_VER2_COMP_GRP_3 */
{
.comp_mask = 0x0000201C,
},
/* CAM_VFE_BUS_VER2_COMP_GRP_4 */
{
.comp_mask = 0x00002020,
},
/* CAM_VFE_BUS_VER2_COMP_GRP_5 */
{
.comp_mask = 0x00002024,
},
/* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0 */
{
.comp_mask = 0x0000202C,
.addr_sync_mask = 0x00002088,
},
/* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_1 */
{
.comp_mask = 0x00002030,
.addr_sync_mask = 0x0000208C,
},
/* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_2 */
{
.comp_mask = 0x00002034,
.addr_sync_mask = 0x00002090,
},
/* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_3 */
{
.comp_mask = 0x00002038,
.addr_sync_mask = 0x00002094,
},
/* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_4 */
{
.comp_mask = 0x0000203C,
.addr_sync_mask = 0x00002098,
},
/* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5 */
{
.comp_mask = 0x00002040,
.addr_sync_mask = 0x0000209C,
},
},
.num_out = 18,
.vfe_out_hw_info = {
{
.vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI0,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI1,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI2,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FULL,
.max_width = 4096,
.max_height = 4096,
},
{
.vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS4,
.max_width = 1920,
.max_height = 1080,
},
{
.vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS16,
.max_width = 1920,
.max_height = 1080,
},
{
.vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FD,
.max_width = 1920,
.max_height = 1080,
},
{
.vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_PDAF,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type =
CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type =
CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST,
.max_width = 1920,
.max_height = 1080,
},
{
.vfe_out_type =
CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type =
CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type =
CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type =
CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type =
CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type =
CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS,
.max_width = -1,
.max_height = -1,
},
{
.vfe_out_type =
CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST,
.max_width = -1,
.max_height = -1,
},
},
};
struct cam_vfe_hw_info cam_vfe170_150_hw_info = {
.irq_reg_info = &vfe170_150_top_irq_reg_info,
.bus_version = CAM_VFE_BUS_VER_2_0,
.bus_hw_info = &vfe170_150_bus_hw_info,
.top_version = CAM_VFE_TOP_VER_2_0,
.top_hw_info = &vfe170_150_top_hw_info,
.camif_version = CAM_VFE_CAMIF_VER_2_0,
.camif_reg = &vfe170_150_camif_reg,
.camif_lite_version = 0,
.camif_lite_reg = NULL,
};
#endif /* _CAM_vfe170_150_H_ */

2
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c
View file

@ -2594,6 +2594,7 @@ static void cam_vfe_bus_update_ubwc_meta_addr(
case CAM_CPAS_TITAN_170_V100:
case CAM_CPAS_TITAN_170_V110:
case CAM_CPAS_TITAN_170_V120:
case CAM_CPAS_TITAN_170_V200:
ubwc_regs =
(struct cam_vfe_bus_ver2_reg_offset_ubwc_client *)regs;
CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j,
@ -2811,6 +2812,7 @@ static int cam_vfe_bus_update_ubwc_regs(
case CAM_CPAS_TITAN_170_V100:
case CAM_CPAS_TITAN_170_V110:
case CAM_CPAS_TITAN_170_V120:
case CAM_CPAS_TITAN_170_V200:
rc = cam_vfe_bus_update_ubwc_legacy_regs(
wm_data, camera_hw_version, reg_val_pair, i, j);
break;

13
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c
View file

@ -48,6 +48,7 @@ struct cam_vfe_mux_camif_data {
bool enable_sof_irq_debug;
uint32_t irq_debug_cnt;
uint32_t camif_debug;
uint32_t dual_hw_idx;
uint32_t is_dual;
};
@ -259,6 +260,10 @@ int cam_vfe_camif_ver2_acquire_resource(
camif_data->priv = acquire_data->priv;
camif_data->is_dual = acquire_data->vfe_in.is_dual;
if (acquire_data->vfe_in.is_dual)
camif_data->dual_hw_idx =
acquire_data->vfe_in.dual_hw_idx;
CAM_DBG(CAM_ISP, "hw id:%d pix_pattern:%d dsp_mode=%d",
camif_res->hw_intf->hw_idx,
camif_data->pix_pattern, camif_data->dsp_mode);
@ -330,6 +335,7 @@ static int cam_vfe_camif_resource_start(
int rc = 0;
uint32_t err_irq_mask[CAM_IFE_IRQ_REGISTERS_MAX];
uint32_t irq_mask[CAM_IFE_IRQ_REGISTERS_MAX];
uint32_t dual_vfe_sync_val;
struct cam_vfe_soc_private *soc_private;
if (!camif_res) {
@ -390,6 +396,7 @@ static int cam_vfe_camif_resource_start(
case CAM_CPAS_TITAN_170_V100:
case CAM_CPAS_TITAN_170_V110:
case CAM_CPAS_TITAN_170_V120:
case CAM_CPAS_TITAN_170_V200:
cam_io_w_mb(rsrc_data->reg_data->epoch_line_cfg,
rsrc_data->mem_base +
rsrc_data->camif_reg->epoch_irq);
@ -414,6 +421,12 @@ static int cam_vfe_camif_resource_start(
break;
}
if (rsrc_data->is_dual && rsrc_data->reg_data->dual_vfe_sync_mask) {
dual_vfe_sync_val = (rsrc_data->dual_hw_idx &
rsrc_data->reg_data->dual_vfe_sync_mask) + 1;
cam_io_w_mb(dual_vfe_sync_val, rsrc_data->mem_base +
rsrc_data->camif_reg->dual_vfe_sync);
}
camif_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
/* Reg Update */

4
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_VFE_CAMIF_VER2_H_
@ -22,6 +22,7 @@ struct cam_vfe_camif_ver2_reg {
uint32_t reg_update_cmd;
uint32_t vfe_diag_config;
uint32_t vfe_diag_sensor_status;
uint32_t dual_vfe_sync;
};
struct cam_vfe_camif_reg_data {
@ -62,6 +63,7 @@ struct cam_vfe_camif_reg_data {
uint32_t subscribe_irq_mask1;
uint32_t enable_diagnostic_hw;
uint32_t dual_vfe_sync_mask;
};
struct cam_vfe_camif_ver2_hw_info {