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ARM: arm-soc: late cleanups

Browse source 
These are cleanups and smaller changes that either depend on earlier
 feature branches or came in late during the development cycle.
 We normally try to get all cleanups early, so these are the exceptions:
 
 - A follow-up on the clocksource reworks, hopefully the last time
   we need to merge clocksource subsystem changes through arm-soc.
   A first set of patches was part of the original 3.10 arm-soc cleanup
   series because of interdependencies with timer drivers now moved out
   of arch/arm.
 
 - Migrating the SPEAr13xx platform away from using auxdata for DMA
   channel descriptions towards using information in device tree,
   based on the earlier SPEAr multiplatform series
 
 - A few follow-ups on the Atmel SAMA5 support and other changes
   for Atmel at91 based on the larger at91 reworks.
 
 - Moving the armada irqchip implementation to drivers/irqchip
 
 - Several OMAP cleanups following up on the larger series already
   merged in 3.10.
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Merge tag 'cleanup-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late cleanups from Arnd Bergmann:
 "These are cleanups and smaller changes that either depend on earlier
  feature branches or came in late during the development cycle.  We
  normally try to get all cleanups early, so these are the exceptions:

   - A follow-up on the clocksource reworks, hopefully the last time we
     need to merge clocksource subsystem changes through arm-soc.

     A first set of patches was part of the original 3.10 arm-soc
     cleanup series because of interdependencies with timer drivers now
     moved out of arch/arm.

   - Migrating the SPEAr13xx platform away from using auxdata for DMA
     channel descriptions towards using information in device tree,
     based on the earlier SPEAr multiplatform series

   - A few follow-ups on the Atmel SAMA5 support and other changes for
     Atmel at91 based on the larger at91 reworks.

   - Moving the armada irqchip implementation to drivers/irqchip

   - Several OMAP cleanups following up on the larger series already
     merged in 3.10."

* tag 'cleanup-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits)
  ARM: OMAP4: change the device names in usb_bind_phy
  ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a
  ARM: SPEAr: conditionalize SMP code
  ARM: arch_timer: Silence debug preempt warnings
  ARM: OMAP: remove unused variable
  serial: amba-pl011: fix !CONFIG_DMA_ENGINE case
  ata: arasan: remove the need for platform_data
  ARM: at91/sama5d34ek.dts: remove not needed compatibility string
  ARM: at91: dts: add MCI DMA support
  ARM: at91: dts: add i2c dma support
  ARM: at91: dts: set #dma-cells to the correct value
  ARM: at91: suspend both memory controllers on at91sam9263
  irqchip: armada-370-xp: slightly cleanup irq controller driver
  irqchip: armada-370-xp: move IRQ handler to avoid forward declaration
  irqchip: move IRQ driver for Armada 370/XP
  ARM: mvebu: move L2 cache initialization in init_early()
  devtree: add binding documentation for sp804
  ARM: integrator-cp: convert use CLKSRC_OF for timer init
  ARM: versatile: use OF init for sp804 timer
  ARM: versatile: add versatile dtbs to dtbs target
  ...
This commit is contained in:
Linus Torvalds 2013-05-07 11:22:14 -07:00
commit 1bf25e78af
79 changed files with 777 additions and 1041 deletions
Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/Kconfig
View file

@ -1059,6 +1059,7 @@ config PLAT_VERSATILE
config ARM_TIMER_SP804
bool
select CLKSRC_MMIO
select CLKSRC_OF if OF
source arch/arm/mm/Kconfig

2
arch/arm/boot/dts/Makefile
View file

@ -194,6 +194,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra30-cardhu-a04.dtb \
tegra114-dalmore.dtb \
tegra114-pluto.dtb
dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
versatile-pb.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
vexpress-v2p-ca9.dtb \
vexpress-v2p-ca15-tc1.dtb \

5
arch/arm/boot/dts/at91sam9g45.dtsi
View file

@ -108,6 +108,7 @@
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <21 4 0>;
#dma-cells = <2>;
};
pinctrl@fffff200 {
@ -533,6 +534,8 @@
compatible = "atmel,hsmci";
reg = <0xfff80000 0x600>;
interrupts = <11 4 0>;
dmas = <&dma 1 0>;
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -542,6 +545,8 @@
compatible = "atmel,hsmci";
reg = <0xfffd0000 0x600>;
interrupts = <29 4 0>;
dmas = <&dma 1 13>;
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";

9
arch/arm/boot/dts/at91sam9n12.dtsi
View file

@ -89,6 +89,8 @@
compatible = "atmel,hsmci";
reg = <0xf0008000 0x600>;
interrupts = <12 4 0>;
dmas = <&dma 1 0>;
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -110,6 +112,7 @@
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <20 4 0>;
#dma-cells = <2>;
};
pinctrl@fffff400 {
@ -378,6 +381,9 @@
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8010000 0x100>;
interrupts = <9 4 6>;
dmas = <&dma 1 13>,
<&dma 1 14>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -387,6 +393,9 @@
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8014000 0x100>;
interrupts = <10 4 6>;
dmas = <&dma 1 15>,
<&dma 1 16>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";

15
arch/arm/boot/dts/at91sam9x5.dtsi
View file

@ -104,12 +104,14 @@
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <20 4 0>;
#dma-cells = <2>;
};
dma1: dma-controller@ffffee00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffee00 0x200>;
interrupts = <21 4 0>;
#dma-cells = <2>;
};
pinctrl@fffff400 {
@ -465,6 +467,8 @@
compatible = "atmel,hsmci";
reg = <0xf0008000 0x600>;
interrupts = <12 4 0>;
dmas = <&dma0 1 0>;
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -474,6 +478,8 @@
compatible = "atmel,hsmci";
reg = <0xf000c000 0x600>;
interrupts = <26 4 0>;
dmas = <&dma1 1 0>;
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -535,6 +541,9 @@
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8010000 0x100>;
interrupts = <9 4 6>;
dmas = <&dma0 1 7>,
<&dma0 1 8>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@ -546,6 +555,9 @@
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8014000 0x100>;
interrupts = <10 4 6>;
dmas = <&dma1 1 5>,
<&dma1 1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@ -557,6 +569,9 @@
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8018000 0x100>;
interrupts = <11 4 6>;
dmas = <&dma0 1 9>,
<&dma0 1 10>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";

6
arch/arm/boot/dts/integratorcp.dts
View file

@ -24,15 +24,15 @@
};
timer0: timer@13000000 {
compatible = "arm,sp804", "arm,primecell";
compatible = "arm,integrator-cp-timer";
};
timer1: timer@13000100 {
compatible = "arm,sp804", "arm,primecell";
compatible = "arm,integrator-cp-timer";
};
timer2: timer@13000200 {
compatible = "arm,sp804", "arm,primecell";
compatible = "arm,integrator-cp-timer";
};
pic: pic@14000000 {

19
arch/arm/boot/dts/sama5d3.dtsi
View file

@ -60,6 +60,8 @@
compatible = "atmel,hsmci";
reg = <0xf0000000 0x600>;
interrupts = <21 4 0>;
dmas = <&dma0 2 0>;
dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
status = "disabled";
@ -111,6 +113,9 @@
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf0014000 0x4000>;
interrupts = <18 4 6>;
dmas = <&dma0 2 7>,
<&dma0 2 8>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
#address-cells = <1>;
@ -122,6 +127,9 @@
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf0018000 0x4000>;
interrupts = <19 4 6>;
dmas = <&dma0 2 9>,
<&dma0 2 10>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
#address-cells = <1>;
@ -167,6 +175,8 @@
compatible = "atmel,hsmci";
reg = <0xf8000000 0x600>;
interrupts = <22 4 0>;
dmas = <&dma1 2 0>;
dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
status = "disabled";
@ -178,6 +188,8 @@
compatible = "atmel,hsmci";
reg = <0xf8004000 0x600>;
interrupts = <23 4 0>;
dmas = <&dma1 2 1>;
dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
status = "disabled";
@ -294,6 +306,9 @@
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf801c000 0x4000>;
interrupts = <20 4 6>;
dmas = <&dma1 2 11>,
<&dma1 2 12>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -348,14 +363,14 @@
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffe600 0x200>;
interrupts = <30 4 0>;
#dma-cells = <1>;
#dma-cells = <2>;
};
dma1: dma-controller@ffffe800 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffe800 0x200>;
interrupts = <31 4 0>;
#dma-cells = <1>;
#dma-cells = <2>;
};
ramc0: ramc@ffffea00 {

2
arch/arm/boot/dts/sama5d34ek.dts
View file

@ -12,7 +12,7 @@
/ {
model = "Atmel SAMA5D34-EK";
compatible = "atmel,sama5d34ek", "atmel,sama5ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
ahb {
apb {

3
arch/arm/boot/dts/spear1340.dtsi
View file

@ -113,6 +113,9 @@
reg = <0xb4100000 0x1000>;
interrupts = <0 105 0x4>;
status = "disabled";
dmas = <&dwdma0 0x600 0 0 1>, /* 0xC << 11 */
<&dwdma0 0x680 0 1 0>; /* 0xD << 7 */
dma-names = "tx", "rx";
};
thermal@e07008c4 {

25
arch/arm/boot/dts/spear13xx.dtsi
View file

@ -98,13 +98,24 @@
reg = <0xb2800000 0x1000>;
interrupts = <0 29 0x4>;
status = "disabled";
dmas = <&dwdma0 0 0 0 0>;
dma-names = "data";
};
dma@ea800000 {
dwdma0: dma@ea800000 {
compatible = "snps,dma-spear1340";
reg = <0xea800000 0x1000>;
interrupts = <0 19 0x4>;
status = "disabled";
dma-channels = <8>;
#dma-cells = <3>;
dma-requests = <32>;
chan_allocation_order = <1>;
chan_priority = <1>;
block_size = <0xfff>;
dma-masters = <2>;
data_width = <3 3 0 0>;
};
dma@eb000000 {
@ -112,6 +123,15 @@
reg = <0xeb000000 0x1000>;
interrupts = <0 59 0x4>;
status = "disabled";
dma-requests = <32>;
dma-channels = <8>;
dma-masters = <2>;
#dma-cells = <3>;
chan_allocation_order = <1>;
chan_priority = <1>;
block_size = <0xfff>;
data_width = <3 3 0 0>;
};
fsmc: flash@b0000000 {
@ -261,6 +281,9 @@
#size-cells = <0>;
interrupts = <0 31 0x4>;
status = "disabled";
dmas = <&dwdma0 0x2000 0 0 0>, /* 0x4 << 11 */
<&dwdma0 0x0280 0 0 0>; /* 0x5 << 7 */
dma-names = "tx", "rx";
};
rtc@e0580000 {

12
arch/arm/boot/dts/versatile-ab.dts
View file

@ -121,6 +121,18 @@
interrupts = <0>;
};
timer@101e2000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x101e2000 0x1000>;
interrupts = <4>;
};
timer@101e3000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x101e3000 0x1000>;
interrupts = <5>;
};
gpio0: gpio@101e4000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x101e4000 0x1000>;

1
arch/arm/boot/dts/vexpress-v2p-ca9.dts
View file

@ -98,6 +98,7 @@
<0 49 4>;
clocks = <&oscclk2>, <&oscclk2>;
clock-names = "timclk", "apb_pclk";
status = "disabled";
};
watchdog@100e5000 {

140
arch/arm/common/timer-sp.c
View file

@ -25,33 +25,29 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/sched_clock.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/timer-sp.h>
static long __init sp804_get_clock_rate(const char *name)
static long __init sp804_get_clock_rate(struct clk *clk)
{
struct clk *clk;
long rate;
int err;
clk = clk_get_sys("sp804", name);
if (IS_ERR(clk)) {
pr_err("sp804: %s clock not found: %d\n", name,
(int)PTR_ERR(clk));
return PTR_ERR(clk);
}
err = clk_prepare(clk);
if (err) {
pr_err("sp804: %s clock failed to prepare: %d\n", name, err);
pr_err("sp804: clock failed to prepare: %d\n", err);
clk_put(clk);
return err;
}
err = clk_enable(clk);
if (err) {
pr_err("sp804: %s clock failed to enable: %d\n", name, err);
pr_err("sp804: clock failed to enable: %d\n", err);
clk_unprepare(clk);
clk_put(clk);
return err;
@ -59,7 +55,7 @@ static long __init sp804_get_clock_rate(const char *name)
rate = clk_get_rate(clk);
if (rate < 0) {
pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate);
pr_err("sp804: clock failed to get rate: %ld\n", rate);
clk_disable(clk);
clk_unprepare(clk);
clk_put(clk);
@ -77,9 +73,21 @@ static u32 sp804_read(void)
void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
const char *name,
struct clk *clk,
int use_sched_clock)
{
long rate = sp804_get_clock_rate(name);
long rate;
if (!clk) {
clk = clk_get_sys("sp804", name);
if (IS_ERR(clk)) {
pr_err("sp804: clock not found: %d\n",
(int)PTR_ERR(clk));
return;
}
}
rate = sp804_get_clock_rate(clk);
if (rate < 0)
return;
@ -171,12 +179,20 @@ static struct irqaction sp804_timer_irq = {
.dev_id = &sp804_clockevent,
};
void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
const char *name)
void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
{
struct clock_event_device *evt = &sp804_clockevent;
long rate = sp804_get_clock_rate(name);
long rate;
if (!clk)
clk = clk_get_sys("sp804", name);
if (IS_ERR(clk)) {
pr_err("sp804: %s clock not found: %d\n", name,
(int)PTR_ERR(clk));
return;
}
rate = sp804_get_clock_rate(clk);
if (rate < 0)
return;
@ -186,6 +202,98 @@ void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
evt->irq = irq;
evt->cpumask = cpu_possible_mask;
writel(0, base + TIMER_CTRL);
setup_irq(irq, &sp804_timer_irq);
clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
}
static void __init sp804_of_init(struct device_node *np)
{
static bool initialized = false;
void __iomem *base;
int irq;
u32 irq_num = 0;
struct clk *clk1, *clk2;
const char *name = of_get_property(np, "compatible", NULL);
base = of_iomap(np, 0);
if (WARN_ON(!base))
return;
/* Ensure timers are disabled */
writel(0, base + TIMER_CTRL);
writel(0, base + TIMER_2_BASE + TIMER_CTRL);
if (initialized || !of_device_is_available(np))
goto err;
clk1 = of_clk_get(np, 0);
if (IS_ERR(clk1))
clk1 = NULL;
/* Get the 2nd clock if the timer has 2 timer clocks */
if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
clk2 = of_clk_get(np, 1);
if (IS_ERR(clk2)) {
pr_err("sp804: %s clock not found: %d\n", np->name,
(int)PTR_ERR(clk2));
goto err;
}
} else
clk2 = clk1;
irq = irq_of_parse_and_map(np, 0);
if (irq <= 0)
goto err;
of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
if (irq_num == 2) {
__sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
__sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
} else {
__sp804_clockevents_init(base, irq, clk1 , name);
__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
name, clk2, 1);
}
initialized = true;
return;
err:
iounmap(base);
}
CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
static void __init integrator_cp_of_init(struct device_node *np)
{
static int init_count = 0;
void __iomem *base;
int irq;
const char *name = of_get_property(np, "compatible", NULL);
base = of_iomap(np, 0);
if (WARN_ON(!base))
return;
/* Ensure timer is disabled */
writel(0, base + TIMER_CTRL);
if (init_count == 2 || !of_device_is_available(np))
goto err;
if (!init_count)
sp804_clocksource_init(base, name);
else {
irq = irq_of_parse_and_map(np, 0);
if (irq <= 0)
goto err;
sp804_clockevents_init(base, irq, name);
}
init_count++;
return;
err:
iounmap(base);
}
CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);

13
arch/arm/include/asm/arch_timer.h
View file

@ -10,8 +10,7 @@
#include <clocksource/arm_arch_timer.h>
#ifdef CONFIG_ARM_ARCH_TIMER
int arch_timer_of_register(void);
int arch_timer_sched_clock_init(void);
int arch_timer_arch_init(void);
/*
* These register accessors are marked inline so the compiler can
@ -110,16 +109,6 @@ static inline void __cpuinit arch_counter_set_user_access(void)
asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
}
#else
static inline int arch_timer_of_register(void)
{
return -ENXIO;
}
static inline int arch_timer_sched_clock_init(void)
{
return -ENXIO;
}
#endif
#endif

16
arch/arm/include/asm/hardware/timer-sp.h
View file

@ -1,15 +1,23 @@
struct clk;
void __sp804_clocksource_and_sched_clock_init(void __iomem *,
const char *, int);
const char *, struct clk *, int);
void __sp804_clockevents_init(void __iomem *, unsigned int,
struct clk *, const char *);
static inline void sp804_clocksource_init(void __iomem *base, const char *name)
{
__sp804_clocksource_and_sched_clock_init(base, name, 0);
__sp804_clocksource_and_sched_clock_init(base, name, NULL, 0);
}
static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base,
const char *name)
{
__sp804_clocksource_and_sched_clock_init(base, name, 1);
__sp804_clocksource_and_sched_clock_init(base, name, NULL, 1);
}
void sp804_clockevents_init(void __iomem *, unsigned int, const char *);
static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name)
{
__sp804_clockevents_init(base, irq, NULL, name);
}

2
arch/arm/include/asm/sched_clock.h
View file

@ -11,4 +11,6 @@
extern void sched_clock_postinit(void);
extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate);
extern unsigned long long (*sched_clock_func)(void);
#endif

31
arch/arm/kernel/arch_timer.c
View file

@ -22,9 +22,11 @@ static unsigned long arch_timer_read_counter_long(void)
return arch_timer_read_counter();
}
static u32 arch_timer_read_counter_u32(void)
static u32 sched_clock_mult __read_mostly;
static unsigned long long notrace arch_timer_sched_clock(void)
{
return arch_timer_read_counter();
return arch_timer_read_counter() * sched_clock_mult;
}
static struct delay_timer arch_delay_timer;
@ -37,25 +39,20 @@ static void __init arch_timer_delay_timer_register(void)
register_current_timer_delay(&arch_delay_timer);
}
int __init arch_timer_of_register(void)
int __init arch_timer_arch_init(void)
{
int ret;
u32 arch_timer_rate = arch_timer_get_rate();
ret = arch_timer_init();
if (ret)
return ret;
if (arch_timer_rate == 0)
return -ENXIO;
arch_timer_delay_timer_register();
return 0;
}
int __init arch_timer_sched_clock_init(void)
{
if (arch_timer_get_rate() == 0)
return -ENXIO;
setup_sched_clock(arch_timer_read_counter_u32,
32, arch_timer_get_rate());
/* Cache the sched_clock multiplier to save a divide in the hot path. */
sched_clock_mult = NSEC_PER_SEC / arch_timer_rate;
sched_clock_func = arch_timer_sched_clock;
pr_info("sched_clock: ARM arch timer >56 bits at %ukHz, resolution %uns\n",
arch_timer_rate / 1000, sched_clock_mult);
return 0;
}

15
arch/arm/kernel/sched_clock.c
View file

@ -20,6 +20,7 @@ struct clock_data {
u64 epoch_ns;
u32 epoch_cyc;
u32 epoch_cyc_copy;
unsigned long rate;
u32 mult;
u32 shift;
bool suspended;
@ -113,11 +114,14 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
u64 res, wrap;
char r_unit;
if (cd.rate > rate)
return;
BUG_ON(bits > 32);
WARN_ON(!irqs_disabled());
WARN_ON(read_sched_clock != jiffy_sched_clock_read);
read_sched_clock = read;
sched_clock_mask = (1 << bits) - 1;
cd.rate = rate;
/* calculate the mult/shift to convert counter ticks to ns. */
clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0);
@ -161,12 +165,19 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
pr_debug("Registered %pF as sched_clock source\n", read);
}
unsigned long long notrace sched_clock(void)
static unsigned long long notrace sched_clock_32(void)
{
u32 cyc = read_sched_clock();
return cyc_to_sched_clock(cyc, sched_clock_mask);
}
unsigned long long __read_mostly (*sched_clock_func)(void) = sched_clock_32;
unsigned long long notrace sched_clock(void)
{
return sched_clock_func();
}
void __init sched_clock_postinit(void)
{
/*

7
arch/arm/kernel/time.c
View file

@ -22,6 +22,7 @@
#include <linux/errno.h>
#include <linux/profile.h>
#include <linux/timer.h>
#include <linux/clocksource.h>
#include <linux/irq.h>
#include <asm/thread_info.h>
@ -115,6 +116,10 @@ int __init register_persistent_clock(clock_access_fn read_boot,
void __init time_init(void)
{
machine_desc->init_time();
if (machine_desc->init_time)
machine_desc->init_time();
else
clocksource_of_init();
sched_clock_postinit();
}

2
arch/arm/mach-at91/cpuidle.c
View file

@ -36,6 +36,8 @@ static int at91_enter_idle(struct cpuidle_device *dev,
at91rm9200_standby();
else if (cpu_is_at91sam9g45())
at91sam9g45_standby();
else if (cpu_is_at91sam9263())
at91sam9263_standby();
else
at91sam9_standby();

9
arch/arm/mach-at91/include/mach/cpu.h
View file

@ -86,7 +86,7 @@ enum at91_soc_type {
AT91_SOC_SAMA5D3,
/* Unknown type */
AT91_SOC_NONE
AT91_SOC_UNKNOWN,
};
enum at91_soc_subtype {
@ -107,8 +107,11 @@ enum at91_soc_subtype {
AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
AT91_SOC_SAMA5D35,
/* No subtype for this SoC */
AT91_SOC_SUBTYPE_NONE,
/* Unknown subtype */
AT91_SOC_SUBTYPE_NONE
AT91_SOC_SUBTYPE_UNKNOWN,
};
struct at91_socinfo {
@ -122,7 +125,7 @@ const char *at91_get_soc_subtype(struct at91_socinfo *c);
static inline int at91_soc_is_detected(void)
{
return at91_soc_initdata.type != AT91_SOC_NONE;
return at91_soc_initdata.type != AT91_SOC_UNKNOWN;
}
#ifdef CONFIG_SOC_AT91RM9200

2
arch/arm/mach-at91/pm.c
View file

@ -270,6 +270,8 @@ static int at91_pm_enter(suspend_state_t state)
at91rm9200_standby();
else if (cpu_is_at91sam9g45())
at91sam9g45_standby();
else if (cpu_is_at91sam9263())
at91sam9263_standby();
else
at91sam9_standby();
break;

30
arch/arm/mach-at91/pm.h
View file

@ -70,13 +70,31 @@ static inline void at91sam9g45_standby(void)
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
}
#ifdef CONFIG_SOC_AT91SAM9263
/*
* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
* handle those cases both here and in the Suspend-To-RAM support.
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
* remember.
*/
#warning Assuming EB1 SDRAM controller is *NOT* used
#endif
static inline void at91sam9263_standby(void)
{
u32 lpr0, lpr1;
u32 saved_lpr0, saved_lpr1;
saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
/* self-refresh mode now */
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
cpu_do_idle();
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
}
static inline void at91sam9_standby(void)
{

22
arch/arm/mach-at91/setup.c
View file

@ -105,28 +105,32 @@ static void __init soc_detect(u32 dbgu_base)
switch (socid) {
case ARCH_ID_AT91RM9200:
at91_soc_initdata.type = AT91_SOC_RM9200;
if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE)
if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
at91_boot_soc = at91rm9200_soc;
break;
case ARCH_ID_AT91SAM9260:
at91_soc_initdata.type = AT91_SOC_SAM9260;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9260_soc;
break;
case ARCH_ID_AT91SAM9261:
at91_soc_initdata.type = AT91_SOC_SAM9261;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9261_soc;
break;
case ARCH_ID_AT91SAM9263:
at91_soc_initdata.type = AT91_SOC_SAM9263;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9263_soc;
break;
case ARCH_ID_AT91SAM9G20:
at91_soc_initdata.type = AT91_SOC_SAM9G20;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9260_soc;
break;
@ -139,6 +143,7 @@ static void __init soc_detect(u32 dbgu_base)
case ARCH_ID_AT91SAM9RL64:
at91_soc_initdata.type = AT91_SOC_SAM9RL;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9rl_soc;
break;
@ -161,6 +166,7 @@ static void __init soc_detect(u32 dbgu_base)
/* at91sam9g10 */
if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
at91_soc_initdata.type = AT91_SOC_SAM9G10;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9261_soc;
}
/* at91sam9xe */
@ -242,7 +248,7 @@ static const char *soc_name[] = {
[AT91_SOC_SAM9X5] = "at91sam9x5",
[AT91_SOC_SAM9N12] = "at91sam9n12",
[AT91_SOC_SAMA5D3] = "sama5d3",
[AT91_SOC_NONE] = "Unknown"
[AT91_SOC_UNKNOWN] = "Unknown",
};
const char *at91_get_soc_type(struct at91_socinfo *c)
@ -268,7 +274,8 @@ static const char *soc_subtype_name[] = {
[AT91_SOC_SAMA5D33] = "sama5d33",
[AT91_SOC_SAMA5D34] = "sama5d34",
[AT91_SOC_SAMA5D35] = "sama5d35",
[AT91_SOC_SUBTYPE_NONE] = "Unknown"
[AT91_SOC_SUBTYPE_NONE] = "None",
[AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
};
const char *at91_get_soc_subtype(struct at91_socinfo *c)
@ -282,8 +289,8 @@ void __init at91_map_io(void)
/* Map peripherals */
iotable_init(&at91_io_desc, 1);
at91_soc_initdata.type = AT91_SOC_NONE;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_soc_initdata.type = AT91_SOC_UNKNOWN;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
soc_detect(AT91_BASE_DBGU0);
if (!at91_soc_is_detected())
@ -294,8 +301,9 @@ void __init at91_map_io(void)
pr_info("AT91: Detected soc type: %s\n",
at91_get_soc_type(&at91_soc_initdata));
pr_info("AT91: Detected soc subtype: %s\n",
at91_get_soc_subtype(&at91_soc_initdata));
if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
pr_info("AT91: Detected soc subtype: %s\n",
at91_get_soc_subtype(&at91_soc_initdata));
if (!at91_soc_is_enabled())
panic("AT91: Soc not enabled");

24
arch/arm/mach-highbank/highbank.c
View file

@ -15,6 +15,7 @@
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/irq.h>
@ -28,12 +29,9 @@
#include <linux/amba/bus.h>
#include <linux/clk-provider.h>
#include <asm/arch_timer.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/smp_plat.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/timer-sp.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -90,36 +88,16 @@ static void __init highbank_init_irq(void)
#endif
}
static struct clk_lookup lookup = {
.dev_id = "sp804",
.con_id = NULL,
};
static void __init highbank_timer_init(void)
{
int irq;
struct device_node *np;
void __iomem *timer_base;
/* Map system registers */
np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
sregs_base = of_iomap(np, 0);
WARN_ON(!sregs_base);
np = of_find_compatible_node(NULL, NULL, "arm,sp804");
timer_base = of_iomap(np, 0);
WARN_ON(!timer_base);
irq = irq_of_parse_and_map(np, 0);
of_clk_init(NULL);
lookup.clk = of_clk_get(np, 0);
clkdev_add(&lookup);
sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
sp804_clockevents_init(timer_base, irq, "timer0");
arch_timer_of_register();
arch_timer_sched_clock_init();
clocksource_of_init();
}

34
arch/arm/mach-integrator/integrator_cp.c
View file

@ -250,39 +250,6 @@ static void __init intcp_init_early(void)
}
#ifdef CONFIG_OF
static void __init cp_of_timer_init(void)
{
struct device_node *node;
const char *path;
void __iomem *base;
int err;
int irq;
err = of_property_read_string(of_aliases,
"arm,timer-primary", &path);
if (WARN_ON(err))
return;
node = of_find_node_by_path(path);
base = of_iomap(node, 0);
if (WARN_ON(!base))
return;
writel(0, base + TIMER_CTRL);
sp804_clocksource_init(base, node->name);
err = of_property_read_string(of_aliases,
"arm,timer-secondary", &path);
if (WARN_ON(err))
return;
node = of_find_node_by_path(path);
base = of_iomap(node, 0);
if (WARN_ON(!base))
return;
irq = irq_of_parse_and_map(node, 0);
writel(0, base + TIMER_CTRL);
sp804_clockevents_init(base, irq, node->name);
}
static const struct of_device_id fpga_irq_of_match[] __initconst = {
{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
{ /* Sentinel */ }
@ -383,7 +350,6 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
.init_early = intcp_init_early,
.init_irq = intcp_init_irq_of,
.handle_irq = fpga_handle_irq,
.init_time = cp_of_timer_init,
.init_machine = intcp_init_of,
.restart = integrator_restart,
.dt_compat = intcp_dt_board_compat,

2
arch/arm/mach-mvebu/Makefile
View file

@ -5,6 +5,6 @@ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
obj-y += system-controller.o
obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o
obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o

9
arch/arm/mach-mvebu/armada-370-xp.c
View file

@ -20,6 +20,8 @@
#include <linux/clk/mvebu.h>
#include <linux/dma-mapping.h>
#include <linux/mbus.h>
#include <linux/irqchip.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
@ -72,6 +74,10 @@ void __init armada_370_xp_init_early(void)
ARMADA_370_XP_MBUS_WINS_SIZE,
ARMADA_370_XP_SDRAM_WINS_BASE,
ARMADA_370_XP_SDRAM_WINS_SIZE);
#ifdef CONFIG_CACHE_L2X0
l2x0_of_init(0, ~0UL);
#endif
}
static void __init armada_370_xp_dt_init(void)
@ -90,8 +96,7 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
.init_machine = armada_370_xp_dt_init,
.map_io = armada_370_xp_map_io,
.init_early = armada_370_xp_init_early,
.init_irq = armada_370_xp_init_irq,
.handle_irq = armada_370_xp_handle_irq,
.init_irq = irqchip_init,
.init_time = armada_370_xp_timer_and_clk_init,
.restart = mvebu_restart,
.dt_compat = armada_370_xp_dt_compat,

292
arch/arm/mach-mvebu/irq-armada-370-xp.c
View file

@ -1,292 +0,0 @@
/*
* Marvell Armada 370 and Armada XP SoC IRQ handling
*
* Copyright (C) 2012 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Ben Dooks <ben.dooks@codethink.co.uk>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqdomain.h>
#include <asm/mach/arch.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>
#include <asm/hardware/cache-l2x0.h>
/* Interrupt Controller Registers Map */
#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
#define ARMADA_370_XP_INT_CONTROL (0x00)
#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
#define ACTIVE_DOORBELLS (8)
static DEFINE_RAW_SPINLOCK(irq_controller_lock);
static void __iomem *per_cpu_int_base;
static void __iomem *main_int_base;
static struct irq_domain *armada_370_xp_mpic_domain;
/*
* In SMP mode:
* For shared global interrupts, mask/unmask global enable bit
* For CPU interrupts, mask/unmask the calling CPU's bit
*/
static void armada_370_xp_irq_mask(struct irq_data *d)
{
irq_hw_number_t hwirq = irqd_to_hwirq(d);
if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
writel(hwirq, main_int_base +
ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
else
writel(hwirq, per_cpu_int_base +
ARMADA_370_XP_INT_SET_MASK_OFFS);
}
static void armada_370_xp_irq_unmask(struct irq_data *d)
{
irq_hw_number_t hwirq = irqd_to_hwirq(d);
if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
writel(hwirq, main_int_base +
ARMADA_370_XP_INT_SET_ENABLE_OFFS);
else
writel(hwirq, per_cpu_int_base +
ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}
#ifdef CONFIG_SMP
static int armada_xp_set_affinity(struct irq_data *d,
const struct cpumask *mask_val, bool force)
{
unsigned long reg;
unsigned long new_mask = 0;
unsigned long online_mask = 0;
unsigned long count = 0;
irq_hw_number_t hwirq = irqd_to_hwirq(d);
int cpu;
for_each_cpu(cpu, mask_val) {
new_mask |= 1 << cpu_logical_map(cpu);
count++;
}
/*
* Forbid mutlicore interrupt affinity
* This is required since the MPIC HW doesn't limit
* several CPUs from acknowledging the same interrupt.
*/
if (count > 1)
return -EINVAL;
for_each_cpu(cpu, cpu_online_mask)
online_mask |= 1 << cpu_logical_map(cpu);
raw_spin_lock(&irq_controller_lock);
reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
reg = (reg & (~online_mask)) | new_mask;
writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
raw_spin_unlock(&irq_controller_lock);
return 0;
}
#endif
static struct irq_chip armada_370_xp_irq_chip = {
.name = "armada_370_xp_irq",
.irq_mask = armada_370_xp_irq_mask,
.irq_mask_ack = armada_370_xp_irq_mask,
.irq_unmask = armada_370_xp_irq_unmask,
#ifdef CONFIG_SMP
.irq_set_affinity = armada_xp_set_affinity,
#endif
};
static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
unsigned int virq, irq_hw_number_t hw)
{
armada_370_xp_irq_mask(irq_get_irq_data(virq));
if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
writel(hw, per_cpu_int_base +
ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
else
writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
irq_set_status_flags(virq, IRQ_LEVEL);
if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
irq_set_percpu_devid(virq);
irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
handle_percpu_devid_irq);
} else {
irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
handle_level_irq);
}
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
return 0;
}
#ifdef CONFIG_SMP
void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
{
int cpu;
unsigned long map = 0;
/* Convert our logical CPU mask into a physical one. */
for_each_cpu(cpu, mask)
map |= 1 << cpu_logical_map(cpu);
/*
* Ensure that stores to Normal memory are visible to the
* other CPUs before issuing the IPI.
*/
dsb();
/* submit softirq */
writel((map << 8) | irq, main_int_base +
ARMADA_370_XP_SW_TRIG_INT_OFFS);
}
void armada_xp_mpic_smp_cpu_init(void)
{
/* Clear pending IPIs */
writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
/* Enable first 8 IPIs */
writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base +
ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
/* Unmask IPI interrupt */
writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}
#endif /* CONFIG_SMP */
static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
.map = armada_370_xp_mpic_irq_map,
.xlate = irq_domain_xlate_onecell,
};
static int __init armada_370_xp_mpic_of_init(struct device_node *node,
struct device_node *parent)
{
u32 control;
main_int_base = of_iomap(node, 0);
per_cpu_int_base = of_iomap(node, 1);
BUG_ON(!main_int_base);
BUG_ON(!per_cpu_int_base);
control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
armada_370_xp_mpic_domain =
irq_domain_add_linear(node, (control >> 2) & 0x3ff,
&armada_370_xp_mpic_irq_ops, NULL);
if (!armada_370_xp_mpic_domain)
panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
irq_set_default_host(armada_370_xp_mpic_domain);
#ifdef CONFIG_SMP
armada_xp_mpic_smp_cpu_init();
/*
* Set the default affinity from all CPUs to the boot cpu.
* This is required since the MPIC doesn't limit several CPUs
* from acknowledging the same interrupt.
*/
cpumask_clear(irq_default_affinity);
cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
#endif
return 0;
}
asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
*regs)
{
u32 irqstat, irqnr;
do {
irqstat = readl_relaxed(per_cpu_int_base +
ARMADA_370_XP_CPU_INTACK_OFFS);
irqnr = irqstat & 0x3FF;
if (irqnr > 1022)
break;
if (irqnr > 0) {
irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
irqnr);
handle_IRQ(irqnr, regs);
continue;
}
#ifdef CONFIG_SMP
/* IPI Handling */
if (irqnr == 0) {
u32 ipimask, ipinr;
ipimask = readl_relaxed(per_cpu_int_base +
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
& 0xFF;
writel(0x0, per_cpu_int_base +
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
/* Handle all pending doorbells */
for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) {
if (ipimask & (0x1 << ipinr))
handle_IPI(ipinr, regs);
}
continue;
}
#endif
} while (1);
}
static const struct of_device_id mpic_of_match[] __initconst = {
{.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
{},
};
void __init armada_370_xp_init_irq(void)
{
of_irq_init(mpic_of_match);
#ifdef CONFIG_CACHE_L2X0
l2x0_of_init(0, ~0UL);
#endif
}

43
arch/arm/mach-omap2/board-2430sdp.c
View file

@ -108,24 +108,13 @@ static struct platform_device *sdp2430_devices[] __initdata = {
#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91
#define SDP2430_LCD_PANEL_ENABLE_GPIO 154
static int sdp2430_panel_enable_lcd(struct omap_dss_device *dssdev)
{
gpio_direction_output(SDP2430_LCD_PANEL_ENABLE_GPIO, 1);
gpio_direction_output(SDP2430_LCD_PANEL_BACKLIGHT_GPIO, 1);
return 0;
}
static void sdp2430_panel_disable_lcd(struct omap_dss_device *dssdev)
{
gpio_direction_output(SDP2430_LCD_PANEL_ENABLE_GPIO, 0);
gpio_direction_output(SDP2430_LCD_PANEL_BACKLIGHT_GPIO, 0);
}
static struct panel_generic_dpi_data sdp2430_panel_data = {
.name = "nec_nl2432dr22-11b",
.platform_enable = sdp2430_panel_enable_lcd,
.platform_disable = sdp2430_panel_disable_lcd,
.num_gpios = 2,
.gpios = {
SDP2430_LCD_PANEL_ENABLE_GPIO,
SDP2430_LCD_PANEL_BACKLIGHT_GPIO,
},
};
static struct omap_dss_device sdp2430_lcd_device = {
@ -146,26 +135,6 @@ static struct omap_dss_board_info sdp2430_dss_data = {
.default_device = &sdp2430_lcd_device,
};
static void __init sdp2430_display_init(void)
{
int r;
static struct gpio gpios[] __initdata = {
{ SDP2430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
"LCD reset" },
{ SDP2430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW,
"LCD Backlight" },
};
r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
if (r) {
pr_err("Cannot request LCD GPIOs, error %d\n", r);
return;
}
omap_display_init(&sdp2430_dss_data);
}
#if IS_ENABLED(CONFIG_SMC91X)
static struct omap_smc91x_platform_data board_smc91x_data = {
@ -273,7 +242,7 @@ static void __init omap_2430sdp_init(void)
gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW,
"Secondary LCD backlight");
sdp2430_display_init();
omap_display_init(&sdp2430_dss_data);
}
MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")

53
arch/arm/mach-omap2/board-3430sdp.c
View file

@ -108,53 +108,38 @@ static struct twl4030_keypad_data sdp3430_kp_data = {
#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
#define SDP3430_LCD_PANEL_ENABLE_GPIO 5
static struct gpio sdp3430_dss_gpios[] __initdata = {
{SDP3430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, "LCD reset" },
{SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
};
static void __init sdp3430_display_init(void)
{
int r;
r = gpio_request_array(sdp3430_dss_gpios,
ARRAY_SIZE(sdp3430_dss_gpios));
/*
* the backlight GPIO doesn't directly go to the panel, it enables
* an internal circuit on 3430sdp to create the signal V_BKL_28V,
* this is connected to LED+ pin of the sharp panel. This GPIO
* is left enabled in the board file, and not passed to the panel
* as platform_data.
*/
r = gpio_request_one(SDP3430_LCD_PANEL_BACKLIGHT_GPIO,
GPIOF_OUT_INIT_HIGH, "LCD Backlight");
if (r)
printk(KERN_ERR "failed to get LCD control GPIOs\n");
pr_err("failed to get LCD Backlight GPIO\n");
}
static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
{
gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
return 0;
}
static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
{
gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
}
static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
{
return 0;
}
static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
{
}
static struct panel_sharp_ls037v7dw01_data sdp3430_lcd_data = {
.resb_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO,
.ini_gpio = -1,
.mo_gpio = -1,
.lr_gpio = -1,
.ud_gpio = -1,
};
static struct omap_dss_device sdp3430_lcd_device = {
.name = "lcd",
.driver_name = "sharp_ls_panel",
.type = OMAP_DISPLAY_TYPE_DPI,
.phy.dpi.data_lines = 16,
.platform_enable = sdp3430_panel_enable_lcd,
.platform_disable = sdp3430_panel_disable_lcd,
.data = &sdp3430_lcd_data,
};
static struct tfp410_platform_data dvi_panel = {
@ -175,8 +160,6 @@ static struct omap_dss_device sdp3430_tv_device = {
.driver_name = "venc",
.type = OMAP_DISPLAY_TYPE_VENC,
.phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
.platform_enable = sdp3430_panel_enable_tv,
.platform_disable = sdp3430_panel_disable_tv,
};

2
arch/arm/mach-omap2/board-4430sdp.c
View file

@ -730,7 +730,7 @@ static void __init omap_4430sdp_init(void)
omap4_sdp4430_wifi_init();
omap4_twl6030_hsmmc_init(mmc);
usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
usb_musb_init(&musb_board_data);
status = omap_ethernet_init();

74
arch/arm/mach-omap2/board-am3517evm.c
View file

@ -120,63 +120,14 @@ static int __init am3517_evm_i2c_init(void)
return 0;
}
static int lcd_enabled;
static int dvi_enabled;
#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
static struct gpio am3517_evm_dss_gpios[] __initdata = {
/* GPIO 182 = LCD Backlight Power */
{ LCD_PANEL_BKLIGHT_PWR, GPIOF_OUT_INIT_HIGH, "lcd_backlight_pwr" },
/* GPIO 181 = LCD Panel PWM */
{ LCD_PANEL_PWM, GPIOF_OUT_INIT_HIGH, "lcd bl enable" },
/* GPIO 176 = LCD Panel Power enable pin */
{ LCD_PANEL_PWR, GPIOF_OUT_INIT_HIGH, "dvi enable" },
};
static void __init am3517_evm_display_init(void)
{
int r;
omap_mux_init_gpio(LCD_PANEL_PWR, OMAP_PIN_INPUT_PULLUP);
omap_mux_init_gpio(LCD_PANEL_BKLIGHT_PWR, OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_gpio(LCD_PANEL_PWM, OMAP_PIN_INPUT_PULLDOWN);
r = gpio_request_array(am3517_evm_dss_gpios,
ARRAY_SIZE(am3517_evm_dss_gpios));
if (r) {
printk(KERN_ERR "failed to get DSS panel control GPIOs\n");
return;
}
printk(KERN_INFO "Display initialized successfully\n");
}
#else
static void __init am3517_evm_display_init(void) {}
#endif
static int am3517_evm_panel_enable_lcd(struct omap_dss_device *dssdev)
{
if (dvi_enabled) {
printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
return -EINVAL;
}
gpio_set_value(LCD_PANEL_PWR, 1);
lcd_enabled = 1;
return 0;
}
static void am3517_evm_panel_disable_lcd(struct omap_dss_device *dssdev)
{
gpio_set_value(LCD_PANEL_PWR, 0);
lcd_enabled = 0;
}
static struct panel_generic_dpi_data lcd_panel = {
.name = "sharp_lq",
.platform_enable = am3517_evm_panel_enable_lcd,
.platform_disable = am3517_evm_panel_disable_lcd,
.num_gpios = 3,
.gpios = {
LCD_PANEL_PWR,
LCD_PANEL_BKLIGHT_PWR,
LCD_PANEL_PWM,
},
};
static struct omap_dss_device am3517_evm_lcd_device = {
@ -187,22 +138,11 @@ static struct omap_dss_device am3517_evm_lcd_device = {
.phy.dpi.data_lines = 16,
};
static int am3517_evm_panel_enable_tv(struct omap_dss_device *dssdev)
{
return 0;
}
static void am3517_evm_panel_disable_tv(struct omap_dss_device *dssdev)
{
}
static struct omap_dss_device am3517_evm_tv_device = {
.type = OMAP_DISPLAY_TYPE_VENC,
.name = "tv",
.driver_name = "venc",
.phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
.platform_enable = am3517_evm_panel_enable_tv,
.platform_disable = am3517_evm_panel_disable_tv,
};
static struct tfp410_platform_data dvi_panel = {
@ -365,8 +305,6 @@ static void __init am3517_evm_init(void)
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
usbhs_init(&usbhs_bdata);
am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
/* DSS */
am3517_evm_display_init();
/* RTC - S35390A */
am3517_evm_rtc_init();

60
arch/arm/mach-omap2/board-cm-t35.c
View file

@ -190,45 +190,12 @@ static inline void cm_t35_init_nand(void) {}
#define CM_T35_LCD_BL_GPIO 58
#define CM_T35_DVI_EN_GPIO 54
static int lcd_enabled;
static int dvi_enabled;
static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev)
{
if (dvi_enabled) {
printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
return -EINVAL;
}
gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
gpio_set_value(CM_T35_LCD_BL_GPIO, 1);
lcd_enabled = 1;
return 0;
}
static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
{
lcd_enabled = 0;
gpio_set_value(CM_T35_LCD_BL_GPIO, 0);
gpio_set_value(CM_T35_LCD_EN_GPIO, 0);
}
static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev)
{
return 0;
}
static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev)
{
}
static struct panel_generic_dpi_data lcd_panel = {
.name = "toppoly_tdo35s",
.platform_enable = cm_t35_panel_enable_lcd,
.platform_disable = cm_t35_panel_disable_lcd,
.num_gpios = 1,
.gpios = {
CM_T35_LCD_BL_GPIO,
},
};
static struct omap_dss_device cm_t35_lcd_device = {
@ -257,8 +224,6 @@ static struct omap_dss_device cm_t35_tv_device = {
.driver_name = "venc",
.type = OMAP_DISPLAY_TYPE_VENC,
.phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
.platform_enable = cm_t35_panel_enable_tv,
.platform_disable = cm_t35_panel_disable_tv,
};
static struct omap_dss_device *cm_t35_dss_devices[] = {
@ -292,11 +257,6 @@ static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
},
};
static struct gpio cm_t35_dss_gpios[] __initdata = {
{ CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" },
{ CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" },
};
static void __init cm_t35_init_display(void)
{
int err;
@ -304,23 +264,21 @@ static void __init cm_t35_init_display(void)
spi_register_board_info(cm_t35_lcd_spi_board_info,
ARRAY_SIZE(cm_t35_lcd_spi_board_info));
err = gpio_request_array(cm_t35_dss_gpios,
ARRAY_SIZE(cm_t35_dss_gpios));
err = gpio_request_one(CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW,
"lcd bl enable");
if (err) {
pr_err("CM-T35: failed to request DSS control GPIOs\n");
pr_err("CM-T35: failed to request LCD EN GPIO\n");
return;
}
gpio_export(CM_T35_LCD_EN_GPIO, 0);
gpio_export(CM_T35_LCD_BL_GPIO, 0);
msleep(50);
gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
err = omap_display_init(&cm_t35_dss_data);
if (err) {
pr_err("CM-T35: failed to register DSS device\n");
gpio_free_array(cm_t35_dss_gpios, ARRAY_SIZE(cm_t35_dss_gpios));
gpio_free(CM_T35_LCD_EN_GPIO);
}
}

27
arch/arm/mach-omap2/board-devkit8000.c
View file

@ -103,19 +103,6 @@ static struct omap2_hsmmc_info mmc[] = {
{} /* Terminator */
};
static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
{
if (gpio_is_valid(dssdev->reset_gpio))
gpio_set_value_cansleep(dssdev->reset_gpio, 1);
return 0;
}
static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
{
if (gpio_is_valid(dssdev->reset_gpio))
gpio_set_value_cansleep(dssdev->reset_gpio, 0);
}
static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
@ -127,8 +114,7 @@ static struct regulator_consumer_supply devkit8000_vio_supply[] = {
static struct panel_generic_dpi_data lcd_panel = {
.name = "innolux_at070tn83",
.platform_enable = devkit8000_panel_enable_lcd,
.platform_disable = devkit8000_panel_disable_lcd,
/* gpios filled in code */
};
static struct omap_dss_device devkit8000_lcd_device = {
@ -210,8 +196,6 @@ static struct gpio_led gpio_leds[];
static int devkit8000_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
int ret;
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap_hsmmc_late_init(mmc);
@ -220,13 +204,8 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
/* TWL4030_GPIO_MAX + 0 is "LCD_PWREN" (out, active high) */
devkit8000_lcd_device.reset_gpio = gpio + TWL4030_GPIO_MAX + 0;
ret = gpio_request_one(devkit8000_lcd_device.reset_gpio,
GPIOF_OUT_INIT_LOW, "LCD_PWREN");
if (ret < 0) {
devkit8000_lcd_device.reset_gpio = -EINVAL;
printk(KERN_ERR "Failed to request GPIO for LCD_PWRN\n");
}
lcd_panel.num_gpios = 1;
lcd_panel.gpios[0] = gpio + TWL4030_GPIO_MAX + 0;
/* gpio + 7 is "DVI_PD" (out, active low) */
dvi_panel.power_down_gpio = gpio + 7;

59
arch/arm/mach-omap2/board-ldp.c
View file

@ -181,34 +181,13 @@ static inline void __init ldp_init_smsc911x(void)
/* LCD */
static int ldp_backlight_gpio;
static int ldp_lcd_enable_gpio;
#define LCD_PANEL_RESET_GPIO 55
#define LCD_PANEL_QVGA_GPIO 56
static int ldp_panel_enable_lcd(struct omap_dss_device *dssdev)
{
if (gpio_is_valid(ldp_lcd_enable_gpio))
gpio_direction_output(ldp_lcd_enable_gpio, 1);
if (gpio_is_valid(ldp_backlight_gpio))
gpio_direction_output(ldp_backlight_gpio, 1);
return 0;
}
static void ldp_panel_disable_lcd(struct omap_dss_device *dssdev)
{
if (gpio_is_valid(ldp_lcd_enable_gpio))
gpio_direction_output(ldp_lcd_enable_gpio, 0);
if (gpio_is_valid(ldp_backlight_gpio))
gpio_direction_output(ldp_backlight_gpio, 0);
}
static struct panel_generic_dpi_data ldp_panel_data = {
.name = "nec_nl2432dr22-11b",
.platform_enable = ldp_panel_enable_lcd,
.platform_disable = ldp_panel_disable_lcd,
.num_gpios = 4,
/* gpios filled in code */
};
static struct omap_dss_device ldp_lcd_device = {
@ -231,41 +210,19 @@ static struct omap_dss_board_info ldp_dss_data = {
static void __init ldp_display_init(void)
{
int r;
static struct gpio gpios[] __initdata = {
{LCD_PANEL_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "LCD RESET"},
{LCD_PANEL_QVGA_GPIO, GPIOF_OUT_INIT_HIGH, "LCD QVGA"},
};
r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
if (r) {
pr_err("Cannot request LCD GPIOs, error %d\n", r);
return;
}
ldp_panel_data.gpios[2] = LCD_PANEL_RESET_GPIO;
ldp_panel_data.gpios[3] = LCD_PANEL_QVGA_GPIO;
omap_display_init(&ldp_dss_data);
}
static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio)
{
int r;
ldp_panel_data.gpios[0] = gpio + 7;
ldp_panel_data.gpio_invert[0] = true;
struct gpio gpios[] = {
{gpio + 7 , GPIOF_OUT_INIT_LOW, "LCD ENABLE"},
{gpio + 15, GPIOF_OUT_INIT_LOW, "LCD BACKLIGHT"},
};
r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
if (r) {
pr_err("Cannot request LCD GPIOs, error %d\n", r);
ldp_backlight_gpio = -EINVAL;
ldp_lcd_enable_gpio = -EINVAL;
return r;
}
ldp_backlight_gpio = gpio + 15;
ldp_lcd_enable_gpio = gpio + 7;
ldp_panel_data.gpios[1] = gpio + 15;
ldp_panel_data.gpio_invert[1] = true;
return 0;
}

70
arch/arm/mach-omap2/board-omap3evm.c
View file

@ -155,61 +155,43 @@ static inline void __init omap3evm_init_smsc911x(void) { return; }
#define OMAP3EVM_LCD_PANEL_LR 2
#define OMAP3EVM_LCD_PANEL_UD 3
#define OMAP3EVM_LCD_PANEL_INI 152
#define OMAP3EVM_LCD_PANEL_ENVDD 153
#define OMAP3EVM_LCD_PANEL_QVGA 154
#define OMAP3EVM_LCD_PANEL_RESB 155
#define OMAP3EVM_LCD_PANEL_ENVDD 153
#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
/*
* OMAP3EVM DVI control signals
*/
#define OMAP3EVM_DVI_PANEL_EN_GPIO 199
static struct gpio omap3_evm_dss_gpios[] __initdata = {
{ OMAP3EVM_LCD_PANEL_RESB, GPIOF_OUT_INIT_HIGH, "lcd_panel_resb" },
{ OMAP3EVM_LCD_PANEL_INI, GPIOF_OUT_INIT_HIGH, "lcd_panel_ini" },
{ OMAP3EVM_LCD_PANEL_QVGA, GPIOF_OUT_INIT_LOW, "lcd_panel_qvga" },
{ OMAP3EVM_LCD_PANEL_LR, GPIOF_OUT_INIT_HIGH, "lcd_panel_lr" },
{ OMAP3EVM_LCD_PANEL_UD, GPIOF_OUT_INIT_HIGH, "lcd_panel_ud" },
{ OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW, "lcd_panel_envdd" },
static struct panel_sharp_ls037v7dw01_data omap3_evm_lcd_data = {
.resb_gpio = OMAP3EVM_LCD_PANEL_RESB,
.ini_gpio = OMAP3EVM_LCD_PANEL_INI,
.mo_gpio = OMAP3EVM_LCD_PANEL_QVGA,
.lr_gpio = OMAP3EVM_LCD_PANEL_LR,
.ud_gpio = OMAP3EVM_LCD_PANEL_UD,
};
static int lcd_enabled;
static int dvi_enabled;
static void __init omap3_evm_display_init(void)
{
int r;
r = gpio_request_array(omap3_evm_dss_gpios,
ARRAY_SIZE(omap3_evm_dss_gpios));
r = gpio_request_one(OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW,
"lcd_panel_envdd");
if (r)
printk(KERN_ERR "failed to get lcd_panel_* gpios\n");
}
pr_err("failed to get lcd_panel_envdd GPIO\n");
static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
{
if (dvi_enabled) {
printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
return -EINVAL;
}
gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
r = gpio_request_one(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO,
GPIOF_OUT_INIT_LOW, "lcd_panel_bklight");
if (r)
pr_err("failed to get lcd_panel_bklight GPIO\n");
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
else
gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
lcd_enabled = 1;
return 0;
}
static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
{
gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
else
gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
lcd_enabled = 0;
}
static struct omap_dss_device omap3_evm_lcd_device = {
@ -217,26 +199,14 @@ static struct omap_dss_device omap3_evm_lcd_device = {
.driver_name = "sharp_ls_panel",
.type = OMAP_DISPLAY_TYPE_DPI,
.phy.dpi.data_lines = 18,
.platform_enable = omap3_evm_enable_lcd,
.platform_disable = omap3_evm_disable_lcd,
.data = &omap3_evm_lcd_data,
};
static int omap3_evm_enable_tv(struct omap_dss_device *dssdev)
{
return 0;
}
static void omap3_evm_disable_tv(struct omap_dss_device *dssdev)
{
}
static struct omap_dss_device omap3_evm_tv_device = {
.name = "tv",
.driver_name = "venc",
.type = OMAP_DISPLAY_TYPE_VENC,
.phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
.platform_enable = omap3_evm_enable_tv,
.platform_disable = omap3_evm_disable_tv,
};
static struct tfp410_platform_data dvi_panel = {

7
arch/arm/mach-omap2/board-omap3pandora.c
View file

@ -44,6 +44,7 @@
#include "common.h"
#include <video/omapdss.h>
#include <video/omap-panel-data.h>
#include <linux/platform_data/mtd-nand-omap2.h>
#include "mux.h"
@ -230,12 +231,16 @@ static struct twl4030_keypad_data pandora_kp_data = {
.rep = 1,
};
static struct panel_tpo_td043_data lcd_data = {
.nreset_gpio = 157,
};
static struct omap_dss_device pandora_lcd_device = {
.name = "lcd",
.driver_name = "tpo_td043mtea1_panel",
.type = OMAP_DISPLAY_TYPE_DPI,
.phy.dpi.data_lines = 24,
.reset_gpio = 157,
.data = &lcd_data,
};
static struct omap_dss_device pandora_tv_device = {

11
arch/arm/mach-omap2/board-omap3stalker.c
View file

@ -94,15 +94,6 @@ static void __init omap3_stalker_display_init(void)
return;
}
static int omap3_stalker_enable_tv(struct omap_dss_device *dssdev)
{
return 0;
}
static void omap3_stalker_disable_tv(struct omap_dss_device *dssdev)
{
}
static struct omap_dss_device omap3_stalker_tv_device = {
.name = "tv",
.driver_name = "venc",
@ -112,8 +103,6 @@ static struct omap_dss_device omap3_stalker_tv_device = {
#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE)
.u.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE,
#endif
.platform_enable = omap3_stalker_enable_tv,
.platform_disable = omap3_stalker_disable_tv,
};
static struct tfp410_platform_data dvi_panel = {

2
arch/arm/mach-omap2/board-omap4panda.c
View file

@ -435,7 +435,7 @@ static void __init omap4_panda_init(void)
omap_sdrc_init(NULL, NULL);
omap4_twl6030_hsmmc_init(mmc);
omap4_ehci_init();
usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
usb_musb_init(&musb_board_data);
omap4_panda_display_init();
}

58
arch/arm/mach-omap2/board-overo.c
View file

@ -145,28 +145,9 @@ static inline void __init overo_init_smsc911x(void) { return; }
#endif
/* DSS */
static int lcd_enabled;
static int dvi_enabled;
#define OVERO_GPIO_LCD_EN 144
#define OVERO_GPIO_LCD_BL 145
static struct gpio overo_dss_gpios[] __initdata = {
{ OVERO_GPIO_LCD_EN, GPIOF_OUT_INIT_HIGH, "OVERO_GPIO_LCD_EN" },
{ OVERO_GPIO_LCD_BL, GPIOF_OUT_INIT_HIGH, "OVERO_GPIO_LCD_BL" },
};
static void __init overo_display_init(void)
{
if (gpio_request_array(overo_dss_gpios, ARRAY_SIZE(overo_dss_gpios))) {
printk(KERN_ERR "could not obtain DSS control GPIOs\n");
return;
}
gpio_export(OVERO_GPIO_LCD_EN, 0);
gpio_export(OVERO_GPIO_LCD_BL, 0);
}
static struct tfp410_platform_data dvi_panel = {
.i2c_bus_num = 3,
.power_down_gpio = -1,
@ -187,30 +168,13 @@ static struct omap_dss_device overo_tv_device = {
.phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
};
static int overo_panel_enable_lcd(struct omap_dss_device *dssdev)
{
if (dvi_enabled) {
printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
return -EINVAL;
}
gpio_set_value(OVERO_GPIO_LCD_EN, 1);
gpio_set_value(OVERO_GPIO_LCD_BL, 1);
lcd_enabled = 1;
return 0;
}
static void overo_panel_disable_lcd(struct omap_dss_device *dssdev)
{
gpio_set_value(OVERO_GPIO_LCD_EN, 0);
gpio_set_value(OVERO_GPIO_LCD_BL, 0);
lcd_enabled = 0;
}
static struct panel_generic_dpi_data lcd43_panel = {
.name = "samsung_lte430wq_f0c",
.platform_enable = overo_panel_enable_lcd,
.platform_disable = overo_panel_disable_lcd,
.num_gpios = 2,
.gpios = {
OVERO_GPIO_LCD_EN,
OVERO_GPIO_LCD_BL
},
};
static struct omap_dss_device overo_lcd43_device = {
@ -223,13 +187,20 @@ static struct omap_dss_device overo_lcd43_device = {
#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \
defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE)
static struct panel_generic_dpi_data lcd35_panel = {
.num_gpios = 2,
.gpios = {
OVERO_GPIO_LCD_EN,
OVERO_GPIO_LCD_BL
},
};
static struct omap_dss_device overo_lcd35_device = {
.type = OMAP_DISPLAY_TYPE_DPI,
.name = "lcd35",
.driver_name = "lgphilips_lb035q02_panel",
.phy.dpi.data_lines = 24,
.platform_enable = overo_panel_enable_lcd,
.platform_disable = overo_panel_disable_lcd,
.data = &lcd35_panel,
};
#endif
@ -508,7 +479,6 @@ static void __init overo_init(void)
usbhs_init(&usbhs_bdata);
overo_spi_init();
overo_init_smsc911x();
overo_display_init();
overo_init_led();
overo_init_keys();
omap_twl4030_audio_init("overo", NULL);

26
arch/arm/mach-omap2/board-rx51-video.c
View file

@ -16,6 +16,8 @@
#include <linux/mm.h>
#include <asm/mach-types.h>
#include <video/omapdss.h>
#include <video/omap-panel-data.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include "soc.h"
@ -27,25 +29,16 @@
#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
static int rx51_lcd_enable(struct omap_dss_device *dssdev)
{
gpio_set_value(dssdev->reset_gpio, 1);
return 0;
}
static void rx51_lcd_disable(struct omap_dss_device *dssdev)
{
gpio_set_value(dssdev->reset_gpio, 0);
}
static struct panel_acx565akm_data lcd_data = {
.reset_gpio = RX51_LCD_RESET_GPIO,
};
static struct omap_dss_device rx51_lcd_device = {
.name = "lcd",
.driver_name = "panel-acx565akm",
.type = OMAP_DISPLAY_TYPE_SDI,
.phy.sdi.datapairs = 2,
.reset_gpio = RX51_LCD_RESET_GPIO,
.platform_enable = rx51_lcd_enable,
.platform_disable = rx51_lcd_disable,
.data = &lcd_data,
};
static struct omap_dss_device rx51_tv_device = {
@ -76,13 +69,8 @@ static int __init rx51_video_init(void)
return 0;
}
if (gpio_request_one(RX51_LCD_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
"LCD ACX565AKM reset")) {
pr_err("%s failed to get LCD Reset GPIO\n", __func__);
return 0;
}
omap_display_init(&rx51_dss_board_info);
return 0;
}

38
arch/arm/mach-omap2/board-zoom-display.c
View file

@ -15,8 +15,9 @@
#include <linux/spi/spi.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <video/omapdss.h>
#include "board-zoom.h"
#include <video/omap-panel-data.h>
#include "board-zoom.h"
#include "soc.h"
#include "common.h"
@ -24,37 +25,17 @@
#define LCD_PANEL_RESET_GPIO_PILOT 55
#define LCD_PANEL_QVGA_GPIO 56
static struct gpio zoom_lcd_gpios[] __initdata = {
{ -EINVAL, GPIOF_OUT_INIT_HIGH, "lcd reset" },
{ LCD_PANEL_QVGA_GPIO, GPIOF_OUT_INIT_HIGH, "lcd qvga" },
static struct panel_nec_nl8048_data zoom_lcd_data = {
/* res_gpio filled in code */
.qvga_gpio = LCD_PANEL_QVGA_GPIO,
};
static void __init zoom_lcd_panel_init(void)
{
zoom_lcd_gpios[0].gpio = (omap_rev() > OMAP3430_REV_ES3_0) ?
LCD_PANEL_RESET_GPIO_PROD :
LCD_PANEL_RESET_GPIO_PILOT;
if (gpio_request_array(zoom_lcd_gpios, ARRAY_SIZE(zoom_lcd_gpios)))
pr_err("%s: Failed to get LCD GPIOs.\n", __func__);
}
static int zoom_panel_enable_lcd(struct omap_dss_device *dssdev)
{
return 0;
}
static void zoom_panel_disable_lcd(struct omap_dss_device *dssdev)
{
}
static struct omap_dss_device zoom_lcd_device = {
.name = "lcd",
.driver_name = "NEC_8048_panel",
.type = OMAP_DISPLAY_TYPE_DPI,
.phy.dpi.data_lines = 24,
.platform_enable = zoom_panel_enable_lcd,
.platform_disable = zoom_panel_disable_lcd,
.data = &zoom_lcd_data,
};
static struct omap_dss_device *zoom_dss_devices[] = {
@ -67,6 +48,13 @@ static struct omap_dss_board_info zoom_dss_data = {
.default_device = &zoom_lcd_device,
};
static void __init zoom_lcd_panel_init(void)
{
zoom_lcd_data.res_gpio = (omap_rev() > OMAP3430_REV_ES3_0) ?
LCD_PANEL_RESET_GPIO_PROD :
LCD_PANEL_RESET_GPIO_PILOT;
}
static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
.turbo_mode = 1,
};

54
arch/arm/mach-omap2/dss-common.c
View file

@ -52,7 +52,6 @@ static struct omap_dss_device omap4_panda_dvi_device = {
.driver_name = "tfp410",
.data = &omap4_dvi_panel,
.phy.dpi.data_lines = 24,
.reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
.channel = OMAP_DSS_CHANNEL_LCD2,
};
@ -177,45 +176,12 @@ static struct picodlp_panel_data sdp4430_picodlp_pdata = {
.pwrgood_gpio = 45,
};
static void sdp4430_picodlp_init(void)
{
int r;
const struct gpio picodlp_gpios[] = {
{DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
"DLP POWER ON"},
{sdp4430_picodlp_pdata.emu_done_gpio, GPIOF_IN,
"DLP EMU DONE"},
{sdp4430_picodlp_pdata.pwrgood_gpio, GPIOF_OUT_INIT_LOW,
"DLP PWRGOOD"},
};
r = gpio_request_array(picodlp_gpios, ARRAY_SIZE(picodlp_gpios));
if (r)
pr_err("Cannot request PicoDLP GPIOs, error %d\n", r);
}
static int sdp4430_panel_enable_picodlp(struct omap_dss_device *dssdev)
{
gpio_set_value(DISPLAY_SEL_GPIO, 0);
gpio_set_value(DLP_POWER_ON_GPIO, 1);
return 0;
}
static void sdp4430_panel_disable_picodlp(struct omap_dss_device *dssdev)
{
gpio_set_value(DLP_POWER_ON_GPIO, 0);
gpio_set_value(DISPLAY_SEL_GPIO, 1);
}
static struct omap_dss_device sdp4430_picodlp_device = {
.name = "picodlp",
.driver_name = "picodlp_panel",
.type = OMAP_DISPLAY_TYPE_DPI,
.phy.dpi.data_lines = 24,
.channel = OMAP_DSS_CHANNEL_LCD2,
.platform_enable = sdp4430_panel_enable_picodlp,
.platform_disable = sdp4430_panel_disable_picodlp,
.data = &sdp4430_picodlp_pdata,
};
@ -232,17 +198,26 @@ static struct omap_dss_board_info sdp4430_dss_data = {
.default_device = &sdp4430_lcd_device,
};
/*
* we select LCD2 by default (instead of Pico DLP) by setting DISPLAY_SEL_GPIO.
* Setting DLP_POWER_ON gpio enables the VDLP_2V5 VDLP_1V8 and VDLP_1V0 rails
* used by picodlp on the 4430sdp platform. Keep this gpio disabled as LCD2 is
* selected by default
*/
void __init omap_4430sdp_display_init(void)
{
int r;
/* Enable LCD2 by default (instead of Pico DLP) */
r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
"display_sel");
if (r)
pr_err("%s: Could not get display_sel GPIO\n", __func__);
sdp4430_picodlp_init();
r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
"DLP POWER ON");
if (r)
pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__);
omap_display_init(&sdp4430_dss_data);
/*
* OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
@ -262,12 +237,15 @@ void __init omap_4430sdp_display_init_of(void)
{
int r;
/* Enable LCD2 by default (instead of Pico DLP) */
r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
"display_sel");
if (r)
pr_err("%s: Could not get display_sel GPIO\n", __func__);
sdp4430_picodlp_init();
r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
"DLP POWER ON");
if (r)
pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__);
omap_display_init(&sdp4430_dss_data);
}

7
arch/arm/mach-omap2/timer.c
View file

@ -46,7 +46,6 @@
#include <asm/smp_twd.h>
#include <asm/sched_clock.h>
#include <asm/arch_timer.h>
#include "omap_hwmod.h"
#include "omap_device.h"
#include <plat/counter-32k.h>
@ -627,14 +626,10 @@ void __init omap4_local_timer_init(void)
#ifdef CONFIG_SOC_OMAP5
void __init omap5_realtime_timer_init(void)
{
int err;
omap4_sync32k_timer_init();
realtime_counter_init();
err = arch_timer_of_register();
if (err)
pr_err("%s: arch_timer_register failed %d\n", __func__, err);
clocksource_of_init();
}
#endif /* CONFIG_SOC_OMAP5 */

1
arch/arm/mach-shmobile/board-kzm9d.c
View file

@ -90,6 +90,5 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d")
.init_irq = emev2_init_irq,
.init_machine = kzm9d_add_standard_devices,
.init_late = shmobile_init_late,
.init_time = shmobile_timer_init,
.dt_compat = kzm9d_boards_compat_dt,
MACHINE_END

1
arch/arm/mach-shmobile/setup-emev2.c
View file

@ -456,7 +456,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
.nr_irqs = NR_IRQS_LEGACY,
.init_irq = irqchip_init,
.init_machine = emev2_add_standard_devices_dt,
.init_time = shmobile_timer_init,
.dt_compat = emev2_boards_compat_dt,
MACHINE_END

1
arch/arm/mach-shmobile/setup-r8a7740.c
View file

@ -1030,7 +1030,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
.init_early = r8a7740_add_early_devices_dt,
.init_irq = r8a7740_init_irq,
.init_machine = r8a7740_add_standard_devices_dt,
.init_time = shmobile_timer_init,
.dt_compat = r8a7740_boards_compat_dt,
MACHINE_END

1
arch/arm/mach-shmobile/setup-sh7372.c
View file

@ -1175,7 +1175,6 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
.init_irq = sh7372_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = sh7372_add_standard_devices_dt,
.init_time = shmobile_timer_init,
.dt_compat = sh7372_boards_compat_dt,
MACHINE_END

1
arch/arm/mach-shmobile/setup-sh73a0.c
View file

@ -1037,7 +1037,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
.nr_irqs = NR_IRQS_LEGACY,
.init_irq = irqchip_init,
.init_machine = sh73a0_add_standard_devices_dt,
.init_time = shmobile_timer_init,
.dt_compat = sh73a0_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */

7
arch/arm/mach-shmobile/timer.c
View file

@ -19,10 +19,8 @@
*
*/
#include <linux/platform_device.h>
#include <linux/clocksource.h>
#include <linux/delay.h>
#include <asm/arch_timer.h>
#include <asm/mach/time.h>
#include <asm/smp_twd.h>
void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
unsigned int mult, unsigned int div)
@ -63,6 +61,5 @@ void __init shmobile_earlytimer_init(void)
void __init shmobile_timer_init(void)
{
arch_timer_of_register();
arch_timer_sched_clock_init();
clocksource_of_init();
}

6
arch/arm/mach-spear/Makefile
View file

@ -7,10 +7,10 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
# Common support
obj-y := restart.o time.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
smp-$(CONFIG_SMP) += headsmp.o platsmp.o
smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o
obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o $(smp-y)
obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o
obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o

5
arch/arm/mach-spear/generic.h
View file

@ -22,11 +22,6 @@ extern void spear13xx_timer_init(void);
extern void spear3xx_timer_init(void);
extern struct pl022_ssp_controller pl022_plat_data;
extern struct pl08x_platform_data pl080_plat_data;
extern struct dw_dma_platform_data dmac_plat_data;
extern struct dw_dma_slave cf_dma_priv;
extern struct dw_dma_slave nand_read_dma_priv;
extern struct dw_dma_slave nand_write_dma_priv;
bool dw_dma_filter(struct dma_chan *chan, void *slave);
void __init spear_setup_of_timer(void);
void __init spear3xx_clk_init(void __iomem *misc_base,

2
arch/arm/mach-spear/include/mach/spear.h
View file

@ -82,8 +82,6 @@
#define VA_L2CC_BASE IOMEM(UL(0xFB000000))
/* others */
#define DMAC0_BASE UL(0xEA800000)
#define DMAC1_BASE UL(0xEB000000)
#define MCIF_CF_BASE UL(0xB2800000)
/* Debug uart for linux, will be used for debug and uncompress messages */

30
arch/arm/mach-spear/spear1310.c
View file

@ -23,40 +23,12 @@
#include <mach/spear.h>
/* Base addresses */
#define SPEAR1310_SSP1_BASE UL(0x5D400000)
#define SPEAR1310_SATA0_BASE UL(0xB1000000)
#define SPEAR1310_SATA1_BASE UL(0xB1800000)
#define SPEAR1310_SATA2_BASE UL(0xB4000000)
#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
static struct arasan_cf_pdata cf_pdata = {
.cf_if_clk = CF_IF_CLK_166M,
.quirk = CF_BROKEN_UDMA,
.dma_priv = &cf_dma_priv,
};
/* ssp device registration */
static struct pl022_ssp_controller ssp1_plat_data = {
.enable_dma = 0,
};
/* Add SPEAr1310 auxdata to pass platform data */
static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data),
{}
};
static void __init spear1310_dt_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table,
spear1310_auxdata_lookup, NULL);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const spear1310_dt_board_compat[] = {

32
arch/arm/mach-spear/spear1340.c
View file

@ -16,18 +16,16 @@
#include <linux/ahci_platform.h>
#include <linux/amba/serial.h>
#include <linux/delay.h>
#include <linux/dw_dmac.h>
#include <linux/of_platform.h>
#include <linux/irqchip.h>
#include <asm/mach/arch.h>
#include "generic.h"
#include <mach/spear.h>
#include "spear13xx-dma.h"
/* FIXME: Move SATA PHY code into a standalone driver */
/* Base addresses */
#define SPEAR1340_SATA_BASE UL(0xB1000000)
#define SPEAR1340_UART1_BASE UL(0xB4100000)
/* Power Management Registers */
#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
@ -79,28 +77,6 @@
(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
static struct dw_dma_slave uart1_dma_param[] = {
{
/* Tx */
.cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX),
.cfg_lo = 0,
.src_master = DMA_MASTER_MEMORY,
.dst_master = SPEAR1340_DMA_MASTER_UART1,
}, {
/* Rx */
.cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX),
.cfg_lo = 0,
.src_master = SPEAR1340_DMA_MASTER_UART1,
.dst_master = DMA_MASTER_MEMORY,
}
};
static struct amba_pl011_data uart1_data = {
.dma_filter = dw_dma_filter,
.dma_tx_param = &uart1_dma_param[0],
.dma_rx_param = &uart1_dma_param[1],
};
/* SATA device registration */
static int sata_miphy_init(struct device *dev, void __iomem *addr)
{
@ -159,14 +135,8 @@ static struct ahci_platform_data sata_pdata = {
/* Add SPEAr1340 auxdata to pass platform data */
static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
&sata_pdata),
OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data),
{}
};

128
arch/arm/mach-spear/spear13xx-dma.h
View file

@ -1,128 +0,0 @@
/*
* arch/arm/mach-spear13xx/include/mach/dma.h
*
* DMA information for SPEAr13xx machine family
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.linux@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* request id of all the peripherals */
enum dma_master_info {
/* Accessible from only one master */
DMA_MASTER_MCIF = 0,
DMA_MASTER_FSMC = 1,
/* Accessible from both 0 & 1 */
DMA_MASTER_MEMORY = 0,
DMA_MASTER_ADC = 0,
DMA_MASTER_UART0 = 0,
DMA_MASTER_SSP0 = 0,
DMA_MASTER_I2C0 = 0,
#ifdef CONFIG_MACH_SPEAR1310
/* Accessible from only one master */
SPEAR1310_DMA_MASTER_JPEG = 1,
/* Accessible from both 0 & 1 */
SPEAR1310_DMA_MASTER_I2S = 0,
SPEAR1310_DMA_MASTER_UART1 = 0,
SPEAR1310_DMA_MASTER_UART2 = 0,
SPEAR1310_DMA_MASTER_UART3 = 0,
SPEAR1310_DMA_MASTER_UART4 = 0,
SPEAR1310_DMA_MASTER_UART5 = 0,
SPEAR1310_DMA_MASTER_I2C1 = 0,
SPEAR1310_DMA_MASTER_I2C2 = 0,
SPEAR1310_DMA_MASTER_I2C3 = 0,
SPEAR1310_DMA_MASTER_I2C4 = 0,
SPEAR1310_DMA_MASTER_I2C5 = 0,
SPEAR1310_DMA_MASTER_I2C6 = 0,
SPEAR1310_DMA_MASTER_I2C7 = 0,
SPEAR1310_DMA_MASTER_SSP1 = 0,
#endif
#ifdef CONFIG_MACH_SPEAR1340
/* Accessible from only one master */
SPEAR1340_DMA_MASTER_I2S_PLAY = 1,
SPEAR1340_DMA_MASTER_I2S_REC = 1,
SPEAR1340_DMA_MASTER_I2C1 = 1,
SPEAR1340_DMA_MASTER_UART1 = 1,
/* following are accessible from both master 0 & 1 */
SPEAR1340_DMA_MASTER_SPDIF = 0,
SPEAR1340_DMA_MASTER_CAM = 1,
SPEAR1340_DMA_MASTER_VIDEO_IN = 0,
SPEAR1340_DMA_MASTER_MALI = 0,
#endif
};
enum request_id {
DMA_REQ_ADC = 0,
DMA_REQ_SSP0_TX = 4,
DMA_REQ_SSP0_RX = 5,
DMA_REQ_UART0_TX = 6,
DMA_REQ_UART0_RX = 7,
DMA_REQ_I2C0_TX = 8,
DMA_REQ_I2C0_RX = 9,
#ifdef CONFIG_MACH_SPEAR1310
SPEAR1310_DMA_REQ_FROM_JPEG = 2,
SPEAR1310_DMA_REQ_TO_JPEG = 3,
SPEAR1310_DMA_REQ_I2S_TX = 10,
SPEAR1310_DMA_REQ_I2S_RX = 11,
SPEAR1310_DMA_REQ_I2C1_RX = 0,
SPEAR1310_DMA_REQ_I2C1_TX = 1,
SPEAR1310_DMA_REQ_I2C2_RX = 2,
SPEAR1310_DMA_REQ_I2C2_TX = 3,
SPEAR1310_DMA_REQ_I2C3_RX = 4,
SPEAR1310_DMA_REQ_I2C3_TX = 5,
SPEAR1310_DMA_REQ_I2C4_RX = 6,
SPEAR1310_DMA_REQ_I2C4_TX = 7,
SPEAR1310_DMA_REQ_I2C5_RX = 8,
SPEAR1310_DMA_REQ_I2C5_TX = 9,
SPEAR1310_DMA_REQ_I2C6_RX = 10,
SPEAR1310_DMA_REQ_I2C6_TX = 11,
SPEAR1310_DMA_REQ_UART1_RX = 12,
SPEAR1310_DMA_REQ_UART1_TX = 13,
SPEAR1310_DMA_REQ_UART2_RX = 14,
SPEAR1310_DMA_REQ_UART2_TX = 15,
SPEAR1310_DMA_REQ_UART5_RX = 16,
SPEAR1310_DMA_REQ_UART5_TX = 17,
SPEAR1310_DMA_REQ_SSP1_RX = 18,
SPEAR1310_DMA_REQ_SSP1_TX = 19,
SPEAR1310_DMA_REQ_I2C7_RX = 20,
SPEAR1310_DMA_REQ_I2C7_TX = 21,
SPEAR1310_DMA_REQ_UART3_RX = 28,
SPEAR1310_DMA_REQ_UART3_TX = 29,
SPEAR1310_DMA_REQ_UART4_RX = 30,
SPEAR1310_DMA_REQ_UART4_TX = 31,
#endif
#ifdef CONFIG_MACH_SPEAR1340
SPEAR1340_DMA_REQ_SPDIF_TX = 2,
SPEAR1340_DMA_REQ_SPDIF_RX = 3,
SPEAR1340_DMA_REQ_I2S_TX = 10,
SPEAR1340_DMA_REQ_I2S_RX = 11,
SPEAR1340_DMA_REQ_UART1_TX = 12,
SPEAR1340_DMA_REQ_UART1_RX = 13,
SPEAR1340_DMA_REQ_I2C1_TX = 14,
SPEAR1340_DMA_REQ_I2C1_RX = 15,
SPEAR1340_DMA_REQ_CAM0_EVEN = 0,
SPEAR1340_DMA_REQ_CAM0_ODD = 1,
SPEAR1340_DMA_REQ_CAM1_EVEN = 2,
SPEAR1340_DMA_REQ_CAM1_ODD = 3,
SPEAR1340_DMA_REQ_CAM2_EVEN = 4,
SPEAR1340_DMA_REQ_CAM2_ODD = 5,
SPEAR1340_DMA_REQ_CAM3_EVEN = 6,
SPEAR1340_DMA_REQ_CAM3_ODD = 7,
#endif
};
#endif /* __MACH_DMA_H */

60
arch/arm/mach-spear/spear13xx.c
View file

@ -16,70 +16,12 @@
#include <linux/amba/pl022.h>
#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/dw_dmac.h>
#include <linux/err.h>
#include <linux/of.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include "generic.h"
#include <mach/spear.h>
#include "spear13xx-dma.h"
/* common dw_dma filter routine to be used by peripherals */
bool dw_dma_filter(struct dma_chan *chan, void *slave)
{
struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
if (chan->device->dev == dws->dma_dev) {
chan->private = slave;
return true;
} else {
return false;
}
}
/* ssp device registration */
static struct dw_dma_slave ssp_dma_param[] = {
{
/* Tx */
.cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
.cfg_lo = 0,
.src_master = DMA_MASTER_MEMORY,
.dst_master = DMA_MASTER_SSP0,
}, {
/* Rx */
.cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
.cfg_lo = 0,
.src_master = DMA_MASTER_SSP0,
.dst_master = DMA_MASTER_MEMORY,
}
};
struct pl022_ssp_controller pl022_plat_data = {
.enable_dma = 1,
.dma_filter = dw_dma_filter,
.dma_rx_param = &ssp_dma_param[1],
.dma_tx_param = &ssp_dma_param[0],
};
/* CF device registration */
struct dw_dma_slave cf_dma_priv = {
.cfg_hi = 0,
.cfg_lo = 0,
.src_master = 0,
.dst_master = 0,
};
/* dmac device registeration */
struct dw_dma_platform_data dmac_plat_data = {
.nr_channels = 8,
.chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
.chan_priority = CHAN_PRIORITY_DESCENDING,
.block_size = 4095U,
.nr_masters = 2,
.data_width = { 3, 3, 0, 0 },
};
#include "generic.h"
void __init spear13xx_l2x0_init(void)
{

26
arch/arm/mach-versatile/core.c
View file

@ -749,12 +749,25 @@ void versatile_restart(char mode, const char *cmd)
/* Early initializations */
void __init versatile_init_early(void)
{
u32 val;
void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
/*
* set clock frequency:
* VERSATILE_REFCLK is 32KHz
* VERSATILE_TIMCLK is 1MHz
*/
val = readl(__io_address(VERSATILE_SCTL_BASE));
writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
__io_address(VERSATILE_SCTL_BASE));
}
void __init versatile_init(void)
@ -785,19 +798,6 @@ void __init versatile_init(void)
*/
void __init versatile_timer_init(void)
{
u32 val;
/*
* set clock frequency:
* VERSATILE_REFCLK is 32KHz
* VERSATILE_TIMCLK is 1MHz
*/
val = readl(__io_address(VERSATILE_SCTL_BASE));
writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
__io_address(VERSATILE_SCTL_BASE));
/*
* Initialise to a known state (all timers off)

1
arch/arm/mach-versatile/versatile_dt.c
View file

@ -45,7 +45,6 @@ DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
.map_io = versatile_map_io,
.init_early = versatile_init_early,
.init_irq = versatile_init_irq,
.init_time = versatile_timer_init,
.init_machine = versatile_dt_init,
.dt_compat = versatile_dt_match,
.restart = versatile_restart,

25
arch/arm/mach-vexpress/v2m.c
View file

@ -1,6 +1,7 @@
/*
* Versatile Express V2M Motherboard Support
*/
#include <linux/clocksource.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/mmci.h>
@ -25,7 +26,6 @@
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <asm/arch_timer.h>
#include <asm/mach-types.h>
#include <asm/sizes.h>
#include <asm/mach/arch.h>
@ -63,9 +63,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
if (WARN_ON(!base || irq == NO_IRQ))
return;
writel(0, base + TIMER_1_BASE + TIMER_CTRL);
writel(0, base + TIMER_2_BASE + TIMER_CTRL);
sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
}
@ -430,29 +427,11 @@ void __init v2m_dt_init_early(void)
static void __init v2m_dt_timer_init(void)
{
struct device_node *node = NULL;
of_clk_init(NULL);
clocksource_of_init();
do {
node = of_find_compatible_node(node, NULL, "arm,sp804");
} while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB);
if (node) {
pr_info("Using SP804 '%s' as a clock & events source\n",
node->full_name);
WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
"timclken1"), "v2m-timer0", "sp804"));
WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
"timclken2"), "v2m-timer1", "sp804"));
v2m_sp804_init(of_iomap(node, 0),
irq_of_parse_and_map(node, 0));
}
arch_timer_of_register();
if (arch_timer_sched_clock_init() != 0)
versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
24000000);
}

9
arch/arm/mach-virt/virt.c
View file

@ -23,21 +23,13 @@
#include <linux/of_platform.h>
#include <linux/smp.h>
#include <asm/arch_timer.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
static void __init virt_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static void __init virt_timer_init(void)
{
WARN_ON(arch_timer_of_register() != 0);
WARN_ON(arch_timer_sched_clock_init() != 0);
}
static const char *virt_dt_match[] = {
"linux,dummy-virt",
NULL
@ -47,7 +39,6 @@ extern struct smp_operations virt_smp_ops;
DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
.init_irq = irqchip_init,
.init_time = virt_timer_init,
.init_machine = virt_init,
.smp = smp_ops(virt_smp_ops),
.dt_compat = virt_dt_match,