From 65f975619b0245fca0a3e7bb294e47b583e669b2 Mon Sep 17 00:00:00 2001
From: Elliot Berman <eberman@codeaurora.org>
Date: Mon, 22 Jul 2019 10:18:00 -0700
Subject: [PATCH] arm64: Apply erratum 1024718 to Cortex A55 r2p0

Add Cortex A55 r2p0 MIDR value to list of CPUs that impacted by erratum
1024718.

Change-Id: Ida842a099fcd892c84db28ab6a92728d2303d21b
Signed-off-by: Elliot Berman <eberman@codeaurora.org>
---
 arch/arm64/kernel/cpufeature.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index aabdabf52fdb..83eeed1eb662 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1080,7 +1080,7 @@ static bool cpu_has_broken_dbm(void)
 	/* List of CPUs which have broken DBM support. */
 	static const struct midr_range cpus[] = {
 #ifdef CONFIG_ARM64_ERRATUM_1024718
-		MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
+		MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),  // A55 r0p0 -r2p0
 #endif
 		{},
 	};