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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge "asoc: codecs: Add support for setting ear gain ctl"
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1c6384b3b9
1 changed files with 97 additions and 6 deletions
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@ -131,10 +131,6 @@ static int wcd937x_init_reg(struct snd_soc_component *component)
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0xFF, 0x3A);
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snd_soc_component_update_bits(component, WCD937X_RX_OCP_CTL,
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0x0F, 0x02);
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snd_soc_component_update_bits(component, WCD937X_HPH_R_TEST,
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0x01, 0x01);
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snd_soc_component_update_bits(component, WCD937X_HPH_L_TEST,
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0x01, 0x01);
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return 0;
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}
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@ -677,6 +673,8 @@ static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
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snd_soc_component_update_bits(component,
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WCD937X_HPH_NEW_INT_HPH_TIMER1,
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0x02, 0x02);
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snd_soc_component_update_bits(component,
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WCD937X_HPH_R_TEST, 0x01, 0x01);
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if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
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snd_soc_component_update_bits(component,
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WCD937X_ANA_RX_SUPPLIES,
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@ -687,6 +685,8 @@ static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
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(WCD_RX2 << 0x10));
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break;
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case SND_SOC_DAPM_PRE_PMD:
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snd_soc_component_update_bits(component,
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WCD937X_HPH_R_TEST, 0x01, 0x00);
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if (wcd937x->update_wcd_event)
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wcd937x->update_wcd_event(wcd937x->handle,
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WCD_BOLERO_EVT_RX_MUTE,
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@ -694,9 +694,22 @@ static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
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blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
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WCD_EVENT_PRE_HPHR_PA_OFF,
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&wcd937x->mbhc->wcd_mbhc);
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set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
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break;
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case SND_SOC_DAPM_POST_PMD:
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usleep_range(7000, 7010);
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/*
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* 7ms sleep is required after PA is disabled as per
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* HW requirement. If compander is disabled, then
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* 20ms delay is required.
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*/
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if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
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if (!wcd937x->comp2_enable)
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usleep_range(20000, 20100);
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else
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usleep_range(7000, 7100);
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clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
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}
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snd_soc_component_update_bits(component,
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WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
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blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
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@ -759,6 +772,8 @@ static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
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snd_soc_component_update_bits(component,
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WCD937X_HPH_NEW_INT_HPH_TIMER1,
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0x02, 0x02);
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snd_soc_component_update_bits(component,
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WCD937X_HPH_L_TEST, 0x01, 0x01);
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if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
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snd_soc_component_update_bits(component,
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WCD937X_ANA_RX_SUPPLIES,
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@ -769,6 +784,8 @@ static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
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(WCD_RX1 << 0x10));
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break;
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case SND_SOC_DAPM_PRE_PMD:
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snd_soc_component_update_bits(component,
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WCD937X_HPH_L_TEST, 0x01, 0x00);
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if (wcd937x->update_wcd_event)
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wcd937x->update_wcd_event(wcd937x->handle,
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WCD_BOLERO_EVT_RX_MUTE,
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@ -776,9 +793,22 @@ static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
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blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
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WCD_EVENT_PRE_HPHL_PA_OFF,
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&wcd937x->mbhc->wcd_mbhc);
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set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
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break;
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case SND_SOC_DAPM_POST_PMD:
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usleep_range(7000, 7010);
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/*
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* 7ms sleep is required after PA is disabled as per
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* HW requirement. If compander is disabled, then
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* 20ms delay is required.
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*/
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if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
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if (!wcd937x->comp1_enable)
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usleep_range(20000, 20100);
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else
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usleep_range(7000, 7100);
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clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
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}
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snd_soc_component_update_bits(component,
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WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
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blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
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@ -880,6 +910,9 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
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snd_soc_component_update_bits(component,
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WCD937X_DIGITAL_PDM_WD_CTL0,
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0x17, 0x13);
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if (!wcd937x->comp1_enable)
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snd_soc_component_update_bits(component,
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WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
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break;
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case SND_SOC_DAPM_POST_PMU:
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usleep_range(6000, 6010);
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@ -899,6 +932,9 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
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(WCD_RX1 << 0x10 | 0x1));
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break;
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case SND_SOC_DAPM_POST_PMD:
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if (!wcd937x->comp1_enable)
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snd_soc_component_update_bits(component,
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WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
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usleep_range(7000, 7010);
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wcd_cls_h_fsm(component, &wcd937x->clsh_info,
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WCD_CLSH_EVENT_POST_PA,
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@ -1565,6 +1601,48 @@ static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
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return 0;
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}
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static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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u8 ear_pa_gain = 0;
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struct snd_soc_component *component =
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snd_soc_kcontrol_component(kcontrol);
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ear_pa_gain = snd_soc_component_read32(component,
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WCD937X_ANA_EAR_COMPANDER_CTL);
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ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
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ucontrol->value.integer.value[0] = ear_pa_gain;
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dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
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ear_pa_gain);
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return 0;
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}
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static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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u8 ear_pa_gain = 0;
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struct snd_soc_component *component =
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snd_soc_kcontrol_component(kcontrol);
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struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
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dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
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__func__, ucontrol->value.integer.value[0]);
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ear_pa_gain = ucontrol->value.integer.value[0] << 2;
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if (!wcd937x->comp1_enable) {
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snd_soc_component_update_bits(component,
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WCD937X_ANA_EAR_COMPANDER_CTL,
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0x7C, ear_pa_gain);
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}
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return 0;
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}
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static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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@ -1660,11 +1738,24 @@ static const char * const rx_hph_mode_mux_text[] = {
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"CLS_H_ULP", "CLS_AB_HIFI",
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};
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static const char * const wcd937x_ear_pa_gain_text[] = {
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"G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
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"G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
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"G_M6_DB", "G_7P5_DB", "G_M9_DB",
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"G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
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"G_M15_DB", "G_M16P5_DB", "G_M18_DB",
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};
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static const struct soc_enum rx_hph_mode_mux_enum =
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SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
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rx_hph_mode_mux_text);
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static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
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wcd937x_ear_pa_gain_text);
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static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
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SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
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wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
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SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
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wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
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SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
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