techpack: dataipa: Enable Regdump for msmnile

Enable support to save regump for msmnile target.
Change-Id: I47add92e8eb82a546d4217815699fccd52b7b5b8

config/dataipa_gsi_V1.h

@@ -1,9 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
-* Copyright (c) 2020, The Linux Foundation. All rights reserved.
+* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
 */
 
 #define CONFIG_GSI 1
 #define CONFIG_RMNET_IPA3 1
 #define CONFIG_RNDIS_IPA 1
 #define CONFIG_IPA_WDI_UNIFIED_API 1
+#define CONFIG_IPA3_REGDUMP 1
+#define CONFIG_IPA3_REGDUMP_IPA_4_1 1
+#define CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS 0

config/dataipa_gsi_V1_GKI.conf

@@ -3,3 +3,5 @@ export CONFIG_IPA_CLIENTS_MANAGER=m
 export CONFIG_IPA_WDI_UNIFIED_API=y
 export CONFIG_RMNET_IPA3=y
 export CONFIG_RNDIS_IPA=m
+export CONFIG_IPA3_REGDUMP=y
+export CONFIG_IPA3_REGDUMP_IPA_4_1=y

config/dataipa_gsi_V1_QGKI.conf

@@ -3,3 +3,5 @@ export CONFIG_IPA_CLIENTS_MANAGER=y
 export CONFIG_IPA_WDI_UNIFIED_API=y
 export CONFIG_RMNET_IPA3=y
 export CONFIG_RNDIS_IPA=y
+export CONFIG_IPA3_REGDUMP=y
+export CONFIG_IPA3_REGDUMP_IPA_4_1=y

drivers/platform/msm/Makefile

@@ -57,6 +57,9 @@ ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_4_5),y m))
 LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump/ipa4.5
 endif
 
+ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_4_1),y m))
+LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump/ipa4.1
+endif
 
 obj-$(CONFIG_GSI) += gsi/
 obj-$(CONFIG_IPA3) += ipa/

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio_def.h

@@ -0,0 +1,539 @@
+/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#if !defined(_GSI_HWIO_DEF_H_)
+#define _GSI_HWIO_DEF_H_
+
+/* *****************************************************************************
+ *
+ * HWIO register definitions
+ *
+ * *****************************************************************************
+ */
+struct gsi_hwio_def_gsi_cfg_s {
+	u32	gsi_enable : 1;
+	u32	mcs_enable : 1;
+	u32	double_mcs_clk_freq : 1;
+	u32	uc_is_mcs : 1;
+	u32	gsi_pwr_clps : 1;
+	u32	bp_mtrix_disable : 1;
+	u32	reserved0 : 26;
+};
+union gsi_hwio_def_gsi_cfg_u {
+	struct gsi_hwio_def_gsi_cfg_s	def;
+	u32			value;
+};
+struct gsi_hwio_def_gsi_ree_cfg_s {
+	u32	move_to_esc_clr_mode_trsh : 1;
+	u32	reserved0 : 7;
+	u32	max_burst_size : 8;
+	u32	reserved1 : 16;
+};
+union gsi_hwio_def_gsi_ree_cfg_u {
+	struct gsi_hwio_def_gsi_ree_cfg_s	def;
+	u32				value;
+};
+struct gsi_hwio_def_gsi_manager_ee_qos_n_s {
+	u32	ee_prio : 2;
+	u32	reserved0 : 6;
+	u32	max_ch_alloc : 5;
+	u32	reserved1 : 3;
+	u32	max_ev_alloc : 5;
+	u32	reserved2 : 11;
+};
+union gsi_hwio_def_gsi_manager_ee_qos_n_u {
+	struct gsi_hwio_def_gsi_manager_ee_qos_n_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_gsi_shram_n_s {
+	u32 shram : 32;
+};
+union gsi_hwio_def_gsi_shram_n_u {
+	struct gsi_hwio_def_gsi_shram_n_s	def;
+	u32				value;
+};
+struct gsi_hwio_def_gsi_test_bus_sel_s {
+	u32	gsi_testbus_sel : 8;
+	u32	reserved0 : 8;
+	u32	gsi_hw_events_sel : 4;
+	u32	reserved1 : 12;
+};
+union gsi_hwio_def_gsi_test_bus_sel_u {
+	struct gsi_hwio_def_gsi_test_bus_sel_s	def;
+	u32				value;
+};
+struct gsi_hwio_def_gsi_test_bus_reg_s {
+	u32 gsi_testbus_reg : 32;
+};
+union gsi_hwio_def_gsi_test_bus_reg_u {
+	struct gsi_hwio_def_gsi_test_bus_reg_s	def;
+	u32				value;
+};
+struct gsi_hwio_def_gsi_debug_countern_s {
+	u32	counter_value : 16;
+	u32	reserved0 : 16;
+};
+union gsi_hwio_def_gsi_debug_countern_u {
+	struct gsi_hwio_def_gsi_debug_countern_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s {
+	u32	addr_20_0 : 21;
+	u32	write : 1;
+	u32	tid : 5;
+	u32	mid : 5;
+};
+union gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_u {
+	struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s {
+	u32 rf_reg : 32;
+};
+union gsi_hwio_def_gsi_debug_sw_rf_n_read_u {
+	struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s {
+	u32	phy_ch : 5;
+	u32	valid : 1;
+	u32	reserved0 : 26;
+};
+union gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_u {
+	struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s	def;
+	u32							value;
+};
+struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s {
+	u32	phy_ev_ch : 5;
+	u32	valid : 1;
+	u32	reserved0 : 26;
+};
+union gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_u {
+	struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s {
+	u32	chtype_protocol : 3;
+	u32	chtype_dir : 1;
+	u32	ee : 4;
+	u32	chid : 5;
+	u32	reserved0 : 1;
+	u32	erindex : 5;
+	u32	reserved1 : 1;
+	u32	chstate : 4;
+	u32	element_size : 8;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s {
+	u32	r_length : 16;
+	u32	reserved0 : 16;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s {
+	u32 r_base_addr_lsbs : 32;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s {
+	u32 r_base_addr_msbs : 32;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s {
+	u32 read_ptr_lsb : 32;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s {
+	u32 read_ptr_msb : 32;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s {
+	u32 write_ptr_lsb : 32;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s {
+	u32 write_ptr_msb : 32;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s {
+	u32	read_ptr : 16;
+	u32	reserved0 : 16;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s {
+	u32	re_intr_db : 16;
+	u32	reserved0 : 16;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s {
+	u32	wrr_weight : 4;
+	u32	reserved0 : 4;
+	u32	max_prefetch : 1;
+	u32	use_db_eng : 1;
+	u32	use_escape_buf_only : 1;
+	u32	reserved1 : 21;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_qos_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s def;
+	u32				value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s {
+	u32 scratch : 32;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s {
+	u32 scratch : 32;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s {
+	u32 scratch : 32;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s {
+	u32 scratch : 32;
+};
+union gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_u {
+	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s {
+	u32	chtype : 4;
+	u32	ee : 4;
+	u32	evchid : 8;
+	u32	intype : 1;
+	u32	reserved0 : 3;
+	u32	chstate : 4;
+	u32	element_size : 8;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s {
+	u32	r_length : 16;
+	u32	reserved0 : 16;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s {
+	u32 r_base_addr_lsbs : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s {
+	u32 r_base_addr_msbs : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s {
+	u32 read_ptr_lsb : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s {
+	u32 read_ptr_msb : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s {
+	u32 write_ptr_lsb : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s {
+	u32 write_ptr_msb : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s {
+	u32	int_modt : 16;
+	u32	int_modc : 8;
+	u32	int_mod_cnt : 8;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s {
+	u32 intvec : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s {
+	u32 msi_addr_lsb : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s {
+	u32 msi_addr_msb : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s {
+	u32 rp_update_addr_lsb : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s {
+	u32 rp_update_addr_msb : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s {
+	u32 scratch : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_scratch_0_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s {
+	u32 scratch : 32;
+};
+union gsi_hwio_def_ee_n_ev_ch_k_scratch_1_u {
+	struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_gsi_status_s {
+	u32	enabled : 1;
+	u32	reserved0 : 31;
+};
+union gsi_hwio_def_ee_n_gsi_status_u {
+	struct gsi_hwio_def_ee_n_gsi_status_s	def;
+	u32				value;
+};
+struct gsi_hwio_def_ee_n_cntxt_type_irq_s {
+	u32	ch_ctrl : 1;
+	u32	ev_ctrl : 1;
+	u32	glob_ee : 1;
+	u32	ieob : 1;
+	u32	inter_ee_ch_ctrl : 1;
+	u32	inter_ee_ev_ctrl : 1;
+	u32	general : 1;
+	u32	reserved0 : 25;
+};
+union gsi_hwio_def_ee_n_cntxt_type_irq_u {
+	struct gsi_hwio_def_ee_n_cntxt_type_irq_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s {
+	u32	ch_ctrl : 1;
+	u32	ev_ctrl : 1;
+	u32	glob_ee : 1;
+	u32	ieob : 1;
+	u32	inter_ee_ch_ctrl : 1;
+	u32	inter_ee_ev_ctrl : 1;
+	u32	general : 1;
+	u32	reserved0 : 25;
+};
+union gsi_hwio_def_ee_n_cntxt_type_irq_msk_u {
+	struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s {
+	u32 gsi_ch_bit_map : 32;
+};
+union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_u {
+	struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s {
+	u32 ev_ch_bit_map : 32;
+};
+union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_u {
+	struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s {
+	u32	gsi_ch_bit_map_msk : 17;
+	u32	reserved0 : 15;
+};
+union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_u {
+	struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s {
+	u32	ev_ch_bit_map_msk : 12;
+	u32	reserved0 : 20;
+};
+union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_u {
+	struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s {
+	u32 gsi_ch_bit_map : 32;
+};
+union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_u {
+	struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s {
+	u32 ev_ch_bit_map : 32;
+};
+union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_u {
+	struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s {
+	u32 ev_ch_bit_map : 32;
+};
+union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_u {
+	struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s {
+	u32	ev_ch_bit_map_msk : 12;
+	u32	reserved0 : 20;
+};
+union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_u {
+	struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s {
+	u32 ev_ch_bit_map : 32;
+};
+union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_u {
+	struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s {
+	u32	error_int : 1;
+	u32	gp_int1 : 1;
+	u32	gp_int2 : 1;
+	u32	gp_int3 : 1;
+	u32	reserved0 : 28;
+};
+union gsi_hwio_def_ee_n_cntxt_glob_irq_stts_u {
+	struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s {
+	u32	gsi_break_point : 1;
+	u32	gsi_bus_error : 1;
+	u32	gsi_cmd_fifo_ovrflow : 1;
+	u32	gsi_mcs_stack_ovrflow : 1;
+	u32	reserved0 : 28;
+};
+union gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_u {
+	struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_cntxt_intset_s {
+	u32	intype : 1;
+	u32	reserved0 : 31;
+};
+union gsi_hwio_def_ee_n_cntxt_intset_u {
+	struct gsi_hwio_def_ee_n_cntxt_intset_s def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s {
+	u32 msi_addr_lsb : 32;
+};
+union gsi_hwio_def_ee_n_cntxt_msi_base_lsb_u {
+	struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s {
+	u32 msi_addr_msb : 32;
+};
+union gsi_hwio_def_ee_n_cntxt_msi_base_msb_u {
+	struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s	def;
+	u32						value;
+};
+struct gsi_hwio_def_ee_n_error_log_s {
+	u32 error_log : 32;
+};
+union gsi_hwio_def_ee_n_error_log_u {
+	struct gsi_hwio_def_ee_n_error_log_s	def;
+	u32				value;
+};
+struct gsi_hwio_def_ee_n_error_log_clr_s {
+	u32 error_log_clr : 32;
+};
+union gsi_hwio_def_ee_n_error_log_clr_u {
+	struct gsi_hwio_def_ee_n_error_log_clr_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_cntxt_scratch_0_s {
+	u32 scratch : 32;
+};
+union gsi_hwio_def_ee_n_cntxt_scratch_0_u {
+	struct gsi_hwio_def_ee_n_cntxt_scratch_0_s	def;
+	u32					value;
+};
+struct gsi_hwio_def_ee_n_cntxt_scratch_1_s {
+	u32 scratch : 32;
+};
+union gsi_hwio_def_ee_n_cntxt_scratch_1_u {
+	struct gsi_hwio_def_ee_n_cntxt_scratch_1_s	def;
+	u32					value;
+};
+#endif

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_access_control.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 and only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+#if !defined(_IPA_ACCESS_CONTROL_H_)
+#define _IPA_ACCESS_CONTROL_H_
+
+#include "ipa_reg_dump.h"
+
+/*
+ * The following is target specific.
+ */
+static struct reg_mem_access_map_t mem_access_map[] = {
+	/*------------------------------------------------------------*/
+	/*      Range               Use when              Use when    */
+	/*  Begin    End           SD_ENABLED           SD_DISABLED   */
+	/*------------------------------------------------------------*/
+	{ 0x04000, 0x05000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
+	{ 0x07000, 0x0f000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
+	{ 0x05000, 0x07000, { &io_matrix[AA_COMBO], &io_matrix[AN_COMBO] } },
+	{ 0x0f000, 0x10000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } },
+	{ 0x20000, 0x24000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
+	{ 0x24000, 0x28000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
+	{ 0x28000, 0x2c000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
+	{ 0x10000, 0x11000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
+	{ 0x11000, 0x12000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
+	{ 0x12000, 0x13000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
+	{ 0x43000, 0x44000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
+	{ 0x44000, 0x45000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
+	{ 0x45000, 0x47000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
+	{ 0x40000, 0x42000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
+	{ 0x42000, 0x43000, { &io_matrix[AA_COMBO], &io_matrix[AN_COMBO] } },
+	{ 0x47000, 0x4a000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
+	{ 0x4a000, 0x5a000, { &io_matrix[AN_COMBO], &io_matrix[NN_COMBO] } },
+	{ 0x5a000, 0x5c000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } },
+	{ 0x5e000, 0x60000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
+	{ 0x60000, 0x70000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
+	{ 0x70000, 0x72000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
+	{ 0x72000, 0x80000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
+};
+
+#endif /* #if !defined(_IPA_ACCESS_CONTROL_H_) */

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio_def.h

@@ -0,0 +1,29 @@
+/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#if !defined(_IPA_GCC_HWIO_DEF_H_)
+#define _IPA_GCC_HWIO_DEF_H_
+
+/* *****************************************************************************
+ *
+ * HWIO register definitions
+ *
+ * *****************************************************************************
+ */
+struct ipa_gcc_hwio_def_gcc_ipa_bcr_s {
+	u32	blk_ares : 1;
+	u32	reserved0 : 31;
+};
+union ipa_gcc_hwio_def_gcc_ipa_bcr_u {
+	struct ipa_gcc_hwio_def_gcc_ipa_bcr_s	def;
+	u32				value;
+};
+#endif

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hw_common_ex.h

@@ -0,0 +1,610 @@
+/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#if !defined(_IPA_HW_COMMON_EX_H_)
+#define _IPA_HW_COMMON_EX_H_
+
+/* VLVL defs are available for 854 */
+#define FEATURE_VLVL_DEFS                            true
+
+/* IPAv4 version flag for Sdx24 */
+#define FEATURE_IPA_HW_VERSION_4_0                   true
+
+/* Important Platform Specific Values : IRQ_NUM, IRQ_CNT, BCR */
+#define IPA_HW_BAM_IRQ_NUM                           440
+
+/* Q6 IRQ number for IPA. Fetched from IPCatalog */
+#define IPA_HW_IRQ_NUM                               441
+
+/* Total number of different interrupts that can be enabled */
+#define IPA_HW_IRQ_CNT_TOTAL                         23
+
+/* IPAv4 BCR value */
+#define IPA_HW_BCR_REG_VAL                           0x00000039
+
+/* IPAv4 spare reg value */
+#define IPA_HW_SPARE_1_REG_VAL                       0xC0000005
+
+/* Whether to allow setting step mode on IPA when we crash or not */
+#define IPA_CFG_HW_IS_STEP_MODE_ALLOWED              (false)
+
+/* GSI MHI related definitions */
+#define IPA_HW_GSI_MHI_CONSUMER_CHANNEL_NUM          0x0
+#define IPA_HW_GSI_MHI_PRODUCER_CHANNEL_NUM          0x1
+
+#define IPA_HW_GSI_MHI_CONSUMER_EP_NUM               0x1
+#define IPA_HW_GSI_MHI_PRODUCER_EP_NUM               0x11
+
+/* IPA ZIP WA related Macros */
+#define IPA_HW_DCMP_SRC_PIPE                         0x8
+#define IPA_HW_DCMP_DEST_PIPE                        0x4
+#define IPA_HW_ACK_MNGR_MASK                         0x1D
+#define IPA_HW_DCMP_SRC_GRP                          0x5
+
+/* IPA Clock resource name */
+#define IPA_CLK_RESOURCE_NAME                        "/clk/pcnoc"
+
+/* IPA Clock Bus Client name */
+#define IPA_CLK_BUS_CLIENT_NAME                      "IPA_PCNOC_BUS_CLIENT"
+
+/* HPS Sequences */
+#define IPA_HW_PKT_PROCESS_HPS_DMA                      0x0
+#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_UCP       0x3
+#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_NO_DECIPH      0x4
+#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_DECIPH         0x5
+#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_NO_UCP 0x6
+#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_NO_UCP    0x7
+#define IPA_HW_PKT_PROCESS_HPS_DMA_PARSER               0x8
+#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_PARSER        0x9
+
+/* DPS Sequences */
+#define IPA_HW_PKT_PROCESS_DPS_DMA                      0x0
+#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECIPH          0x1
+#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECOMP          0x2
+
+/* Src RSRC GRP config */
+#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_0           0x05050404
+#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_1           0x0A0A0A0A
+#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_2           0x0C0C0C0C
+#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_3           0x3F003F00
+#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_4           0x0E0E0E0E
+
+#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_0           0x00000101
+#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_1           0x00000808
+#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_2           0x00000808
+#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_3           0x3F003F00
+#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_4           0x00000E0E
+
+/* Dest RSRC GRP config */
+#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_0           0x04040404
+#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_1           0x3F013F02
+
+#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_0           0x02020303
+#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_1           0x02000201
+
+
+#define IPA_HW_RX_HPS_CLIENTS_MIN_DEPTH_0            0x00020703
+#define IPA_HW_RX_HPS_CLIENTS_MAX_DEPTH_0            0x00020703
+
+#define IPA_HW_RSRP_GRP_0                            0x0
+#define IPA_HW_RSRP_GRP_1                            0x1
+#define IPA_HW_RSRP_GRP_2                            0x2
+#define IPA_HW_RSRP_GRP_3                            0x3
+
+#define IPA_HW_PCIE_SRC_RSRP_GRP                     IPA_HW_RSRP_GRP_0
+#define IPA_HW_PCIE_DEST_RSRP_GRP                    IPA_HW_RSRP_GRP_0
+
+#define IPA_HW_DDR_SRC_RSRP_GRP                      IPA_HW_RSRP_GRP_1
+#define IPA_HW_DDR_DEST_RSRP_GRP                     IPA_HW_RSRP_GRP_1
+
+#define IPA_HW_SRC_RSRP_TYPE_MAX                     0x5
+#define IPA_HW_DST_RSRP_TYPE_MAX                     0x2
+
+#define GSI_HW_QSB_LOG_MISC_MAX 0x4
+
+/* IPA Clock Bus Client name */
+#define IPA_CLK_BUS_CLIENT_NAME                      "IPA_PCNOC_BUS_CLIENT"
+
+/* Is IPA decompression feature enabled */
+#define IPA_HW_IS_DECOMPRESSION_ENABLED              (1)
+
+/* Whether to allow setting step mode on IPA when we crash or not */
+#define IPA_HW_IS_STEP_MODE_ALLOWED                  (true)
+
+/*
+ * HW specific clock vote freq values in KHz
+ * (BIMC/SNOC/PCNOC/IPA/Q6 CPU)
+ */
+enum ipa_hw_clk_freq_e {
+	/* BIMC */
+	IPA_HW_CLK_FREQ_BIMC_PEAK       = 518400,
+	IPA_HW_CLK_FREQ_BIMC_NOM_PLUS   = 404200,
+	IPA_HW_CLK_FREQ_BIMC_NOM        = 404200,
+	IPA_HW_CLK_FREQ_BIMC_SVS        = 100000,
+
+	/* PCNOC */
+	IPA_HW_CLK_FREQ_PCNOC_PEAK      = 133330,
+	IPA_HW_CLK_FREQ_PCNOC_NOM_PLUS  = 100000,
+	IPA_HW_CLK_FREQ_PCNOC_NOM       = 100000,
+	IPA_HW_CLK_FREQ_PCNOC_SVS       = 50000,
+
+	/*IPA_HW_CLK_SNOC*/
+	IPA_HW_CLK_FREQ_SNOC_PEAK       = 200000,
+	IPA_HW_CLK_FREQ_SNOC_NOM_PLUS   = 150000,
+	IPA_HW_CLK_FREQ_SNOC_NOM        = 150000,
+	IPA_HW_CLK_FREQ_SNOC_SVS        = 85000,
+	IPA_HW_CLK_FREQ_SNOC_SVS_2      = 50000,
+
+	/* IPA */
+	IPA_HW_CLK_FREQ_IPA_PEAK        = 500000,
+	IPA_HW_CLK_FREQ_IPA_NOM_PLUS    = 440000,
+	IPA_HW_CLK_FREQ_IPA_NOM         = 440000,
+	IPA_HW_CLK_FREQ_IPA_SVS         = 250000,
+	IPA_HW_CLK_FREQ_IPA_SVS_2       = 120000,
+
+	/* Q6 CPU */
+	IPA_HW_CLK_FREQ_Q6_PEAK         = 729600,
+	IPA_HW_CLK_FREQ_Q6_NOM_PLUS     = 729600,
+	IPA_HW_CLK_FREQ_Q6_NOM          = 729600,
+	IPA_HW_CLK_FREQ_Q6_SVS          = 729600,
+};
+
+/* Pipe ID of all the IPA pipes */
+enum ipa_hw_pipe_id_e {
+	IPA_HW_PIPE_ID_0,
+	IPA_HW_PIPE_ID_1,
+	IPA_HW_PIPE_ID_2,
+	IPA_HW_PIPE_ID_3,
+	IPA_HW_PIPE_ID_4,
+	IPA_HW_PIPE_ID_5,
+	IPA_HW_PIPE_ID_6,
+	IPA_HW_PIPE_ID_7,
+	IPA_HW_PIPE_ID_8,
+	IPA_HW_PIPE_ID_9,
+	IPA_HW_PIPE_ID_10,
+	IPA_HW_PIPE_ID_11,
+	IPA_HW_PIPE_ID_12,
+	IPA_HW_PIPE_ID_13,
+	IPA_HW_PIPE_ID_14,
+	IPA_HW_PIPE_ID_15,
+	IPA_HW_PIPE_ID_16,
+	IPA_HW_PIPE_ID_17,
+	IPA_HW_PIPE_ID_18,
+	IPA_HW_PIPE_ID_19,
+	IPA_HW_PIPE_ID_20,
+	IPA_HW_PIPE_ID_21,
+	IPA_HW_PIPE_ID_22,
+	IPA_HW_PIPE_ID_MAX
+};
+
+/* Pipe ID's of System Bam Endpoints between Q6 & IPA */
+enum ipa_hw_q6_pipe_id_e {
+	/* Pipes used by IPA Q6 driver */
+	IPA_HW_Q6_DL_CONSUMER_PIPE_ID           = IPA_HW_PIPE_ID_3,
+	IPA_HW_Q6_CTL_CONSUMER_PIPE_ID          = IPA_HW_PIPE_ID_4,
+	IPA_HW_Q6_UL_PRODUCER_PIPE_ID           = IPA_HW_PIPE_ID_13,
+	IPA_HW_Q6_DL_PRODUCER_PIPE_ID           = IPA_HW_PIPE_ID_14,
+
+	IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_ID       = IPA_HW_PIPE_ID_6,
+	IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_ID       = IPA_HW_PIPE_ID_16,
+	/* Test Simulator Pipes */
+	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_ID     = IPA_HW_PIPE_ID_0,
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_ID     = IPA_HW_PIPE_ID_12,
+	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_ID     = IPA_HW_PIPE_ID_1,
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_ID     = IPA_HW_PIPE_ID_10,
+	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_ID     = IPA_HW_PIPE_ID_2,
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_ID     = IPA_HW_PIPE_ID_11,
+	/* GSI UT channel SW->IPA */
+	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_ID     = IPA_HW_PIPE_ID_5,
+	/* GSI UT channel IPA->SW */
+	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_ID     = IPA_HW_PIPE_ID_17,
+	/* GSI UT channel SW->IPA */
+	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_ID     = IPA_HW_PIPE_ID_7,
+	/* GSI UT channel IPA->SW */
+	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_ID     = IPA_HW_PIPE_ID_18,
+	IPA_HW_Q6_DIAG_CONSUMER_PIPE_ID         = IPA_HW_PIPE_ID_19,
+	IPA_HW_Q6_PIPE_ID_MAX                   = IPA_HW_PIPE_ID_MAX,
+};
+
+enum ipa_hw_q6_pipe_ch_id_e {
+	/* Channels used by IPA Q6 driver */
+	IPA_HW_Q6_DL_CONSUMER_PIPE_CH_ID           = 0,
+	IPA_HW_Q6_CTL_CONSUMER_PIPE_CH_ID          = 1,
+	IPA_HW_Q6_UL_PRODUCER_PIPE_CH_ID           = 3,
+	IPA_HW_Q6_DL_PRODUCER_PIPE_CH_ID           = 4,
+
+	IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_CH_ID       = 2,
+	IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_CH_ID       = 5,
+	/* Test Simulator Channels */
+	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_CH_ID     = 6,
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_CH_ID     = 8,
+	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_CH_ID     = 9,
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_CH_ID     = 10,
+	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_CH_ID     = 11,
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_CH_ID     = 12,
+	/* GSI UT channel SW->IPA */
+	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_CH_ID     = 13,
+	/* GSI UT channel IPA->SW */
+	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_CH_ID     = 14,
+	/* GSI UT channel SW->IPA */
+	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_CH_ID     = 15,
+	/* GSI UT channel IPA->SW */
+	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_CH_ID     = 16,
+};
+
+/* System Bam Endpoints between Q6 & IPA */
+enum ipa_hw_q6_pipe_e {
+	/* DL Pipe IPA->Q6 */
+	IPA_HW_Q6_DL_PRODUCER_PIPE = 0,
+	/* UL Pipe IPA->Q6 */
+	IPA_HW_Q6_UL_PRODUCER_PIPE = 1,
+	/* DL Pipe Q6->IPA */
+	IPA_HW_Q6_DL_CONSUMER_PIPE = 2,
+	/* CTL Pipe Q6->IPA */
+	IPA_HW_Q6_CTL_CONSUMER_PIPE = 3,
+	/*  Q6 -> IPA,  LTE DL Optimized path */
+	IPA_HW_Q6_LTE_DL_CONSUMER_PIPE = 4,
+	/* LWA DL(Wifi to Q6) */
+	IPA_HW_Q6_LWA_DL_PRODUCER_PIPE = 5,
+	/* Diag status pipe IPA->Q6 */
+	/* Used only when FEATURE_IPA_TEST_PER_SIM is ON */
+	/* SIM Pipe IPA->Sim */
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0 = 7,
+	/* SIM Pipe Sim->IPA */
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1 = 8,
+	/* SIM Pipe Sim->IPA */
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2 = 9,
+	/* SIM Pipe Sim->IPA */
+	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0 = 10,
+	/* SIM B2B PROD Pipe  */
+	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1 = 11,
+	/* SIM Pipe IPA->Sim */
+	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2 = 12,
+	/* End FEATURE_IPA_TEST_PER_SIM */
+	/* GSI UT channel SW->IPA */
+	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1 = 13,
+	/* GSI UT channel IPA->SW */
+	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1 = 14,
+	/* GSI UT channel SW->IPA */
+	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2 = 15,
+	/* GSI UT channel IPA->SW */
+	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2 = 16,
+	IPA_HW_Q6_PIPE_TOTAL
+};
+
+/* System Bam Endpoints between Q6 & IPA */
+enum ipa_hw_q6_gsi_ev_e { /* In Sdx24 0..11 */
+	/* DL Pipe IPA->Q6 */
+	IPA_HW_Q6_DL_PRODUCER_PIPE_GSI_EV = 0,
+	/* UL Pipe IPA->Q6 */
+	IPA_HW_Q6_UL_PRODUCER_PIPE_GSI_EV = 1,
+	/* DL Pipe Q6->IPA */
+	//IPA_HW_Q6_DL_CONSUMER_PIPE_GSI_EV = 2,
+	/* CTL Pipe Q6->IPA */
+	//IPA_HW_Q6_CTL_CONSUMER_PIPE_GSI_EV = 3,
+	/*  Q6 -> IPA,  LTE DL Optimized path */
+	//IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_GSI_EV = 4,
+	/* LWA DL(Wifi to Q6) */
+	//IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_GSI_EV = 5,
+	/* Diag status pipe IPA->Q6 */
+	//IPA_HW_Q6_DIAG_STATUS_PRODUCER_PIPE_GSI_EV = 6,
+	/* Used only when FEATURE_IPA_TEST_PER_SIM is ON */
+	/* SIM Pipe IPA->Sim */
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_GSI_EV = 2,
+	/* SIM Pipe Sim->IPA */
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_GSI_EV = 3,
+	/* SIM Pipe Sim->IPA */
+	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_GSI_EV = 4,
+	/* SIM Pipe Sim->IPA */
+	IPA_HW_Q6_SIM_1_GSI_EV = 5,
+	IPA_HW_Q6_SIM_2_GSI_EV = 6,
+	IPA_HW_Q6_SIM_3_GSI_EV = 7,
+	IPA_HW_Q6_SIM_4_GSI_EV = 8,
+
+	IPA_HW_Q6_PIPE_GSI_EV_TOTAL
+};
+
+/*
+ * All the IRQ's supported by the IPA HW. Use this enum to set IRQ_EN
+ * register and read IRQ_STTS register
+ */
+enum ipa_hw_irq_e {
+	IPA_HW_IRQ_GSI_HWP                     = (1 << 25),
+	IPA_HW_IRQ_GSI_IPA_IF_TLV_RCVD         = (1 << 24),
+	IPA_HW_IRQ_GSI_EE_IRQ                  = (1 << 23),
+	IPA_HW_IRQ_DCMP_ERR                    = (1 << 22),
+	IPA_HW_IRQ_HWP_ERR                     = (1 << 21),
+	IPA_HW_IRQ_RED_MARKER_ABOVE            = (1 << 20),
+	IPA_HW_IRQ_YELLOW_MARKER_ABOVE         = (1 << 19),
+	IPA_HW_IRQ_RED_MARKER_BELOW            = (1 << 18),
+	IPA_HW_IRQ_YELLOW_MARKER_BELOW         = (1 << 17),
+	IPA_HW_IRQ_BAM_IDLE_IRQ                = (1 << 16),
+	IPA_HW_IRQ_TX_HOLB_DROP                = (1 << 15),
+	IPA_HW_IRQ_TX_SUSPEND                  = (1 << 14),
+	IPA_HW_IRQ_PROC_ERR                    = (1 << 13),
+	IPA_HW_IRQ_STEP_MODE                   = (1 << 12),
+	IPA_HW_IRQ_TX_ERR                      = (1 << 11),
+	IPA_HW_IRQ_DEAGGR_ERR                  = (1 << 10),
+	IPA_HW_IRQ_RX_ERR                      = (1 << 9),
+	IPA_HW_IRQ_PROC_TO_HW_ACK_Q_NOT_EMPTY  = (1 << 8),
+	IPA_HW_IRQ_HWP_RX_CMD_Q_NOT_FULL       = (1 << 7),
+	IPA_HW_IRQ_HWP_IN_Q_NOT_EMPTY          = (1 << 6),
+	IPA_HW_IRQ_HWP_IRQ_3                   = (1 << 5),
+	IPA_HW_IRQ_HWP_IRQ_2                   = (1 << 4),
+	IPA_HW_IRQ_HWP_IRQ_1                   = (1 << 3),
+	IPA_HW_IRQ_HWP_IRQ_0                   = (1 << 2),
+	IPA_HW_IRQ_EOT_COAL                    = (1 << 1),
+	IPA_HW_IRQ_BAD_SNOC_ACCESS             = (1 << 0),
+	IPA_HW_IRQ_NONE                        = 0,
+	IPA_HW_IRQ_ALL                         = 0xFFFFFFFF
+};
+
+/*
+ * All the IRQ sources supported by the IPA HW. Use this enum to set
+ * IRQ_SRCS register
+ */
+enum ipa_hw_irq_srcs_e {
+	IPA_HW_IRQ_SRCS_PIPE_0  = (1 << IPA_HW_PIPE_ID_0),
+	IPA_HW_IRQ_SRCS_PIPE_1  = (1 << IPA_HW_PIPE_ID_1),
+	IPA_HW_IRQ_SRCS_PIPE_2  = (1 << IPA_HW_PIPE_ID_2),
+	IPA_HW_IRQ_SRCS_PIPE_3  = (1 << IPA_HW_PIPE_ID_3),
+	IPA_HW_IRQ_SRCS_PIPE_4  = (1 << IPA_HW_PIPE_ID_4),
+	IPA_HW_IRQ_SRCS_PIPE_5  = (1 << IPA_HW_PIPE_ID_5),
+	IPA_HW_IRQ_SRCS_PIPE_6  = (1 << IPA_HW_PIPE_ID_6),
+	IPA_HW_IRQ_SRCS_PIPE_7  = (1 << IPA_HW_PIPE_ID_7),
+	IPA_HW_IRQ_SRCS_PIPE_8  = (1 << IPA_HW_PIPE_ID_8),
+	IPA_HW_IRQ_SRCS_PIPE_9  = (1 << IPA_HW_PIPE_ID_9),
+	IPA_HW_IRQ_SRCS_PIPE_10 = (1 << IPA_HW_PIPE_ID_10),
+	IPA_HW_IRQ_SRCS_PIPE_11 = (1 << IPA_HW_PIPE_ID_11),
+	IPA_HW_IRQ_SRCS_PIPE_12 = (1 << IPA_HW_PIPE_ID_12),
+	IPA_HW_IRQ_SRCS_PIPE_13 = (1 << IPA_HW_PIPE_ID_13),
+	IPA_HW_IRQ_SRCS_PIPE_14 = (1 << IPA_HW_PIPE_ID_14),
+	IPA_HW_IRQ_SRCS_PIPE_15 = (1 << IPA_HW_PIPE_ID_15),
+	IPA_HW_IRQ_SRCS_PIPE_16 = (1 << IPA_HW_PIPE_ID_16),
+	IPA_HW_IRQ_SRCS_PIPE_17 = (1 << IPA_HW_PIPE_ID_17),
+	IPA_HW_IRQ_SRCS_PIPE_18 = (1 << IPA_HW_PIPE_ID_18),
+	IPA_HW_IRQ_SRCS_PIPE_19 = (1 << IPA_HW_PIPE_ID_19),
+	IPA_HW_IRQ_SRCS_PIPE_20 = (1 << IPA_HW_PIPE_ID_20),
+	IPA_HW_IRQ_SRCS_PIPE_21 = (1 << IPA_HW_PIPE_ID_21),
+	IPA_HW_IRQ_SRCS_PIPE_22 = (1 << IPA_HW_PIPE_ID_22),
+	IPA_HW_IRQ_SRCS_NONE    = 0,
+	IPA_HW_IRQ_SRCS_ALL     = 0xFFFFFFFF,
+};
+
+/*
+ * Total number of channel contexts that need to be saved for APPS
+ */
+#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7          15
+
+/*
+ * Total number of channel contexts that need to be saved for UC
+ */
+#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC          5
+
+/*
+ * Total number of event ring contexts that need to be saved for APPS
+ */
+#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7         12
+
+/*
+ * Total number of event ring contexts that need to be saved for UC
+ */
+#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC         4
+
+/*
+ * Total number of endpoints for which ipa_reg_save.pipes[endp_number]
+ * are not saved by default (only if ipa_cfg.gen.full_reg_trace =
+ * true) There is no extra endpoints in Stingray
+ */
+#define IPA_HW_REG_SAVE_NUM_ENDP_EXTRA               0
+
+/*
+ * Total number of endpoints for which ipa_reg_save.pipes[endp_number]
+ * are always saved
+ */
+#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES             23
+
+/*
+ * Macro to set the active flag for all active pipe indexed register
+ */
+#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_ACTIVE() \
+	do { \
+		ipa_reg_save.ipa.pipes[0].active = true; \
+		ipa_reg_save.ipa.pipes[1].active = true; \
+		ipa_reg_save.ipa.pipes[2].active = true; \
+		ipa_reg_save.ipa.pipes[3].active = true; \
+		ipa_reg_save.ipa.pipes[4].active = true; \
+		ipa_reg_save.ipa.pipes[5].active = true; \
+		ipa_reg_save.ipa.pipes[6].active = true; \
+		ipa_reg_save.ipa.pipes[7].active = true; \
+		ipa_reg_save.ipa.pipes[8].active = true; \
+		ipa_reg_save.ipa.pipes[9].active = true; \
+		ipa_reg_save.ipa.pipes[10].active = true; \
+		ipa_reg_save.ipa.pipes[11].active = true; \
+		ipa_reg_save.ipa.pipes[12].active = true; \
+		ipa_reg_save.ipa.pipes[13].active = true; \
+		ipa_reg_save.ipa.pipes[14].active = true; \
+		ipa_reg_save.ipa.pipes[15].active = true; \
+		ipa_reg_save.ipa.pipes[16].active = true; \
+		ipa_reg_save.ipa.pipes[17].active = true; \
+		ipa_reg_save.ipa.pipes[18].active = true; \
+		ipa_reg_save.ipa.pipes[19].active = true; \
+		ipa_reg_save.ipa.pipes[20].active = true; \
+		ipa_reg_save.ipa.pipes[21].active = true; \
+		ipa_reg_save.ipa.pipes[22].active = true; \
+	} while (0)
+
+/*
+ * Macro to define a particular register cfg entry for the remaining
+ * pipe indexed register.  In Stingray case we don't have extra
+ * endpoints so it is intentially empty
+ */
+#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(REG_NAME, VAR_NAME)  \
+	{ 0, 0 }
+
+/*
+ * Macro to set the active flag for all active pipe indexed register
+ * In Stingray case we don't have extra endpoints so it is intentially
+ * empty
+ */
+#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE()  \
+	do { \
+	} while (0)
+
+#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \
+		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
+		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \
+		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].var_name }
+
+/*
+ * Macro to define a particular register cfg entry for all GSI EE
+ * register
+ */
+#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 0),	\
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 2), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[2].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[3].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 4), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[4].var_name }
+
+#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 0), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[1].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 2), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[2].var_name }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[3].var_name }
+
+/*
+ * Macro to define a particular register cfg entry for all pipe
+ * indexed register
+ */
+#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(reg_name, var_name) \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
+		(u32 *)&ipa_reg_save.ipa.pipes[0].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
+		(u32 *)&ipa_reg_save.ipa.pipes[1].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 2), \
+		(u32 *)&ipa_reg_save.ipa.pipes[2].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \
+		(u32 *)&ipa_reg_save.ipa.pipes[3].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 4), \
+		(u32 *)&ipa_reg_save.ipa.pipes[4].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 5), \
+		(u32 *)&ipa_reg_save.ipa.pipes[5].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 6), \
+		(u32 *)&ipa_reg_save.ipa.pipes[6].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 7), \
+		(u32 *)&ipa_reg_save.ipa.pipes[7].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 8), \
+		(u32 *)&ipa_reg_save.ipa.pipes[8].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 9), \
+		(u32 *)&ipa_reg_save.ipa.pipes[9].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 10), \
+		(u32 *)&ipa_reg_save.ipa.pipes[10].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 11), \
+		(u32 *)&ipa_reg_save.ipa.pipes[11].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 12), \
+		(u32 *)&ipa_reg_save.ipa.pipes[12].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 13), \
+		(u32 *)&ipa_reg_save.ipa.pipes[13].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 14), \
+		(u32 *)&ipa_reg_save.ipa.pipes[14].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 15), \
+		(u32 *)&ipa_reg_save.ipa.pipes[15].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 16), \
+		(u32 *)&ipa_reg_save.ipa.pipes[16].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 17), \
+		(u32 *)&ipa_reg_save.ipa.pipes[17].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 18), \
+		(u32 *)&ipa_reg_save.ipa.pipes[18].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 19), \
+		(u32 *)&ipa_reg_save.ipa.pipes[19].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 20), \
+		(u32 *)&ipa_reg_save.ipa.pipes[20].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 21), \
+		(u32 *)&ipa_reg_save.ipa.pipes[21].endp.var_name }, \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 22), \
+		(u32 *)&ipa_reg_save.ipa.pipes[22].endp.var_name }
+
+
+#define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM        8
+/*
+ * Total number of rx splt cmdq's see:
+ * ipa_rx_splt_cmdq_n_cmd[IPA_RX_SPLT_CMDQ_MAX]
+ */
+#define IPA_RX_SPLT_CMDQ_MAX 3
+
+#endif /* #if !defined(_IPA_HW_COMMON_EX_H_) */

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_pkt_cntxt.h

@@ -0,0 +1,190 @@
+/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#if !defined(_IPA_PKT_CNTXT_H_)
+#define _IPA_PKT_CNTXT_H_
+
+#define IPA_HW_PKT_CTNTX_MAX        0x10
+#define IPA_HW_NUM_SAVE_PKT_CTNTX   0x8
+#define IPA_HW_PKT_CTNTX_START_ADDR 0xE434CA00
+#define IPA_HW_PKT_CTNTX_SIZE       (sizeof(ipa_pkt_ctntx_opcode_state_s) + \
+				     sizeof(ipa_pkt_ctntx_u))
+
+/*
+ * Packet Context States
+ */
+enum ipa_hw_pkt_cntxt_state_e {
+	IPA_HW_PKT_CNTXT_STATE_HFETCHER_INIT = 1,
+	IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR,
+	IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR_REP,
+	IPA_HW_PKT_CNTXT_STATE_H_DCPH,
+	IPA_HW_PKT_CNTXT_STATE_PKT_PARSER,
+	IPA_HW_PKT_CNTXT_STATE_FILTER_NAT,
+	IPA_HW_PKT_CNTXT_STATE_ROUTER,
+	IPA_HW_PKT_CNTXT_STATE_HDRI,
+	IPA_HW_PKT_CNTXT_STATE_UCP,
+	IPA_HW_PKT_CNTXT_STATE_ENQUEUER,
+	IPA_HW_PKT_CNTXT_STATE_DFETCHER,
+	IPA_HW_PKT_CNTXT_STATE_D_DCPH,
+	IPA_HW_PKT_CNTXT_STATE_DISPATCHER,
+	IPA_HW_PKT_CNTXT_STATE_TX,
+	IPA_HW_PKT_CNTXT_STATE_TX_ZLT,
+	IPA_HW_PKT_CNTXT_STATE_DFETCHER_DMAR,
+	IPA_HW_PKT_CNTXT_STATE_DCMP,
+};
+
+/*
+ * Packet Context fields as received from VI/Design
+ */
+struct ipa_pkt_ctntx_s {
+	u64	opcode                           : 8;
+	u64	state                            : 5;
+	u64	not_used_1                       : 2;
+	u64	tx_pkt_dma_done                  : 1;
+	u64	exc_deagg                        : 1;
+	u64	exc_pkt_version                  : 1;
+	u64	exc_pkt_len                      : 1;
+	u64	exc_threshold                    : 1;
+	u64	exc_sw                           : 1;
+	u64	exc_nat                          : 1;
+	u64	exc_frag_miss                    : 1;
+	u64	filter_bypass                    : 1;
+	u64	router_bypass                    : 1;
+	u64	nat_bypass                       : 1;
+	u64	hdri_bypass                      : 1;
+	u64	dcph_bypass                      : 1;
+	u64	security_credentials_select      : 1;
+	u64	pkt_2nd_pass                     : 1;
+	u64	xlat_bypass                      : 1;
+	u64	dcph_valid                       : 1;
+	u64	ucp_on                           : 1;
+	u64	replication                      : 1;
+	u64	src_status_en                    : 1;
+	u64	dest_status_en                   : 1;
+	u64	frag_status_en                   : 1;
+	u64	eot_dest                         : 1;
+	u64	eot_notif                        : 1;
+	u64	prev_eot_dest                    : 1;
+	u64	src_hdr_len                      : 8;
+	u64	tx_valid_sectors                 : 8;
+	u64	rx_flags                         : 8;
+	u64	rx_packet_length                 : 16;
+	u64	revised_packet_length            : 16;
+	u64	frag_en                          : 1;
+	u64	frag_bypass                      : 1;
+	u64	frag_process                     : 1;
+	u64	notif_pipe                       : 5;
+	u64	src_id                           : 8;
+	u64	tx_pkt_transferred               : 1;
+	u64	src_pipe                         : 5;
+	u64	dest_pipe                        : 5;
+	u64	frag_pipe                        : 5;
+	u64	ihl_offset                       : 8;
+	u64	protocol                         : 8;
+	u64	tos                              : 8;
+	u64	id                               : 16;
+	u64	v6_reserved                      : 4;
+	u64	ff                               : 1;
+	u64	mf                               : 1;
+	u64	pkt_israg                        : 1;
+	u64	tx_holb_timer_overflow           : 1;
+	u64	tx_holb_timer_running            : 1;
+	u64	trnseq_0                         : 3;
+	u64	trnseq_1                         : 3;
+	u64	trnseq_2                         : 3;
+	u64	trnseq_3                         : 3;
+	u64	trnseq_4                         : 3;
+	u64	trnseq_ex_length                 : 8;
+	u64	trnseq_4_length                  : 8;
+	u64	trnseq_4_offset                  : 8;
+	u64	dps_tx_pop_cnt                   : 2;
+	u64	dps_tx_push_cnt                  : 2;
+	u64	vol_ic_dcph_cfg                  : 1;
+	u64	vol_ic_tag_stts                  : 1;
+	u64	vol_ic_pxkt_init_e               : 1;
+	u64	vol_ic_pkt_init                  : 1;
+	u64	tx_holb_counter                  : 32;
+	u64	trnseq_0_length                  : 8;
+	u64	trnseq_0_offset                  : 8;
+	u64	trnseq_1_length                  : 8;
+	u64	trnseq_1_offset                  : 8;
+	u64	trnseq_2_length                  : 8;
+	u64	trnseq_2_offset                  : 8;
+	u64	trnseq_3_length                  : 8;
+	u64	trnseq_3_offset                  : 8;
+	u64	dmar_valid_length                : 16;
+	u64	dcph_valid_length                : 16;
+	u64	frag_hdr_offset                  : 9;
+	u64	ip_payload_offset                : 9;
+	u64	frag_rule                        : 4;
+	u64	frag_table                       : 1;
+	u64	frag_hit                         : 1;
+	u64	data_cmdq_ptr                    : 8;
+	u64	filter_result                    : 6;
+	u64	router_result                    : 6;
+	u64	nat_result                       : 6;
+	u64	hdri_result                      : 6;
+	u64	dcph_result                      : 6;
+	u64	dcph_result_valid                : 1;
+	u32	not_used_2                       : 4;
+	u64	tx_pkt_suspended                 : 1;
+	u64	tx_pkt_dropped                   : 1;
+	u32	not_used_3                       : 3;
+	u64	metadata_valid                   : 1;
+	u64	metadata_type                    : 4;
+	u64	ul_cs_start_diff                 : 9;
+	u64	cs_disable_trlr_vld_bit          : 1;
+	u64	cs_required                      : 1;
+	u64	dest_hdr_len                     : 8;
+	u64	fr_l                             : 1;
+	u64	fl_h                             : 1;
+	u64	fr_g                             : 1;
+	u64	fr_ret                           : 1;
+	u64	fr_rule_id                       : 10;
+	u64	rt_l                             : 1;
+	u64	rt_h                             : 1;
+	u64	rtng_tbl_index                   : 5;
+	u64	rt_match                         : 1;
+	u64	rt_rule_id                       : 10;
+	u64	nat_tbl_index                    : 13;
+	u64	nat_type                         : 2;
+	u64	hdr_l                            : 1;
+	u64	header_offset                    : 10;
+	u64	not_used_4                       : 1;
+	u64	filter_result_valid              : 1;
+	u64	router_result_valid              : 1;
+	u64	nat_result_valid                 : 1;
+	u64	hdri_result_valid                : 1;
+	u64	not_used_5                       : 1;
+	u64	stream_id                        : 8;
+	u64	not_used_6                       : 6;
+	u64	dcph_context_index               : 2;
+	u64	dcph_cfg_size                    : 16;
+	u64	dcph_cfg_count                   : 32;
+	u64	tag_info                         : 48;
+	u64	ucp_cmd_id                       : 16;
+	u64	metadata                         : 32;
+	u64	ucp_cmd_params                   : 32;
+	u64	nat_ip_address                   : 32;
+	u64	nat_ip_cs_diff                   : 16;
+	u64	frag_dest_pipe                   : 5;
+	u64	frag_nat_type                    : 2;
+	u64	fragr_ret                        : 1;
+	u64	frag_protocol                    : 8;
+	u64	src_ip_address                   : 32;
+	u64	dest_ip_address                  : 32;
+	u64	not_used_7                       : 37;
+	u64	frag_hdr_l                       : 1;
+	u64	frag_header_offset               : 10;
+	u64	frag_id                          : 16;
+} __packed;
+
+#endif /* #if !defined(_IPA_PKT_CNTXT_H_) */

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
  */
 #if !defined(_IPA_HW_COMMON_EX_H_)
 #define _IPA_HW_COMMON_EX_H_
@@ -505,6 +505,107 @@ enum ipa_hw_irq_srcs_e {
 #define IPA_GSI_ADDR  0x00006000
 #define IPA_GSI_SIZE  round_up(5376, sizeof(u32))
 
+#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \
+       { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \
+               (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \
+       { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
+               (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \
+       { GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \
+              (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].\
+                       var_name }
+
+/*
+ * Macro to define a particular register cfg entry for all GSI EE
+ * register
+ */
+#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
+              (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \
+              (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[15].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[16].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[17].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[18].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1),  \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
+               (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }
+
+#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[12].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[13].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[14].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[15].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[16].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[17].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name }, \
+       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
+               (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }
+
 /*
  * Macro to define a particular register cfg entry for all pipe
  * indexed register

drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
  */
 #include "ipa_reg_dump.h"
 #include "ipa_access_control.h"
@@ -52,12 +52,18 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
 	GEN_SRC_DST_ADDR_MAP(IPA_STATE_DFETCHER,
 			     ipa.gen,
 			     ipa_state_dfetcher),
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_0,
 			     ipa.gen,
 			     ipa_state_fetcher_mask_0),
 	GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_1,
 			     ipa.gen,
 			     ipa_state_fetcher_mask_1),
+#else
+	GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK,
+			     ipa.gen,
+			     ipa_state_fetcher_mask),
+#endif
 	GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_AOS,
 			     ipa.gen,
 			     ipa_state_gsi_aos),
@@ -115,9 +121,6 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
 	GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_RAM_PTR,
 			     ipa.gen,
 			     ipa_log_buf_hw_cmd_ram_ptr),
-	GEN_SRC_DST_ADDR_MAP(IPA_STATE_DPL_FIFO,
-			     ipa.gen,
-			     ipa_state_dpl_fifo),
 	GEN_SRC_DST_ADDR_MAP(IPA_COMP_HW_VERSION,
 			     ipa.gen,
 			     ipa_comp_hw_version),
@@ -172,12 +175,26 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
 	GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG,
 			     ipa.gen,
 			     ipa_rsrc_grp_cfg),
-	GEN_SRC_DST_ADDR_MAP(IPA_PIPELINE_DISABLE,
-			     ipa.gen,
-			     ipa_pipeline_disable),
 	GEN_SRC_DST_ADDR_MAP(IPA_COMP_CFG,
 			     ipa.gen,
 			     ipa_comp_cfg),
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_1)
+	GEN_SRC_DST_ADDR_MAP(IPA_GSI_CONF,
+			     ipa.gen,
+			     ipa_gsi_conf),
+	GEN_SRC_DST_ADDR_MAP(IPA_TAG_TIMER,
+			     ipa.gen,
+			     ipa_tag_timer),
+	GEN_SRC_DST_ADDR_MAP(IPA_BCR,
+			     ipa.gen,
+			     ipa_bcr),
+#else
+	GEN_SRC_DST_ADDR_MAP(IPA_STATE_DPL_FIFO,
+			     ipa.gen,
+			     ipa_state_dpl_fifo),
+	GEN_SRC_DST_ADDR_MAP(IPA_PIPELINE_DISABLE,
+			     ipa.gen,
+			     ipa_pipeline_disable),
 	GEN_SRC_DST_ADDR_MAP(IPA_STATE_NLO_AGGR,
 			     ipa.gen,
 			     ipa_state_nlo_aggr),
@@ -213,12 +230,13 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
 			     ipa_nlo_vp_qbap_open),
 
 	/* Debug Registers */
-	GEN_SRC_DST_ADDR_MAP(IPA_DEBUG_DATA,
-			     ipa.dbg,
-			     ipa_debug_data),
 	GEN_SRC_DST_ADDR_MAP(IPA_STEP_MODE_BREAKPOINTS,
 			     ipa.dbg,
 			     ipa_step_mode_breakpoints),
+#endif
+	GEN_SRC_DST_ADDR_MAP(IPA_DEBUG_DATA,
+			     ipa.dbg,
+			     ipa_debug_data),
 	GEN_SRC_DST_ADDR_MAP(IPA_STEP_MODE_STATUS,
 			     ipa.dbg,
 			     ipa_step_mode_status),
@@ -352,33 +370,38 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
 					    ipa_src_rsrc_grp_01_rsrc_type_n),
 	IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n,
 					    ipa_src_rsrc_grp_23_rsrc_type_n),
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n,
 					    ipa_src_rsrc_grp_45_rsrc_type_n),
+#endif
 
 	/* Destination Resource Group Config Registers */
 	IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_01_RSRC_TYPE_n,
 					    ipa_dst_rsrc_grp_01_rsrc_type_n),
 	IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_23_RSRC_TYPE_n,
 					    ipa_dst_rsrc_grp_23_rsrc_type_n),
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_45_RSRC_TYPE_n,
 					    ipa_dst_rsrc_grp_45_rsrc_type_n),
-
+#endif
 	/* Source Resource Group Count Registers */
 	IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(
 		IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n,
 		ipa_src_rsrc_grp_0123_rsrc_type_cnt_n),
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(
 		IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n,
 		ipa_src_rsrc_grp_4567_rsrc_type_cnt_n),
-
+#endif
 	/* Destination Resource Group Count Registers */
 	IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(
 		IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n,
 		ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n),
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(
 		IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n,
 		ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n),
-
+#endif
 	/*
 	 * =====================================================================
 	 * GSI register definitions begin here...
@@ -968,6 +991,7 @@ void ipa_save_registers(void)
 		}
 	}
 
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	if (ipa3_ctx->do_ram_collection_on_crash) {
 		for (i = 0; i < IPA_IU_SIZE / sizeof(u32); i++) {
 			ipa_reg_save.ipa.ipa_iu_ptr[i] =
@@ -1000,7 +1024,7 @@ void ipa_save_registers(void)
 		IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_seq_ptr);
 		IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_gsi_ptr);
 	}
-
+#endif
 	ipa_reg_save_anomaly_check();
 
 	IPAERR("Completed\n");
@@ -1493,13 +1517,15 @@ int ipa_reg_save_init(u32 value)
 		 i++)
 		*(ipa_regs_to_save_array[num_regs + i].dst_addr) = 0x0;
 
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_1)
+	return 0;
+#else
 	ipa_reg_save.ipa.ipa_gsi_ptr  = NULL;
 	ipa_reg_save.ipa.ipa_seq_ptr  = NULL;
 	ipa_reg_save.ipa.ipa_hram_ptr = NULL;
 	ipa_reg_save.ipa.ipa_mbox_ptr = NULL;
 	ipa_reg_save.ipa.ipa_sram_ptr = NULL;
 	ipa_reg_save.ipa.ipa_iu_ptr   = NULL;
-
 	if (ipa3_ctx->do_ram_collection_on_crash) {
 		ipa_reg_save.ipa.ipa_iu_ptr =
 			alloc_and_init(IPA_IU_SIZE, value);
@@ -1543,7 +1569,6 @@ int ipa_reg_save_init(u32 value)
 			goto alloc_fail2;
 		}
 	}
-
 	return 0;
 
 alloc_fail2:
@@ -1553,6 +1578,7 @@ alloc_fail2:
 	kfree(ipa_reg_save.ipa.ipa_sram_ptr);
 	kfree(ipa_reg_save.ipa.ipa_iu_ptr);
 	iounmap(ipa3_ctx->reg_collection_base);
+#endif
 alloc_fail1:
 	return -ENOMEM;
 }

drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
  */
 #if !defined(_IPA_REG_DUMP_H_)
 #define _IPA_REG_DUMP_H_
@@ -247,12 +247,12 @@ struct map_src_dst_addr_s {
  * indexed register
  */
 #define IPA_REG_SAVE_CFG_ENTRY_GEN_EE(reg_name, var_name) \
-	({ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
 		(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_Q6_EE].var_name }, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \
 		(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_A7_EE].var_name }, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_HWP_EE), \
-		(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name })
+		(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name }
 
 #define IPA_REG_SAVE_CFG_ENTRY_GSI_FIFO(reg_name, var_name, index) \
 	{ GEN_SCALER_REG_OFST(reg_name), \
@@ -270,7 +270,7 @@ struct map_src_dst_addr_s {
  * group register
  */
 #define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(reg_name, var_name) \
-	({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
 		(u32 *)&ipa_reg_save.ipa.src_rsrc_grp[0].var_name }, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
 		(u32 *)&ipa_reg_save.ipa.src_rsrc_grp[1].var_name }, \
@@ -279,24 +279,24 @@ struct map_src_dst_addr_s {
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \
 		(u32 *)&ipa_reg_save.ipa.src_rsrc_grp[3].var_name }, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 4), \
-		(u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name })
+		(u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name }
 
 /*
  * Macro to define a particular register cfg entry for all resource
  * group register
  */
 #define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(reg_name, var_name) \
-	({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
 		(u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[0].var_name }, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
-		(u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name })
+		(u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name }
 
 /*
  * Macro to define a particular register cfg entry for all source
  * resource group count register
  */
 #define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(reg_name, var_name) \
-	({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
 		(u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[0].var_name }, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
 		(u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[1].var_name }, \
@@ -305,142 +305,41 @@ struct map_src_dst_addr_s {
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \
 		(u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[3].var_name }, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 4), \
-		(u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name })
+		(u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name }
 
 /*
  * Macro to define a particular register cfg entry for all dest
  * resource group count register
  */
 #define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(reg_name, var_name) \
-	({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
 		(u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[0].var_name }, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
-		(u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name })
-
-#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \
-	({ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \
-		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \
-	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
-		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \
-	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \
-		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].\
-			var_name })
-
-/*
- * Macro to define a particular register cfg entry for all GSI EE
- * register
- */
-#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \
-	({ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[15].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[16].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[17].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[18].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1),	\
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
-		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name })
-
-#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \
-	({ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[12].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[13].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[14].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[15].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[16].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[17].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
-		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name })
+		(u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name }
 
 /*
  * Macro to define a particular register cfg entry for GSI QSB debug
  * registers
  */
 #define IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG(reg_name, var_name) \
-	({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
 		(u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[0] }, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
 		(u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[1] }, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 2), \
 		(u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[2] }, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \
-		(u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[3] })
+		(u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[3] }
 
 #define IPA_REG_SAVE_RX_SPLT_CMDQ(reg_name, var_name) \
-	({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
+	{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
 		(u32 *)&ipa_reg_save.ipa.dbg.var_name[0]}, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
 		(u32 *)&ipa_reg_save.ipa.dbg.var_name[1]}, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 2), \
 		(u32 *)&ipa_reg_save.ipa.dbg.var_name[2]}, \
 	{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \
-		(u32 *)&ipa_reg_save.ipa.dbg.var_name[3]})
+		(u32 *)&ipa_reg_save.ipa.dbg.var_name[3]}
 
 /*
  * IPA HW Platform Type
@@ -448,6 +347,7 @@ struct map_src_dst_addr_s {
 enum ipa_hw_ee_e {
 	IPA_HW_A7_EE  = 0, /* A7's execution environment */
 	IPA_HW_Q6_EE  = 1, /* Q6's execution environment */
+	IPA_HW_UC_EE  = 2, /* UC's execution environment */
 	IPA_HW_HWP_EE = 3, /* HWP's execution environment */
 	IPA_HW_EE_MAX,     /* Max EE to support */
 };
@@ -471,10 +371,21 @@ struct ipa_gen_regs_s {
 	  ipa_state_aggr_active;
 	struct ipa_hwio_def_ipa_state_dfetcher_s
 	  ipa_state_dfetcher;
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	struct ipa_hwio_def_ipa_state_fetcher_mask_0_s
 	  ipa_state_fetcher_mask_0;
 	struct ipa_hwio_def_ipa_state_fetcher_mask_1_s
 	  ipa_state_fetcher_mask_1;
+#else
+	struct ipa_hwio_def_ipa_gsi_conf_s
+	  ipa_gsi_conf;
+	struct ipa_hwio_def_ipa_state_fetcher_mask_s
+	  ipa_state_fetcher_mask;
+	struct ipa_hwio_def_ipa_tag_timer_s
+	  ipa_tag_timer;
+	struct ipa_hwio_def_ipa_bcr_s
+	  ipa_bcr;
+#endif
 	struct ipa_hwio_def_ipa_state_gsi_aos_s
 	  ipa_state_gsi_aos;
 	struct ipa_hwio_def_ipa_state_gsi_if_s
@@ -551,6 +462,7 @@ struct ipa_gen_regs_s {
 	  ipa_rsrc_grp_cfg;
 	struct ipa_hwio_def_ipa_comp_cfg_s
 	  ipa_comp_cfg;
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	struct ipa_hwio_def_ipa_state_dpl_fifo_s
 	  ipa_state_dpl_fifo;
 	struct ipa_hwio_def_ipa_pipeline_disable_s
@@ -577,6 +489,7 @@ struct ipa_gen_regs_s {
 	  ipa_nlo_vp_dsm_open;
 	struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s
 	  ipa_nlo_vp_qbap_open;
+#endif
 };
 
 /*
@@ -726,8 +639,10 @@ struct ipa_reg_save_dbg_s {
 	  ipa_debug_data;
 	struct ipa_hwio_def_ipa_step_mode_status_s
 	  ipa_step_mode_status;
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	struct ipa_hwio_def_ipa_step_mode_breakpoints_s
 	  ipa_step_mode_breakpoints;
+#endif
 	struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s
 	  ipa_rx_splt_cmdq_cmd_n[IPA_RX_SPLT_CMDQ_MAX];
 	struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s
@@ -854,8 +769,10 @@ struct ipa_reg_save_src_rsrc_grp_s {
 	  ipa_src_rsrc_grp_01_rsrc_type_n;
 	struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s
 	  ipa_src_rsrc_grp_23_rsrc_type_n;
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s
 	  ipa_src_rsrc_grp_45_rsrc_type_n;
+#endif
 };
 
 /* Source Resource Group IPA register save data struct */
@@ -864,24 +781,30 @@ struct ipa_reg_save_dst_rsrc_grp_s {
 	  ipa_dst_rsrc_grp_01_rsrc_type_n;
 	struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s
 	  ipa_dst_rsrc_grp_23_rsrc_type_n;
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s
 	  ipa_dst_rsrc_grp_45_rsrc_type_n;
+#endif
 };
 
 /* Source Resource Group Count IPA register save data struct */
 struct ipa_reg_save_src_rsrc_cnt_s {
 	struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s
 	  ipa_src_rsrc_grp_0123_rsrc_type_cnt_n;
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s
 	  ipa_src_rsrc_grp_4567_rsrc_type_cnt_n;
+#endif
 };
 
 /* Destination Resource Group Count IPA register save data struct */
 struct ipa_reg_save_dst_rsrc_cnt_s {
 	struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s
 	  ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n;
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s
 	  ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n;
+#endif
 };
 
 /* GSI General register save data struct */
@@ -984,6 +907,7 @@ static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = {
 	HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR,
 	HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_0,
 	HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_1,
+#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
 	HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_2,
 	HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_1,
 	HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_2,
@@ -992,6 +916,7 @@ static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = {
 	HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_3,
 	HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TLV_0,
 	HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_8,
+#endif
 };
 
 /*