mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner: "This update provides: - Yet another two irq controller chip drivers - A few updates and fixes for GICV3 - A resource managed function for interrupt allocation - Fixes, updates and enhancements all over the place" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/qcom: Fix error handling genirq: Clarify logic calculating bogus irqreturn_t values genirq/msi: Add stubs for get_cached_msi_msg/pci_write_msi_msg genirq/devres: Use dev_name(dev) as default for devname genirq: Fix /proc/interrupts output alignment irqdesc: Add a resource managed version of irq_alloc_descs() irqchip/gic-v3-its: Zero command on allocation irqchip/gic-v3-its: Fix command buffer allocation irqchip/mips-gic: Fix local interrupts irqchip: Add a driver for Cortina Gemini irqchip: DT bindings for Cortina Gemini irqchip irqchip/gic-v3: Remove duplicate definition of GICD_TYPER_LPIS irqchip/gic-v3-its: Rename MAPVI to MAPTI irqchip/gic-v3-its: Drop deprecated GITS_BASER_TYPE_CPU irqchip/gic-v3-its: Refactor command encoding irqchip/gic-v3-its: Enable cacheable attribute Read-allocate hints irqchip/qcom: Add IRQ combiner driver ACPI: Add support for ResourceSource/IRQ domain mapping ACPI: Generic GSI: Do not attempt to map non-GSI IRQs during bus scan irq/platform-msi: Fix comment about maximal MSIs
This commit is contained in:
Linus Torvalds
commit
1cd4027cfe
21 changed files with 1027 additions and 149 deletions
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@ -283,3 +283,12 @@ config EZNPS_GIC
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config STM32_EXTI
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bool
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select IRQ_DOMAIN
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config QCOM_IRQ_COMBINER
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bool "QCOM IRQ combiner support"
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depends on ARCH_QCOM && ACPI
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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help
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Say yes here to add support for the IRQ combiner devices embedded
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in Qualcomm Technologies chips.
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@ -6,6 +6,7 @@ obj-$(CONFIG_ATH79) += irq-ath79-misc.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
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obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
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obj-$(CONFIG_ARCH_GEMINI) += irq-gemini.o
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obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
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obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o
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obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
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@ -75,3 +76,4 @@ obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
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obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
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obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
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obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
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obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
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185
drivers/irqchip/irq-gemini.c
Normal file
185
drivers/irqchip/irq-gemini.c
Normal file
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@ -0,0 +1,185 @@
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/*
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* irqchip for the Cortina Systems Gemini Copyright (C) 2017 Linus
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* Walleij <linus.walleij@linaro.org>
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*
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* Based on arch/arm/mach-gemini/irq.c
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* Copyright (C) 2001-2006 Storlink, Corp.
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*/
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/versatile-fpga.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/cpu.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#define GEMINI_NUM_IRQS 32
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#define GEMINI_IRQ_SOURCE(base_addr) (base_addr + 0x00)
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#define GEMINI_IRQ_MASK(base_addr) (base_addr + 0x04)
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#define GEMINI_IRQ_CLEAR(base_addr) (base_addr + 0x08)
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#define GEMINI_IRQ_MODE(base_addr) (base_addr + 0x0C)
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#define GEMINI_IRQ_POLARITY(base_addr) (base_addr + 0x10)
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#define GEMINI_IRQ_STATUS(base_addr) (base_addr + 0x14)
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#define GEMINI_FIQ_SOURCE(base_addr) (base_addr + 0x20)
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#define GEMINI_FIQ_MASK(base_addr) (base_addr + 0x24)
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#define GEMINI_FIQ_CLEAR(base_addr) (base_addr + 0x28)
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#define GEMINI_FIQ_MODE(base_addr) (base_addr + 0x2C)
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#define GEMINI_FIQ_POLARITY(base_addr) (base_addr + 0x30)
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#define GEMINI_FIQ_STATUS(base_addr) (base_addr + 0x34)
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/**
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* struct gemini_irq_data - irq data container for the Gemini IRQ controller
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* @base: memory offset in virtual memory
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* @chip: chip container for this instance
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* @domain: IRQ domain for this instance
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*/
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struct gemini_irq_data {
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void __iomem *base;
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struct irq_chip chip;
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struct irq_domain *domain;
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};
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static void gemini_irq_mask(struct irq_data *d)
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{
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struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
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unsigned int mask;
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mask = readl(GEMINI_IRQ_MASK(g->base));
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mask &= ~BIT(irqd_to_hwirq(d));
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writel(mask, GEMINI_IRQ_MASK(g->base));
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}
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static void gemini_irq_unmask(struct irq_data *d)
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{
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struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
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unsigned int mask;
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mask = readl(GEMINI_IRQ_MASK(g->base));
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mask |= BIT(irqd_to_hwirq(d));
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writel(mask, GEMINI_IRQ_MASK(g->base));
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}
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static void gemini_irq_ack(struct irq_data *d)
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{
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struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
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writel(BIT(irqd_to_hwirq(d)), GEMINI_IRQ_CLEAR(g->base));
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}
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static int gemini_irq_set_type(struct irq_data *d, unsigned int trigger)
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{
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struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
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int offset = irqd_to_hwirq(d);
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u32 mode, polarity;
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mode = readl(GEMINI_IRQ_MODE(g->base));
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polarity = readl(GEMINI_IRQ_POLARITY(g->base));
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if (trigger & (IRQ_TYPE_LEVEL_HIGH)) {
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irq_set_handler_locked(d, handle_level_irq);
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/* Disable edge detection */
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mode &= ~BIT(offset);
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polarity &= ~BIT(offset);
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} else if (trigger & IRQ_TYPE_EDGE_RISING) {
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irq_set_handler_locked(d, handle_edge_irq);
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mode |= BIT(offset);
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polarity |= BIT(offset);
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} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
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irq_set_handler_locked(d, handle_edge_irq);
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mode |= BIT(offset);
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polarity &= ~BIT(offset);
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} else {
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irq_set_handler_locked(d, handle_bad_irq);
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pr_warn("GEMINI IRQ: no supported trigger selected for line %d\n",
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offset);
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}
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writel(mode, GEMINI_IRQ_MODE(g->base));
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writel(polarity, GEMINI_IRQ_POLARITY(g->base));
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return 0;
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}
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static struct irq_chip gemini_irq_chip = {
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.name = "GEMINI",
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.irq_ack = gemini_irq_ack,
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.irq_mask = gemini_irq_mask,
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.irq_unmask = gemini_irq_unmask,
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.irq_set_type = gemini_irq_set_type,
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};
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/* Local static for the IRQ entry call */
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static struct gemini_irq_data girq;
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asmlinkage void __exception_irq_entry gemini_irqchip_handle_irq(struct pt_regs *regs)
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{
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struct gemini_irq_data *g = &girq;
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int irq;
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u32 status;
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while ((status = readl(GEMINI_IRQ_STATUS(g->base)))) {
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irq = ffs(status) - 1;
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handle_domain_irq(g->domain, irq, regs);
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}
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}
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static int gemini_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct gemini_irq_data *g = d->host_data;
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irq_set_chip_data(irq, g);
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/* All IRQs should set up their type, flags as bad by default */
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irq_set_chip_and_handler(irq, &gemini_irq_chip, handle_bad_irq);
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irq_set_probe(irq);
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return 0;
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}
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static void gemini_irqdomain_unmap(struct irq_domain *d, unsigned int irq)
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{
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops gemini_irqdomain_ops = {
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.map = gemini_irqdomain_map,
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.unmap = gemini_irqdomain_unmap,
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.xlate = irq_domain_xlate_onetwocell,
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};
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int __init gemini_of_init_irq(struct device_node *node,
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struct device_node *parent)
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{
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struct gemini_irq_data *g = &girq;
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/*
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* Disable the idle handler by default since it is buggy
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* For more info see arch/arm/mach-gemini/idle.c
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*/
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cpu_idle_poll_ctrl(true);
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g->base = of_iomap(node, 0);
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WARN(!g->base, "unable to map gemini irq registers\n");
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/* Disable all interrupts */
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writel(0, GEMINI_IRQ_MASK(g->base));
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writel(0, GEMINI_FIQ_MASK(g->base));
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g->domain = irq_domain_add_simple(node, GEMINI_NUM_IRQS, 0,
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&gemini_irqdomain_ops, g);
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set_handle_irq(gemini_irqchip_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(gemini, "cortina,gemini-interrupt-controller",
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gemini_of_init_irq);
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@ -161,7 +161,7 @@ struct its_cmd_desc {
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struct its_device *dev;
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u32 phys_id;
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u32 event_id;
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} its_mapvi_cmd;
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} its_mapti_cmd;
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struct {
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struct its_device *dev;
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@ -193,58 +193,56 @@ struct its_cmd_block {
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typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
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struct its_cmd_desc *);
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static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
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{
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u64 mask = GENMASK_ULL(h, l);
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*raw_cmd &= ~mask;
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*raw_cmd |= (val << l) & mask;
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}
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static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
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{
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cmd->raw_cmd[0] &= ~0xffULL;
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cmd->raw_cmd[0] |= cmd_nr;
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its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
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}
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static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
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{
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cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
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cmd->raw_cmd[0] |= ((u64)devid) << 32;
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its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
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}
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static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
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{
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cmd->raw_cmd[1] &= ~0xffffffffULL;
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cmd->raw_cmd[1] |= id;
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its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
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}
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static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
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{
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cmd->raw_cmd[1] &= 0xffffffffULL;
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cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
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its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
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}
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static void its_encode_size(struct its_cmd_block *cmd, u8 size)
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{
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cmd->raw_cmd[1] &= ~0x1fULL;
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cmd->raw_cmd[1] |= size & 0x1f;
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its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
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}
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static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
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{
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cmd->raw_cmd[2] &= ~0xffffffffffffULL;
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cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00ULL;
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its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 50, 8);
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}
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static void its_encode_valid(struct its_cmd_block *cmd, int valid)
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{
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cmd->raw_cmd[2] &= ~(1ULL << 63);
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cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
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its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
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}
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static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
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{
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cmd->raw_cmd[2] &= ~(0xffffffffULL << 16);
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cmd->raw_cmd[2] |= (target_addr & (0xffffffffULL << 16));
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its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 50, 16);
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}
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static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
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{
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cmd->raw_cmd[2] &= ~0xffffULL;
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cmd->raw_cmd[2] |= col;
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its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
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}
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|
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static inline void its_fixup_cmd(struct its_cmd_block *cmd)
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|
|
@ -289,18 +287,18 @@ static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
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return desc->its_mapc_cmd.col;
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}
|
||||
|
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static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
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static struct its_collection *its_build_mapti_cmd(struct its_cmd_block *cmd,
|
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struct its_cmd_desc *desc)
|
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{
|
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struct its_collection *col;
|
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|
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col = dev_event_to_col(desc->its_mapvi_cmd.dev,
|
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desc->its_mapvi_cmd.event_id);
|
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col = dev_event_to_col(desc->its_mapti_cmd.dev,
|
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desc->its_mapti_cmd.event_id);
|
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|
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its_encode_cmd(cmd, GITS_CMD_MAPVI);
|
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its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
|
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its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
|
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its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
|
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its_encode_cmd(cmd, GITS_CMD_MAPTI);
|
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its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
|
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its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
|
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its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
|
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its_encode_collection(cmd, col->col_id);
|
||||
|
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its_fixup_cmd(cmd);
|
||||
|
|
@ -413,6 +411,12 @@ static struct its_cmd_block *its_allocate_entry(struct its_node *its)
|
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if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
|
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its->cmd_write = its->cmd_base;
|
||||
|
||||
/* Clear command */
|
||||
cmd->raw_cmd[0] = 0;
|
||||
cmd->raw_cmd[1] = 0;
|
||||
cmd->raw_cmd[2] = 0;
|
||||
cmd->raw_cmd[3] = 0;
|
||||
|
||||
return cmd;
|
||||
}
|
||||
|
||||
|
|
@ -531,15 +535,15 @@ static void its_send_mapc(struct its_node *its, struct its_collection *col,
|
|||
its_send_single_command(its, its_build_mapc_cmd, &desc);
|
||||
}
|
||||
|
||||
static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id)
|
||||
static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
|
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{
|
||||
struct its_cmd_desc desc;
|
||||
|
||||
desc.its_mapvi_cmd.dev = dev;
|
||||
desc.its_mapvi_cmd.phys_id = irq_id;
|
||||
desc.its_mapvi_cmd.event_id = id;
|
||||
desc.its_mapti_cmd.dev = dev;
|
||||
desc.its_mapti_cmd.phys_id = irq_id;
|
||||
desc.its_mapti_cmd.event_id = id;
|
||||
|
||||
its_send_single_command(dev->its, its_build_mapvi_cmd, &desc);
|
||||
its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
|
||||
}
|
||||
|
||||
static void its_send_movi(struct its_device *dev,
|
||||
|
|
@ -824,7 +828,7 @@ static int __init its_alloc_lpi_tables(void)
|
|||
static const char *its_base_type_string[] = {
|
||||
[GITS_BASER_TYPE_DEVICE] = "Devices",
|
||||
[GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
|
||||
[GITS_BASER_TYPE_CPU] = "Physical CPUs",
|
||||
[GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
|
||||
[GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
|
||||
[GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
|
||||
[GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
|
||||
|
|
@ -960,7 +964,7 @@ static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser
|
|||
u32 psz, u32 *order)
|
||||
{
|
||||
u64 esz = GITS_BASER_ENTRY_SIZE(its_read_baser(its, baser));
|
||||
u64 val = GITS_BASER_InnerShareable | GITS_BASER_WaWb;
|
||||
u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
|
||||
u32 ids = its->device_ids;
|
||||
u32 new_order = *order;
|
||||
bool indirect = false;
|
||||
|
|
@ -1025,7 +1029,7 @@ static int its_alloc_tables(struct its_node *its)
|
|||
u64 typer = gic_read_typer(its->base + GITS_TYPER);
|
||||
u32 ids = GITS_TYPER_DEVBITS(typer);
|
||||
u64 shr = GITS_BASER_InnerShareable;
|
||||
u64 cache = GITS_BASER_WaWb;
|
||||
u64 cache = GITS_BASER_RaWaWb;
|
||||
u32 psz = SZ_64K;
|
||||
int err, i;
|
||||
|
||||
|
|
@ -1122,7 +1126,7 @@ static void its_cpu_init_lpis(void)
|
|||
/* set PROPBASE */
|
||||
val = (page_to_phys(gic_rdists->prop_page) |
|
||||
GICR_PROPBASER_InnerShareable |
|
||||
GICR_PROPBASER_WaWb |
|
||||
GICR_PROPBASER_RaWaWb |
|
||||
((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
|
||||
|
||||
gicr_write_propbaser(val, rbase + GICR_PROPBASER);
|
||||
|
|
@ -1147,7 +1151,7 @@ static void its_cpu_init_lpis(void)
|
|||
/* set PENDBASE */
|
||||
val = (page_to_phys(pend_page) |
|
||||
GICR_PENDBASER_InnerShareable |
|
||||
GICR_PENDBASER_WaWb);
|
||||
GICR_PENDBASER_RaWaWb);
|
||||
|
||||
gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
|
||||
tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
|
||||
|
|
@ -1498,7 +1502,7 @@ static void its_irq_domain_activate(struct irq_domain *domain,
|
|||
its_dev->event_map.col_map[event] = cpumask_first(cpu_mask);
|
||||
|
||||
/* Map the GIC IRQ and event to the device */
|
||||
its_send_mapvi(its_dev, d->hwirq, event);
|
||||
its_send_mapti(its_dev, d->hwirq, event);
|
||||
}
|
||||
|
||||
static void its_irq_domain_deactivate(struct irq_domain *domain,
|
||||
|
|
@ -1693,7 +1697,8 @@ static int __init its_probe_one(struct resource *res,
|
|||
its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
|
||||
its->numa_node = numa_node;
|
||||
|
||||
its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
|
||||
its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
|
||||
get_order(ITS_CMD_QUEUE_SZ));
|
||||
if (!its->cmd_base) {
|
||||
err = -ENOMEM;
|
||||
goto out_free_its;
|
||||
|
|
@ -1711,7 +1716,7 @@ static int __init its_probe_one(struct resource *res,
|
|||
goto out_free_tables;
|
||||
|
||||
baser = (virt_to_phys(its->cmd_base) |
|
||||
GITS_CBASER_WaWb |
|
||||
GITS_CBASER_RaWaWb |
|
||||
GITS_CBASER_InnerShareable |
|
||||
(ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
|
||||
GITS_CBASER_VALID);
|
||||
|
|
@ -1751,7 +1756,7 @@ static int __init its_probe_one(struct resource *res,
|
|||
out_free_tables:
|
||||
its_free_tables(its);
|
||||
out_free_cmd:
|
||||
kfree(its->cmd_base);
|
||||
free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
|
||||
out_free_its:
|
||||
kfree(its);
|
||||
out_unmap:
|
||||
|
|
|
|||
|
|
@ -968,6 +968,34 @@ static struct irq_domain_ops gic_ipi_domain_ops = {
|
|||
.match = gic_ipi_domain_match,
|
||||
};
|
||||
|
||||
static void __init gic_map_single_int(struct device_node *node,
|
||||
unsigned int irq)
|
||||
{
|
||||
unsigned int linux_irq;
|
||||
struct irq_fwspec local_int_fwspec = {
|
||||
.fwnode = &node->fwnode,
|
||||
.param_count = 3,
|
||||
.param = {
|
||||
[0] = GIC_LOCAL,
|
||||
[1] = irq,
|
||||
[2] = IRQ_TYPE_NONE,
|
||||
},
|
||||
};
|
||||
|
||||
if (!gic_local_irq_is_routable(irq))
|
||||
return;
|
||||
|
||||
linux_irq = irq_create_fwspec_mapping(&local_int_fwspec);
|
||||
WARN_ON(!linux_irq);
|
||||
}
|
||||
|
||||
static void __init gic_map_interrupts(struct device_node *node)
|
||||
{
|
||||
gic_map_single_int(node, GIC_LOCAL_INT_TIMER);
|
||||
gic_map_single_int(node, GIC_LOCAL_INT_PERFCTR);
|
||||
gic_map_single_int(node, GIC_LOCAL_INT_FDC);
|
||||
}
|
||||
|
||||
static void __init __gic_init(unsigned long gic_base_addr,
|
||||
unsigned long gic_addrspace_size,
|
||||
unsigned int cpu_vec, unsigned int irqbase,
|
||||
|
|
@ -1067,6 +1095,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
|
|||
}
|
||||
|
||||
gic_basic_init();
|
||||
gic_map_interrupts(node);
|
||||
}
|
||||
|
||||
void __init gic_init(unsigned long gic_base_addr,
|
||||
|
|
|
|||
296
drivers/irqchip/qcom-irq-combiner.c
Normal file
296
drivers/irqchip/qcom-irq-combiner.c
Normal file
|
|
@ -0,0 +1,296 @@
|
|||
/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Driver for interrupt combiners in the Top-level Control and Status
|
||||
* Registers (TCSR) hardware block in Qualcomm Technologies chips.
|
||||
* An interrupt combiner in this block combines a set of interrupts by
|
||||
* OR'ing the individual interrupt signals into a summary interrupt
|
||||
* signal routed to a parent interrupt controller, and provides read-
|
||||
* only, 32-bit registers to query the status of individual interrupts.
|
||||
* The status bit for IRQ n is bit (n % 32) within register (n / 32)
|
||||
* of the given combiner. Thus, each combiner can be described as a set
|
||||
* of register offsets and the number of IRQs managed.
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "QCOM80B1:" fmt
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#define REG_SIZE 32
|
||||
|
||||
struct combiner_reg {
|
||||
void __iomem *addr;
|
||||
unsigned long enabled;
|
||||
};
|
||||
|
||||
struct combiner {
|
||||
struct irq_domain *domain;
|
||||
int parent_irq;
|
||||
u32 nirqs;
|
||||
u32 nregs;
|
||||
struct combiner_reg regs[0];
|
||||
};
|
||||
|
||||
static inline int irq_nr(u32 reg, u32 bit)
|
||||
{
|
||||
return reg * REG_SIZE + bit;
|
||||
}
|
||||
|
||||
/*
|
||||
* Handler for the cascaded IRQ.
|
||||
*/
|
||||
static void combiner_handle_irq(struct irq_desc *desc)
|
||||
{
|
||||
struct combiner *combiner = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
u32 reg;
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
for (reg = 0; reg < combiner->nregs; reg++) {
|
||||
int virq;
|
||||
int hwirq;
|
||||
u32 bit;
|
||||
u32 status;
|
||||
|
||||
bit = readl_relaxed(combiner->regs[reg].addr);
|
||||
status = bit & combiner->regs[reg].enabled;
|
||||
if (!status)
|
||||
pr_warn_ratelimited("Unexpected IRQ on CPU%d: (%08x %08lx %p)\n",
|
||||
smp_processor_id(), bit,
|
||||
combiner->regs[reg].enabled,
|
||||
combiner->regs[reg].addr);
|
||||
|
||||
while (status) {
|
||||
bit = __ffs(status);
|
||||
status &= ~(1 << bit);
|
||||
hwirq = irq_nr(reg, bit);
|
||||
virq = irq_find_mapping(combiner->domain, hwirq);
|
||||
if (virq > 0)
|
||||
generic_handle_irq(virq);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static void combiner_irq_chip_mask_irq(struct irq_data *data)
|
||||
{
|
||||
struct combiner *combiner = irq_data_get_irq_chip_data(data);
|
||||
struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
|
||||
|
||||
clear_bit(data->hwirq % REG_SIZE, ®->enabled);
|
||||
}
|
||||
|
||||
static void combiner_irq_chip_unmask_irq(struct irq_data *data)
|
||||
{
|
||||
struct combiner *combiner = irq_data_get_irq_chip_data(data);
|
||||
struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
|
||||
|
||||
set_bit(data->hwirq % REG_SIZE, ®->enabled);
|
||||
}
|
||||
|
||||
static struct irq_chip irq_chip = {
|
||||
.irq_mask = combiner_irq_chip_mask_irq,
|
||||
.irq_unmask = combiner_irq_chip_unmask_irq,
|
||||
.name = "qcom-irq-combiner"
|
||||
};
|
||||
|
||||
static int combiner_irq_map(struct irq_domain *domain, unsigned int irq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
irq_set_chip_and_handler(irq, &irq_chip, handle_level_irq);
|
||||
irq_set_chip_data(irq, domain->host_data);
|
||||
irq_set_noprobe(irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void combiner_irq_unmap(struct irq_domain *domain, unsigned int irq)
|
||||
{
|
||||
irq_domain_reset_irq_data(irq_get_irq_data(irq));
|
||||
}
|
||||
|
||||
static int combiner_irq_translate(struct irq_domain *d, struct irq_fwspec *fws,
|
||||
unsigned long *hwirq, unsigned int *type)
|
||||
{
|
||||
struct combiner *combiner = d->host_data;
|
||||
|
||||
if (is_acpi_node(fws->fwnode)) {
|
||||
if (WARN_ON((fws->param_count != 2) ||
|
||||
(fws->param[0] >= combiner->nirqs) ||
|
||||
(fws->param[1] & IORESOURCE_IRQ_LOWEDGE) ||
|
||||
(fws->param[1] & IORESOURCE_IRQ_HIGHEDGE)))
|
||||
return -EINVAL;
|
||||
|
||||
*hwirq = fws->param[0];
|
||||
*type = fws->param[1];
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops domain_ops = {
|
||||
.map = combiner_irq_map,
|
||||
.unmap = combiner_irq_unmap,
|
||||
.translate = combiner_irq_translate
|
||||
};
|
||||
|
||||
static acpi_status count_registers_cb(struct acpi_resource *ares, void *context)
|
||||
{
|
||||
int *count = context;
|
||||
|
||||
if (ares->type == ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
|
||||
++(*count);
|
||||
return AE_OK;
|
||||
}
|
||||
|
||||
static int count_registers(struct platform_device *pdev)
|
||||
{
|
||||
acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
|
||||
acpi_status status;
|
||||
int count = 0;
|
||||
|
||||
if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
|
||||
return -EINVAL;
|
||||
|
||||
status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
|
||||
count_registers_cb, &count);
|
||||
if (ACPI_FAILURE(status))
|
||||
return -EINVAL;
|
||||
return count;
|
||||
}
|
||||
|
||||
struct get_registers_context {
|
||||
struct device *dev;
|
||||
struct combiner *combiner;
|
||||
int err;
|
||||
};
|
||||
|
||||
static acpi_status get_registers_cb(struct acpi_resource *ares, void *context)
|
||||
{
|
||||
struct get_registers_context *ctx = context;
|
||||
struct acpi_resource_generic_register *reg;
|
||||
phys_addr_t paddr;
|
||||
void __iomem *vaddr;
|
||||
|
||||
if (ares->type != ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
|
||||
return AE_OK;
|
||||
|
||||
reg = &ares->data.generic_reg;
|
||||
paddr = reg->address;
|
||||
if ((reg->space_id != ACPI_SPACE_MEM) ||
|
||||
(reg->bit_offset != 0) ||
|
||||
(reg->bit_width > REG_SIZE)) {
|
||||
dev_err(ctx->dev, "Bad register resource @%pa\n", &paddr);
|
||||
ctx->err = -EINVAL;
|
||||
return AE_ERROR;
|
||||
}
|
||||
|
||||
vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE);
|
||||
if (!vaddr) {
|
||||
dev_err(ctx->dev, "Can't map register @%pa\n", &paddr);
|
||||
ctx->err = -ENOMEM;
|
||||
return AE_ERROR;
|
||||
}
|
||||
|
||||
ctx->combiner->regs[ctx->combiner->nregs].addr = vaddr;
|
||||
ctx->combiner->nirqs += reg->bit_width;
|
||||
ctx->combiner->nregs++;
|
||||
return AE_OK;
|
||||
}
|
||||
|
||||
static int get_registers(struct platform_device *pdev, struct combiner *comb)
|
||||
{
|
||||
acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
|
||||
acpi_status status;
|
||||
struct get_registers_context ctx;
|
||||
|
||||
if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
|
||||
return -EINVAL;
|
||||
|
||||
ctx.dev = &pdev->dev;
|
||||
ctx.combiner = comb;
|
||||
ctx.err = 0;
|
||||
|
||||
status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
|
||||
get_registers_cb, &ctx);
|
||||
if (ACPI_FAILURE(status))
|
||||
return ctx.err;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init combiner_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct combiner *combiner;
|
||||
size_t alloc_sz;
|
||||
u32 nregs;
|
||||
int err;
|
||||
|
||||
nregs = count_registers(pdev);
|
||||
if (nregs <= 0) {
|
||||
dev_err(&pdev->dev, "Error reading register resources\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
alloc_sz = sizeof(*combiner) + sizeof(struct combiner_reg) * nregs;
|
||||
combiner = devm_kzalloc(&pdev->dev, alloc_sz, GFP_KERNEL);
|
||||
if (!combiner)
|
||||
return -ENOMEM;
|
||||
|
||||
err = get_registers(pdev, combiner);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
combiner->parent_irq = platform_get_irq(pdev, 0);
|
||||
if (combiner->parent_irq <= 0) {
|
||||
dev_err(&pdev->dev, "Error getting IRQ resource\n");
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
combiner->domain = irq_domain_create_linear(pdev->dev.fwnode, combiner->nirqs,
|
||||
&domain_ops, combiner);
|
||||
if (!combiner->domain)
|
||||
/* Errors printed by irq_domain_create_linear */
|
||||
return -ENODEV;
|
||||
|
||||
irq_set_chained_handler_and_data(combiner->parent_irq,
|
||||
combiner_handle_irq, combiner);
|
||||
|
||||
dev_info(&pdev->dev, "Initialized with [p=%d,n=%d,r=%p]\n",
|
||||
combiner->parent_irq, combiner->nirqs, combiner->regs[0].addr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct acpi_device_id qcom_irq_combiner_ids[] = {
|
||||
{ "QCOM80B1", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver qcom_irq_combiner_probe = {
|
||||
.driver = {
|
||||
.name = "qcom-irq-combiner",
|
||||
.acpi_match_table = ACPI_PTR(qcom_irq_combiner_ids),
|
||||
},
|
||||
.probe = combiner_probe,
|
||||
};
|
||||
|
||||
static int __init register_qcom_irq_combiner(void)
|
||||
{
|
||||
return platform_driver_register(&qcom_irq_combiner_probe);
|
||||
}
|
||||
device_initcall(register_qcom_irq_combiner);
|
||||
Loading…
Reference in a new issue