From 1cfa55008eb3984e7d04ba6a30e10b4089ce16a2 Mon Sep 17 00:00:00 2001 From: Rakshitha Shakamuri Date: Thu, 6 Feb 2020 19:09:43 +0530 Subject: [PATCH] msm: vidc: Align buffer size calculators with num_vpp_pipes Buffer size calculators are dependent on pipe configuration of the chipset. Ex: Kona has 4 pipes and lagoon has 1 pipe. Hence aligning the buffer size calculators based on chipset specific usage of pipes. Change-Id: I8bb19efc4a80c7e17d9db3cf7d5f1151191b502e Signed-off-by: Priyanka Gujjula Signed-off-by: Rakshitha Shakamuri --- msm/vidc/msm_vidc_buffer_calculations.c | 186 +++++++++++++----------- msm/vidc/msm_vidc_buffer_calculations.h | 10 +- msm/vidc/msm_vidc_internal.h | 3 +- msm/vidc/msm_vidc_platform.c | 5 +- 4 files changed, 111 insertions(+), 93 deletions(-) diff --git a/msm/vidc/msm_vidc_buffer_calculations.c b/msm/vidc/msm_vidc_buffer_calculations.c index 3fe3860eb7ef..558b0ccea280 100644 --- a/msm/vidc/msm_vidc_buffer_calculations.c +++ b/msm/vidc/msm_vidc_buffer_calculations.c @@ -60,7 +60,6 @@ #define VENUS_DMA_ALIGNMENT BUFFER_ALIGNMENT_SIZE(256) -#define NUM_OF_VPP_PIPES 4 #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 #define MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE 64 #define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64 @@ -125,10 +124,9 @@ #define SIZE_HW_PIC(sizePerBuf) \ (NUM_HW_PIC_BUF * sizePerBuf) -#define H264_CABAC_HDR_RATIO_HD_TOT_NUM 1 /* 0.25 */ -#define H264_CABAC_HDR_RATIO_HD_TOT_DEN 4 -#define H264_CABAC_RES_RATIO_HD_TOT_NUM 3 /* 0.75 */ -#define H264_CABAC_RES_RATIO_HD_TOT_DEN 4 +#define H264_CABAC_HDR_RATIO_HD_TOT 1 +#define H264_CABAC_RES_RATIO_HD_TOT 3 + /* * some content need more bin buffer, but limit buffer * size for high resolution @@ -182,10 +180,9 @@ #define SIZE_H265D_QP(width, height) SIZE_H264D_QP(width, height) -#define H265_CABAC_HDR_RATIO_HD_TOT_NUM 1 -#define H265_CABAC_HDR_RATIO_HD_TOT_DEN 2 -#define H265_CABAC_RES_RATIO_HD_TOT_NUM 1 -#define H265_CABAC_RES_RATIO_HD_TOT_DEN 2 +#define H265_CABAC_HDR_RATIO_HD_TOT 2 +#define H265_CABAC_RES_RATIO_HD_TOT 2 + /* * some content need more bin buffer, but limit buffer size * for high resolution @@ -278,31 +275,36 @@ static inline u32 calculate_mpeg2d_scratch_size(struct msm_vidc_inst *inst, u32 width, u32 height, bool is_interlaced); static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 work_mode, u32 lcu_size); + u32 width, u32 height, u32 work_mode, u32 lcu_size, u32 num_vpp_pipes); static inline u32 calculate_h264e_scratch_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 work_mode); + u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes); static inline u32 calculate_h265e_scratch_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 work_mode); + u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes); static inline u32 calculate_vp8e_scratch_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 work_mode); + u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes); static inline u32 calculate_h264d_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled); + u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled, + u32 num_vpp_pipes); static inline u32 calculate_h265d_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled); + u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled, + u32 num_vpp_pipes); static inline u32 calculate_vp8d_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled); + u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled, + u32 num_vpp_pipes); static inline u32 calculate_vp9d_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled); + u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled, + u32 num_vpp_pipes); static inline u32 calculate_mpeg2d_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled); + u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled, + u32 num_vpp_pipes); static inline u32 calculate_h264e_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 num_ref, bool ten_bit); + u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes); static inline u32 calculate_h265e_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 num_ref, bool ten_bit); + u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes); static inline u32 calculate_vp8e_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 num_ref, bool ten_bit); + u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes); static inline u32 calculate_enc_scratch2_size(struct msm_vidc_inst *inst, u32 width, u32 height, u32 num_ref, bool ten_bit); @@ -369,14 +371,15 @@ static struct msm_vidc_enc_buff_size_calculators vp8e_calculators = { int msm_vidc_get_decoder_internal_buffer_sizes(struct msm_vidc_inst *inst) { struct msm_vidc_dec_buff_size_calculators *dec_calculators; - u32 width, height, i, out_min_count; + u32 width, height, i, out_min_count, num_vpp_pipes; struct v4l2_format *f; - if (!inst) { + if (!inst || !inst->core || !inst->core->platform_data) { d_vpr_e("%s: Instance is null!", __func__); return -EINVAL; } + num_vpp_pipes = inst->core->platform_data->num_vpp_pipes; f = &inst->fmts[INPUT_PORT].v4l2_fmt; switch (f->fmt.pix_mp.pixelformat) { case V4L2_PIX_FMT_H264: @@ -426,7 +429,8 @@ int msm_vidc_get_decoder_internal_buffer_sizes(struct msm_vidc_inst *inst) curr_req->buffer_size = dec_calculators->calculate_scratch1_size( inst, width, height, out_min_count, - is_secondary_output_mode(inst)); + is_secondary_output_mode(inst), + num_vpp_pipes); valid_buffer_type = true; } else if (curr_req->buffer_type == HAL_BUFFER_INTERNAL_PERSIST_1) { @@ -486,17 +490,18 @@ int msm_vidc_get_num_ref_frames(struct msm_vidc_inst *inst) int msm_vidc_get_encoder_internal_buffer_sizes(struct msm_vidc_inst *inst) { struct msm_vidc_enc_buff_size_calculators *enc_calculators; - u32 width, height, i, num_ref; + u32 width, height, i, num_ref, num_vpp_pipes; bool is_tenbit = false; int num_bframes; struct v4l2_ctrl *bframe; struct v4l2_format *f; - if (!inst) { + if (!inst || !inst->core || !inst->core->platform_data) { d_vpr_e("%s: Instance is null!", __func__); return -EINVAL; } + num_vpp_pipes = inst->core->platform_data->num_vpp_pipes; f = &inst->fmts[OUTPUT_PORT].v4l2_fmt; switch (f->fmt.pix_mp.pixelformat) { case V4L2_PIX_FMT_H264: @@ -537,14 +542,15 @@ int msm_vidc_get_encoder_internal_buffer_sizes(struct msm_vidc_inst *inst) curr_req->buffer_size = enc_calculators->calculate_scratch_size( inst, width, height, - inst->clk_data.work_mode); + inst->clk_data.work_mode, + num_vpp_pipes); valid_buffer_type = true; } else if (curr_req->buffer_type == HAL_BUFFER_INTERNAL_SCRATCH_1) { curr_req->buffer_size = enc_calculators->calculate_scratch1_size( inst, width, height, num_ref, - is_tenbit); + is_tenbit, num_vpp_pipes); valid_buffer_type = true; } else if (curr_req->buffer_type == HAL_BUFFER_INTERNAL_SCRATCH_2) { @@ -987,7 +993,7 @@ u32 msm_vidc_calculate_enc_output_extra_size(struct msm_vidc_inst *inst) return ALIGN(size, SZ_4K); } -static inline u32 size_vpss_lb(u32 width, u32 height) +static inline u32 size_vpss_lb(u32 width, u32 height, u32 num_vpp_pipes) { u32 vpss_4tap_top_buffer_size, vpss_div2_top_buffer_size; u32 vpss_4tap_left_buffer_size, vpss_div2_left_buffer_size; @@ -1009,7 +1015,7 @@ static inline u32 size_vpss_lb(u32 width, u32 height) opb_lb_wr_llb_uv_buffer_size = opb_lb_wr_llb_y_buffer_size = ALIGN((ALIGN(height, 16) / 2) * 64, BUFFER_ALIGNMENT_SIZE(32)); - size = NUM_OF_VPP_PIPES * 2 * (vpss_4tap_top_buffer_size + + size = num_vpp_pipes * 2 * (vpss_4tap_top_buffer_size + vpss_div2_top_buffer_size) + 2 * (vpss_4tap_left_buffer_size + vpss_div2_left_buffer_size) + @@ -1073,7 +1079,8 @@ static inline u32 size_h264d_vpp_cmd_buf(u32 height) return size; } -static inline u32 hfi_iris2_h264d_non_comv_size(u32 width, u32 height) +static inline u32 hfi_iris2_h264d_non_comv_size(u32 width, u32 height, + u32 num_vpp_pipes) { u32 size; u32 size_bse, size_vpp; @@ -1088,11 +1095,11 @@ static inline u32 hfi_iris2_h264d_non_comv_size(u32 width, u32 height) ALIGN(SIZE_H264D_LB_FE_TOP_CTRL(width, height), VENUS_DMA_ALIGNMENT) + ALIGN(SIZE_H264D_LB_FE_LEFT_CTRL(width, height), - VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES + + VENUS_DMA_ALIGNMENT) * num_vpp_pipes + ALIGN(SIZE_H264D_LB_SE_TOP_CTRL(width, height), VENUS_DMA_ALIGNMENT) + ALIGN(SIZE_H264D_LB_SE_LEFT_CTRL(width, height), - VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES + + VENUS_DMA_ALIGNMENT) * num_vpp_pipes + ALIGN(SIZE_H264D_LB_PE_TOP_DATA(width, height), VENUS_DMA_ALIGNMENT) + ALIGN(SIZE_H264D_LB_VSP_TOP(width, height), @@ -1115,10 +1122,8 @@ static inline u32 size_h264d_hw_bin_buffer(u32 width, u32 height) ((BIN_BUFFER_THRESHOLD * 3) >> 1) : ((product * 3) >> 1); - size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_HD_TOT_NUM / - H264_CABAC_HDR_RATIO_HD_TOT_DEN; - size_bin_res = size_yuv * H264_CABAC_RES_RATIO_HD_TOT_NUM / - H264_CABAC_RES_RATIO_HD_TOT_DEN; + size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_HD_TOT; + size_bin_res = size_yuv * H264_CABAC_RES_RATIO_HD_TOT; size_bin_hdr = ALIGN(size_bin_hdr, VENUS_DMA_ALIGNMENT); size_bin_res = ALIGN(size_bin_res, VENUS_DMA_ALIGNMENT); size = size_bin_hdr + size_bin_res; @@ -1132,12 +1137,10 @@ static inline u32 calculate_h264d_scratch_size(struct msm_vidc_inst *inst, u32 aligned_height = ALIGN(height, BUFFER_ALIGNMENT_SIZE(16)); u32 size = 0; - if (!is_interlaced) { + if (!is_interlaced) size = size_h264d_hw_bin_buffer(aligned_width, aligned_height); - size = size * NUM_OF_VPP_PIPES; - } else { + else size = 0; - } return size; } @@ -1185,7 +1188,8 @@ static inline u32 hfi_iris2_h265d_comv_size(u32 width, u32 height, return size; } -static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height) +static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height, + u32 num_vpp_pipes) { u32 size_bse, size_vpp; u32 size = 0; @@ -1205,9 +1209,9 @@ static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height) ALIGN(SIZE_H265D_LB_FE_TOP_CTRL(width, height), VENUS_DMA_ALIGNMENT) + ALIGN(SIZE_H265D_LB_FE_LEFT_CTRL(width, height), - VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES + + VENUS_DMA_ALIGNMENT) * num_vpp_pipes + ALIGN(SIZE_H265D_LB_SE_LEFT_CTRL(width, height), - VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES + + VENUS_DMA_ALIGNMENT) * num_vpp_pipes + ALIGN(SIZE_H265D_LB_SE_TOP_CTRL(width, height), VENUS_DMA_ALIGNMENT) + ALIGN(SIZE_H265D_LB_PE_TOP_DATA(width, height), @@ -1215,7 +1219,7 @@ static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height) ALIGN(SIZE_H265D_LB_VSP_TOP(width, height), VENUS_DMA_ALIGNMENT) + ALIGN(SIZE_H265D_LB_VSP_LEFT(width, height), - VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES + + VENUS_DMA_ALIGNMENT) * num_vpp_pipes + ALIGN(SIZE_H265D_LB_RECON_DMA_METADATA_WR(width, height), VENUS_DMA_ALIGNMENT) * 4 + ALIGN(SIZE_H265D_QP(width, height), VENUS_DMA_ALIGNMENT); @@ -1233,10 +1237,8 @@ static inline u32 size_h265d_hw_bin_buffer(u32 width, u32 height) size_yuv = (product <= BIN_BUFFER_THRESHOLD) ? ((BIN_BUFFER_THRESHOLD * 3) >> 1) : ((product * 3) >> 1); - size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_HD_TOT_NUM / - H265_CABAC_HDR_RATIO_HD_TOT_DEN; - size_bin_res = size_yuv * H265_CABAC_RES_RATIO_HD_TOT_NUM / - H265_CABAC_RES_RATIO_HD_TOT_DEN; + size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_HD_TOT; + size_bin_res = size_yuv * H265_CABAC_RES_RATIO_HD_TOT; size_bin_hdr = ALIGN(size_bin_hdr, VENUS_DMA_ALIGNMENT); size_bin_res = ALIGN(size_bin_res, VENUS_DMA_ALIGNMENT); size = size_bin_hdr + size_bin_res; @@ -1251,12 +1253,10 @@ static inline u32 calculate_h265d_scratch_size(struct msm_vidc_inst *inst, u32 aligned_height = ALIGN(height, BUFFER_ALIGNMENT_SIZE(16)); u32 size = 0; - if (!is_interlaced) { + if (!is_interlaced) size = size_h265d_hw_bin_buffer(aligned_width, aligned_height); - size = size * NUM_OF_VPP_PIPES; - } else { + else size = 0; - } return size; } @@ -1299,7 +1299,7 @@ static inline u32 calculate_mpeg2d_scratch_size(struct msm_vidc_inst *inst, } static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 work_mode, u32 lcu_size) + u32 width, u32 height, u32 work_mode, u32 lcu_size, u32 num_vpp_pipes) { u32 aligned_width, aligned_height, bitstream_size; u32 total_bitbin_buffers = 0, size_singlePipe, bitbin_size = 0; @@ -1319,7 +1319,10 @@ static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst, bitstream_size = aligned_width * aligned_height * 3; bitbin_size = ALIGN(bitstream_size, VENUS_DMA_ALIGNMENT); } - size_singlePipe = bitbin_size / 2; + if (num_vpp_pipes > 2) + size_singlePipe = bitbin_size / 2; + else + size_singlePipe = bitbin_size; if (inst->rc_type == RATE_CONTROL_LOSSLESS) size_singlePipe <<= 1; size_singlePipe = ALIGN(size_singlePipe, VENUS_DMA_ALIGNMENT); @@ -1328,7 +1331,7 @@ static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst, padded_bin_size = ALIGN(size_singlePipe, VENUS_DMA_ALIGNMENT); size_singlePipe = sao_bin_buffer_size + padded_bin_size; size_singlePipe = ALIGN(size_singlePipe, VENUS_DMA_ALIGNMENT); - bitbin_size = size_singlePipe * NUM_OF_VPP_PIPES; + bitbin_size = size_singlePipe * num_vpp_pipes; size = ALIGN(bitbin_size, VENUS_DMA_ALIGNMENT) * total_bitbin_buffers + 512; @@ -1336,50 +1339,56 @@ static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst, } static inline u32 calculate_h264e_scratch_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 work_mode) + u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes) { - return calculate_enc_scratch_size(inst, width, height, work_mode, 16); + return calculate_enc_scratch_size(inst, width, height, work_mode, 16, + num_vpp_pipes); } static inline u32 calculate_h265e_scratch_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 work_mode) + u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes) { - return calculate_enc_scratch_size(inst, width, height, work_mode, 32); + return calculate_enc_scratch_size(inst, width, height, work_mode, 32, + num_vpp_pipes); } static inline u32 calculate_vp8e_scratch_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 work_mode) + u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes) { - return calculate_enc_scratch_size(inst, width, height, work_mode, 16); + return calculate_enc_scratch_size(inst, width, height, work_mode, 16, + num_vpp_pipes); } static inline u32 calculate_h264d_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled) + u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled, + u32 num_vpp_pipes) { u32 co_mv_size = 0, nonco_mv_size = 0; u32 vpss_lb_size = 0; u32 size = 0; co_mv_size = hfi_iris2_h264d_comv_size(width, height, min_buf_count); - nonco_mv_size = hfi_iris2_h264d_non_comv_size(width, height); + nonco_mv_size = hfi_iris2_h264d_non_comv_size(width, height, + num_vpp_pipes); if (split_mode_enabled) - vpss_lb_size = size_vpss_lb(width, height); - + vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes); size = co_mv_size + nonco_mv_size + vpss_lb_size; return size; } static inline u32 calculate_h265d_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled) + u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled, + u32 num_vpp_pipes) { u32 co_mv_size = 0, nonco_mv_size = 0; u32 vpss_lb_size = 0; u32 size = 0; co_mv_size = hfi_iris2_h265d_comv_size(width, height, min_buf_count); - nonco_mv_size = hfi_iris2_h265d_non_comv_size(width, height); + nonco_mv_size = + hfi_iris2_h265d_non_comv_size(width, height, num_vpp_pipes); if (split_mode_enabled) - vpss_lb_size = size_vpss_lb(width, height); + vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes); size = co_mv_size + nonco_mv_size + vpss_lb_size + HDR10_HIST_EXTRADATA_SIZE; @@ -1393,16 +1402,17 @@ static inline u32 hfi_iris2_vp8d_comv_size(u32 width, u32 height, } static inline u32 calculate_vp8d_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled) + u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled, + u32 num_vpp_pipes) { u32 vpss_lb_size = 0; u32 size = 0; size = hfi_iris2_vp8d_comv_size(width, height, 0); size += ALIGN(SIZE_VPXD_LB_FE_LEFT_CTRL(width, height), - VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES + + VENUS_DMA_ALIGNMENT) * num_vpp_pipes + ALIGN(SIZE_VPXD_LB_SE_LEFT_CTRL(width, height), - VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES + + VENUS_DMA_ALIGNMENT) * num_vpp_pipes + ALIGN(SIZE_VP8D_LB_VSP_TOP(width, height), VENUS_DMA_ALIGNMENT) + ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height), @@ -1416,22 +1426,23 @@ static inline u32 calculate_vp8d_scratch1_size(struct msm_vidc_inst *inst, ALIGN(SIZE_VP8D_LB_FE_TOP_DATA(width, height), VENUS_DMA_ALIGNMENT); if (split_mode_enabled) - vpss_lb_size = size_vpss_lb(width, height); + vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes); size += vpss_lb_size; return size; } static inline u32 calculate_vp9d_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled) + u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled, + u32 num_vpp_pipes) { u32 vpss_lb_size = 0; u32 size = 0; size = ALIGN(SIZE_VPXD_LB_FE_LEFT_CTRL(width, height), - VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES + + VENUS_DMA_ALIGNMENT) * num_vpp_pipes + ALIGN(SIZE_VPXD_LB_SE_LEFT_CTRL(width, height), - VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES + + VENUS_DMA_ALIGNMENT) * num_vpp_pipes + ALIGN(SIZE_VP9D_LB_VSP_TOP(width, height), VENUS_DMA_ALIGNMENT) + ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height), @@ -1445,22 +1456,23 @@ static inline u32 calculate_vp9d_scratch1_size(struct msm_vidc_inst *inst, ALIGN(SIZE_VP9D_LB_FE_TOP_DATA(width, height), VENUS_DMA_ALIGNMENT); if (split_mode_enabled) - vpss_lb_size = size_vpss_lb(width, height); + vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes); size += vpss_lb_size + HDR10_HIST_EXTRADATA_SIZE; return size; } static inline u32 calculate_mpeg2d_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled) + u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled, + u32 num_vpp_pipes) { u32 vpss_lb_size = 0; u32 size = 0; size = ALIGN(SIZE_VPXD_LB_FE_LEFT_CTRL(width, height), - VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES + + VENUS_DMA_ALIGNMENT) * num_vpp_pipes + ALIGN(SIZE_VPXD_LB_SE_LEFT_CTRL(width, height), - VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES + + VENUS_DMA_ALIGNMENT) * num_vpp_pipes + ALIGN(SIZE_VP8D_LB_VSP_TOP(width, height), VENUS_DMA_ALIGNMENT) + ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height), @@ -1474,7 +1486,7 @@ static inline u32 calculate_mpeg2d_scratch1_size(struct msm_vidc_inst *inst, ALIGN(SIZE_VP8D_LB_FE_TOP_DATA(width, height), VENUS_DMA_ALIGNMENT); if (split_mode_enabled) - vpss_lb_size = size_vpss_lb(width, height); + vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes); size += vpss_lb_size; return size; @@ -1630,27 +1642,27 @@ static inline u32 calculate_enc_scratch1_size(struct msm_vidc_inst *inst, } static inline u32 calculate_h264e_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 num_ref, bool ten_bit) + u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes) { return calculate_enc_scratch1_size(inst, width, height, 16, - num_ref, ten_bit, NUM_OF_VPP_PIPES, false); + num_ref, ten_bit, num_vpp_pipes, false); } static inline u32 calculate_h265e_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 num_ref, bool ten_bit) + u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes) { return calculate_enc_scratch1_size(inst, width, height, 32, - num_ref, ten_bit, NUM_OF_VPP_PIPES, true); + num_ref, ten_bit, num_vpp_pipes, true); } static inline u32 calculate_vp8e_scratch1_size(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 num_ref, bool ten_bit) + u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes) { + (void)num_vpp_pipes; return calculate_enc_scratch1_size(inst, width, height, 16, num_ref, ten_bit, 1, false); } - static inline u32 hfi_ubwc_calc_metadata_plane_stride(u32 width, u32 metadata_stride_multi, u32 tile_width_pels) { diff --git a/msm/vidc/msm_vidc_buffer_calculations.h b/msm/vidc/msm_vidc_buffer_calculations.h index 2583a5e54b24..a94bc485e32b 100644 --- a/msm/vidc/msm_vidc_buffer_calculations.h +++ b/msm/vidc/msm_vidc_buffer_calculations.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef __H_MSM_VIDC_BUFFER_MEM_DEFS_H__ @@ -14,15 +14,17 @@ struct msm_vidc_dec_buff_size_calculators { u32 (*calculate_scratch_size)(struct msm_vidc_inst *inst, u32 width, u32 height, bool is_interlaced); u32 (*calculate_scratch1_size)(struct msm_vidc_inst *inst, u32 width, - u32 height, u32 min_buf_count, bool split_mode_enabled); + u32 height, u32 min_buf_count, bool split_mode_enabled, + u32 num_vpp_pipes); u32 (*calculate_persist1_size)(void); }; struct msm_vidc_enc_buff_size_calculators { u32 (*calculate_scratch_size)(struct msm_vidc_inst *inst, u32 width, - u32 height, u32 work_mode); + u32 height, u32 work_mode, u32 num_vpp_pipes); u32 (*calculate_scratch1_size)(struct msm_vidc_inst *inst, - u32 width, u32 height, u32 num_ref, bool ten_bit); + u32 width, u32 height, u32 num_ref, bool ten_bit, + u32 num_vpp_pipes); u32 (*calculate_scratch2_size)(struct msm_vidc_inst *inst, u32 width, u32 height, u32 num_ref, bool ten_bit); u32 (*calculate_persist_size)(void); diff --git a/msm/vidc/msm_vidc_internal.h b/msm/vidc/msm_vidc_internal.h index 486aed03fa74..33bbd0b24e00 100644 --- a/msm/vidc/msm_vidc_internal.h +++ b/msm/vidc/msm_vidc_internal.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. */ #ifndef _MSM_VIDC_INTERNAL_H_ @@ -294,6 +294,7 @@ struct msm_vidc_platform_data { unsigned int efuse_data_length; unsigned int sku_version; uint32_t vpu_ver; + uint32_t num_vpp_pipes; struct msm_vidc_ubwc_config_data *ubwc_config; }; diff --git a/msm/vidc/msm_vidc_platform.c b/msm/vidc/msm_vidc_platform.c index 92e120ba7628..9c71ba390339 100644 --- a/msm/vidc/msm_vidc_platform.c +++ b/msm/vidc/msm_vidc_platform.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -552,6 +552,7 @@ static struct msm_vidc_platform_data default_data = { .efuse_data_length = 0, .sku_version = 0, .vpu_ver = VPU_VERSION_IRIS2, + .num_vpp_pipes = 0x4, .ubwc_config = 0x0, }; @@ -567,6 +568,7 @@ static struct msm_vidc_platform_data lahaina_data = { .efuse_data_length = 0, .sku_version = 0, .vpu_ver = VPU_VERSION_IRIS2, + .num_vpp_pipes = 0x4, .ubwc_config = lahaina_ubwc_data, .codecs = default_codecs, .codecs_count = ARRAY_SIZE(default_codecs), @@ -586,6 +588,7 @@ static struct msm_vidc_platform_data bengal_data = { .efuse_data_length = 0, .sku_version = 0, .vpu_ver = VPU_VERSION_AR50_LITE, + .num_vpp_pipes = 0x1, .ubwc_config = 0x0, .codecs = bengal_codecs, .codecs_count = ARRAY_SIZE(bengal_codecs),