diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index e3444c2f59b8..5308b0c758cf 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -83,6 +83,11 @@ #define PCIE20_LINK_DOWN_AXI_ECAM_BLOCK_STATUS (0x630) #define PCIE20_PARF_STATUS (0x230) +#define PCIE20_PARF_DEBUG_CNT_IN_L0S (0xc10) +#define PCIE20_PARF_DEBUG_CNT_IN_L1 (0xc0c) +#define PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L1 (0xc84) +#define PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L2 (0xc88) + #define PCIE20_PARF_CLKREQ_OVERRIDE (0x2b0) #define PCIE20_PARF_CLKREQ_IN_VALUE (BIT(3)) #define PCIE20_PARF_CLKREQ_IN_ENABLE (BIT(1)) @@ -2136,6 +2141,36 @@ static ssize_t enumerate_store(struct device *dev, } static DEVICE_ATTR_WO(enumerate); +static ssize_t aspm_stat_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct msm_pcie_dev_t *pcie_dev = dev_get_drvdata(dev); + + if (!pcie_dev->mhi) + return scnprintf(buf, PAGE_SIZE, + "PCIe: RC%d: No dev or MHI space found\n", + pcie_dev->rc_idx); + + if (pcie_dev->link_status != MSM_PCIE_LINK_ENABLED) + return scnprintf(buf, PAGE_SIZE, + "PCIe: RC%d: registers are not accessible\n", + pcie_dev->rc_idx); + + return scnprintf(buf, PAGE_SIZE, + "PCIe: RC%d: L0s: %u L1: %u L1.1: %u L1.2: %u\n", + pcie_dev->rc_idx, + readl_relaxed(pcie_dev->mhi + + PCIE20_PARF_DEBUG_CNT_IN_L0S), + readl_relaxed(pcie_dev->mhi + + PCIE20_PARF_DEBUG_CNT_IN_L1), + readl_relaxed(pcie_dev->mhi + + PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L1), + readl_relaxed(pcie_dev->mhi + + PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L2)); +} +static DEVICE_ATTR_RO(aspm_stat); + static ssize_t l23_rdy_poll_timeout_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2170,6 +2205,7 @@ static DEVICE_ATTR_RW(l23_rdy_poll_timeout); static struct attribute *msm_pcie_debug_attrs[] = { &dev_attr_link_check_max_count.attr, &dev_attr_enumerate.attr, + &dev_attr_aspm_stat.attr, &dev_attr_l23_rdy_poll_timeout.attr, NULL, };