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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (21 commits) x86/PCI: use dev_printk when possible PCI: add D3 power state avoidance quirk PCI: fix bogus "'device' may be used uninitialized" warning in pci_slot PCI: add an option to allow ASPM enabled forcibly PCI: disable ASPM on pre-1.1 PCIe devices PCI: disable ASPM per ACPI FADT setting PCI MSI: Don't disable MSIs if the mask bit isn't supported PCI: handle 64-bit resources better on 32-bit machines PCI: rewrite PCI BAR reading code PCI: document pci_target_state PCI hotplug: fix typo in pcie hotplug output x86 gart: replace to_pages macro with iommu_num_pages x86, AMD IOMMU: replace to_pages macro with iommu_num_pages iommu: add iommu_num_pages helper function dma-coherent: add documentation to new interfaces Cris: convert to using generic dma-coherent mem allocator Sh: use generic per-device coherent dma allocator ARM: support generic per-device coherent dma mem Generic dma-coherent: fix DMA_MEMORY_EXCLUSIVE x86: use generic per-device dma coherent allocator ...
This commit is contained in:
commit
1d9b9f6a53
36 changed files with 512 additions and 568 deletions
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@ -277,6 +277,7 @@ enum acpi_prefered_pm_profiles {
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#define BAF_LEGACY_DEVICES 0x0001
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#define BAF_8042_KEYBOARD_CONTROLLER 0x0002
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#define BAF_MSI_NOT_SUPPORTED 0x0008
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#define BAF_PCIE_ASPM_CONTROL 0x0010
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#define FADT2_REVISION_ID 3
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#define FADT2_MINUS_REVISION_ID 2
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@ -7,6 +7,8 @@
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#include <linux/scatterlist.h>
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#include <asm-generic/dma-coherent.h>
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/*
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* DMA-consistent mapping functions. These allocate/free a region of
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* uncached, unwrite-buffered mapped memory space for use with DMA
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@ -14,6 +14,8 @@
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#ifdef CONFIG_PCI
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#include <asm-generic/dma-coherent.h>
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void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag);
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32
include/asm-generic/dma-coherent.h
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32
include/asm-generic/dma-coherent.h
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@ -0,0 +1,32 @@
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#ifndef DMA_COHERENT_H
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#define DMA_COHERENT_H
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#ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT
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/*
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* These two functions are only for dma allocator.
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* Don't use them in device drivers.
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*/
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int dma_alloc_from_coherent(struct device *dev, ssize_t size,
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dma_addr_t *dma_handle, void **ret);
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int dma_release_from_coherent(struct device *dev, int order, void *vaddr);
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/*
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* Standard interface
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*/
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#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
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extern int
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dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
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dma_addr_t device_addr, size_t size, int flags);
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extern void
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dma_release_declared_memory(struct device *dev);
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extern void *
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dma_mark_declared_memory_occupied(struct device *dev,
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dma_addr_t device_addr, size_t size);
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#else
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#define dma_alloc_from_coherent(dev, size, handle, ret) (0)
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#define dma_release_from_coherent(dev, order, vaddr) (0)
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#endif
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#endif
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@ -5,6 +5,7 @@
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#include <linux/scatterlist.h>
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#include <asm/cacheflush.h>
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#include <asm/io.h>
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#include <asm-generic/dma-coherent.h>
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extern struct bus_type pci_bus_type;
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@ -249,25 +249,5 @@ static inline int dma_get_cache_alignment(void)
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#define dma_is_consistent(d, h) (1)
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#ifdef CONFIG_X86_32
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# define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
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struct dma_coherent_mem {
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void *virt_base;
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u32 device_base;
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int size;
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int flags;
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unsigned long *bitmap;
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};
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extern int
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dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
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dma_addr_t device_addr, size_t size, int flags);
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extern void
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dma_release_declared_memory(struct device *dev);
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extern void *
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dma_mark_declared_memory_occupied(struct device *dev,
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dma_addr_t device_addr, size_t size);
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#endif /* CONFIG_X86_32 */
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#include <asm-generic/dma-coherent.h>
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#endif
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@ -8,3 +8,4 @@ extern unsigned long iommu_area_alloc(unsigned long *map, unsigned long size,
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unsigned long align_mask);
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extern void iommu_area_free(unsigned long *map, unsigned long start,
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unsigned int nr);
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extern unsigned long iommu_num_pages(unsigned long addr, unsigned long len);
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@ -27,6 +27,7 @@ extern void pcie_aspm_init_link_state(struct pci_dev *pdev);
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extern void pcie_aspm_exit_link_state(struct pci_dev *pdev);
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extern void pcie_aspm_pm_state_change(struct pci_dev *pdev);
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extern void pci_disable_link_state(struct pci_dev *pdev, int state);
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extern void pcie_no_aspm(void);
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#else
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static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
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{
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@ -40,6 +41,10 @@ static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev)
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static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
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{
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}
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static inline void pcie_no_aspm(void)
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{
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}
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#endif
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#ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
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@ -124,6 +124,8 @@ enum pci_dev_flags {
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* generation too.
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*/
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PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
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/* Device configuration is irrevocably lost if disabled into D3 */
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PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
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};
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typedef unsigned short __bitwise pci_bus_flags_t;
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@ -374,6 +374,7 @@
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#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
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#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
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#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
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#define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
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#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
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#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
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#define PCI_EXP_DEVCTL 8 /* Device Control */
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