From 1d9db2ceb70da60aad2d33ba9b5cf2cf4533175f Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 11 Nov 2020 14:50:27 -0800 Subject: [PATCH] ARM: dts: msm: add LTR entries for HSP direct connects on sdxlemur HSP requires PCIe host to have LTR programmed for LPM usecases, therefore, add the required LTR entries for PCIe on sdxlemur. Change-Id: I38f82152f2113dc59c2da89f2328d51c2d161eb8 --- qcom/sdxlemur-cdp.dtsi | 2 ++ qcom/sdxlemur-mtp-mbb.dtsi | 2 ++ qcom/sdxlemur-rcm-rc.dtsi | 2 ++ 3 files changed, 6 insertions(+) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 6b6ff3fc2a0c..fe6531308f6c 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -32,4 +32,6 @@ &pcie0 { qcom,boot-option = <0x1>; + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <70>; }; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index b0e02b918f81..4f4c9bc92f04 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -12,6 +12,8 @@ &pcie0 { qcom,boot-option = <0x1>; + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <70>; }; &sdhc_1 { diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 7e5f6471cab7..0eb9848df6f1 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -12,4 +12,6 @@ &pcie0 { qcom,boot-option = <0x1>; + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <70>; };