From a20646f28a88c6263fb399fed57a42684f0998b8 Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Fri, 7 Jan 2022 17:54:52 +0530 Subject: [PATCH 1/6] ARM: dts: qcom: Set right IRQ type to MHI interrupt Set right IRQ type property for MHI interrupt, Without this getting below warning during bootup WARNING: drivers/irqchip/irq-gic.c:gic_irq_domain_translate (gic_irq_domain_translate) (irq_create_fwspec_mapping) (irq_create_of_mapping) (of_irq_get) (__platform_get_irq_byname) (platform_get_irq_byname) (mhi_dev_probe). Change-Id: I86b3cb88ebd297d16fa0c6a27e96870845a0077b --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 7187570188f5..9f80db1850aa 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -1141,7 +1141,7 @@ qcom,mhi-ep-msi = <0>; qcom,mhi-version = <0x1000000>; qcom,use-ipa-software-channel; - interrupts = <0 145 0>; + interrupts = ; interrupt-names = "mhi-device-inta"; qcom,mhi-ifc-id = <0x030817cb>; qcom,mhi-interrupt; From 60a6dd19524dc45e4f8dc08db1e5c76d1b4bb644 Mon Sep 17 00:00:00 2001 From: Yogesh Lal Date: Thu, 12 Aug 2021 16:49:20 +0530 Subject: [PATCH 2/6] ARM: dts: msm: Add BOOT_CONFIG register offset for sdxlemur Add BOOT_CONFIG to support the EDL over PCIe for sdxlemur. Change-Id: Ia33b56d3bbb4e4bf4df1f6ac049b5b85d1938c5a --- qcom/sdxlemur-v2.dtsi | 5 +++++ qcom/sdxlemur.dtsi | 5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index f2cadc6e4814..2d9f76145127 100644 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -173,3 +173,8 @@ &pil_modem { qcom,vdd_mss-uV-uA = ; }; + + +&dload_mode { + qcom,boot-config-shift = <1 4>; +}; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 7187570188f5..84615c9ee0ed 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -196,8 +196,11 @@ }; }; - dload_mode { + dload_mode: dload_mode { compatible = "qcom,dload-mode"; + reg = <0x786070 0x4>; + reg-names = "boot-config"; + qcom,boot-config-shift = <1 3>; }; dcc: dcc_v2@117f000 { From 0a173e2445eb1e857f4bba0f371459649d8c7f0d Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Tue, 11 Jan 2022 10:55:48 +0530 Subject: [PATCH 3/6] bindings: power: reset: Add qcom-dload-mode bindings for SDX65 Add additional devicetree properties to qcom-dload-mode bindings for SDX65. Change-Id: I2671025430538c6f94c0d2a75eb6ff61f3a1b82f --- bindings/power/reset/qcom,dload-mode.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/bindings/power/reset/qcom,dload-mode.yaml b/bindings/power/reset/qcom,dload-mode.yaml index 067d6eb2b032..ce65735c956b 100644 --- a/bindings/power/reset/qcom,dload-mode.yaml +++ b/bindings/power/reset/qcom,dload-mode.yaml @@ -16,6 +16,18 @@ properties: compatible: items: - const: qcom,dload-mode + reg: + Value type: + Definition: The base address and size for reading the proper configuration + related information. + + reg-names: + Value type: string + Definition: The reg name for reading the configurations. + + qcom,boot-config-shift: + Value type: + Definition: The range of bits from low to high. required: - compatible From c8b1a887c8048e6698aa504ad021f1c24ece6bf3 Mon Sep 17 00:00:00 2001 From: Sai Chaitanya Kaveti Date: Thu, 20 Jan 2022 10:50:24 +0530 Subject: [PATCH 4/6] ARM: dts: msm: Limit the PCIe speed to Gen3 for sdxlemur Limit the PCIe speed to Gen3 for sdxlemur Change-Id: Iac2cb2b50a61f038868d0f678b9bcebd047788c1 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 463320b94b03..cc4a9bf5b24d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -977,7 +977,7 @@ qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; qcom,pcie-device-id = /bits/ 16 <0x0308>; - qcom,pcie-link-speed = <4>; + qcom,pcie-link-speed = <3>; qcom,pcie-phy-ver = <7>; qcom,pcie-active-config; qcom,pcie-aggregated-irq; From 2354537e23f501caa7a6775f6b4063f2e5045a95 Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Fri, 28 Jan 2022 22:06:03 +0530 Subject: [PATCH 5/6] ARM: dts: msm: Disable LPM States for SDXLEMUR + QCN9000 QCN9000 does not supports low power mode. This change disables LPM for SDXLEMUR + QCN9000 variants. Change-Id: I588b96b3cf2479fa098b36a07ce04cba9f04d8a8 --- qcom/sdxlemur-qcn9000.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur-qcn9000.dtsi b/qcom/sdxlemur-qcn9000.dtsi index 48709022c247..d3ec2dcd34c0 100644 --- a/qcom/sdxlemur-qcn9000.dtsi +++ b/qcom/sdxlemur-qcn9000.dtsi @@ -24,6 +24,11 @@ }; &soc { + /* If QCN9000 is connected, LPM modes are disabled */ + qcom,lpm-levels { + status = "disabled"; + }; + wifi0: qcom,cnss-qcn9000@a0000000 { status = "disabled"; compatible = "qcom,cnss-qcn9000"; From 1070b4ca120c7c33f6d9fd9cf424353b420df701 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Tue, 1 Feb 2022 23:52:28 +0530 Subject: [PATCH 6/6] ARM: dts: msm: Modify GPIO28 functionality as per pinctrl change This change modifies GPIO28 function from qup11 to qup11_f1 as per the pinctrl driver change. Depends-on CR: 3112278. Change-Id: Ie102cebddaaf6dd6985fabd0b5f43294714a0f8e --- qcom/blair-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/blair-pinctrl.dtsi b/qcom/blair-pinctrl.dtsi index 9cb472d3e943..5a916a277291 100644 --- a/qcom/blair-pinctrl.dtsi +++ b/qcom/blair-pinctrl.dtsi @@ -337,7 +337,7 @@ qupv3_se7_i2c_active: qupv3_se7_i2c_active { mux { pins = "gpio27", "gpio28"; - function = "qup11"; + function = "qup11_f1"; }; config {