diff --git a/drivers/clk/qcom/dispcc-lahaina.c b/drivers/clk/qcom/dispcc-lahaina.c index 6c144bc5242a..daa2f1897b35 100644 --- a/drivers/clk/qcom/dispcc-lahaina.c +++ b/drivers/clk/qcom/dispcc-lahaina.c @@ -24,6 +24,8 @@ #include "reset.h" #include "vdd-level.h" +static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner); + #define DISP_CC_MISC_CMD 0x8000 enum { @@ -78,6 +80,15 @@ static struct clk_alpha_pll disp_cc_pll0 = { .num_parents = 1, .ops = &clk_alpha_pll_lucid_5lpe_ops, }, + .vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1600000000, + [VDD_NOMINAL] = 2000000000}, + }, }, }; @@ -108,6 +119,15 @@ static struct clk_alpha_pll disp_cc_pll1 = { .num_parents = 1, .ops = &clk_alpha_pll_lucid_5lpe_ops, }, + .vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1600000000, + [VDD_NOMINAL] = 2000000000}, + }, }, }; @@ -262,6 +282,14 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 37500000, + [VDD_NOMINAL] = 75000000}, + }, }; static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { @@ -282,6 +310,14 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 187500000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 358000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { @@ -297,6 +333,14 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 187500000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 358000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = { @@ -312,6 +356,12 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, }; static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { @@ -327,6 +377,12 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, }; static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = { @@ -350,6 +406,14 @@ static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 270000000, + [VDD_LOW_L1] = 540000000, + [VDD_NOMINAL] = 810000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { @@ -365,6 +429,14 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 270000000, + [VDD_LOW_L1] = 540000000, + [VDD_NOMINAL] = 810000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { @@ -380,6 +452,13 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 337500000, + [VDD_NOMINAL] = 675000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { @@ -395,6 +474,13 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 337500000, + [VDD_NOMINAL] = 675000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { @@ -410,6 +496,13 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 337500000, + [VDD_NOMINAL] = 675000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = { @@ -425,6 +518,12 @@ static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, }; static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = { @@ -440,6 +539,14 @@ static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 270000000, + [VDD_LOW] = 594000000, + [VDD_NOMINAL] = 810000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { @@ -455,6 +562,14 @@ static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 337500000, + [VDD_LOW] = 371250000, + [VDD_NOMINAL] = 675000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { @@ -470,6 +585,12 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, }; static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { @@ -485,6 +606,12 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, }; static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { @@ -514,6 +641,15 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 200000000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 345000000, + [VDD_NOMINAL] = 460000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { @@ -529,6 +665,14 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 328125000, + [VDD_LOW] = 525000000, + [VDD_LOW_L1] = 625000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { @@ -544,6 +688,14 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 328125000, + [VDD_LOW] = 525000000, + [VDD_LOW_L1] = 625000000}, + }, }; static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { @@ -570,6 +722,15 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 200000000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 345000000, + [VDD_NOMINAL] = 460000000}, + }, }; static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { @@ -585,6 +746,12 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, }; static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { @@ -605,6 +772,12 @@ static struct clk_rcg2 disp_cc_sleep_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 32000}, + }, }; static struct clk_rcg2 disp_cc_xo_clk_src = { @@ -1356,9 +1529,15 @@ static int disp_cc_lahaina_probe(struct platform_device *pdev) { struct regmap *regmap; struct clk *clk; - struct regulator *regulator; int ret; + vdd_mm.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mm"); + if (IS_ERR(vdd_mm.regulator[0])) { + if (PTR_ERR(vdd_mm.regulator[0]) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_mm regulator\n"); + return PTR_ERR(vdd_mm.regulator[0]); + } + regmap = qcom_cc_map(pdev, &disp_cc_lahaina_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); @@ -1371,14 +1550,6 @@ static int disp_cc_lahaina_probe(struct platform_device *pdev) } devm_clk_put(&pdev->dev, clk); - regulator = devm_regulator_get(&pdev->dev, "vdd_mm"); - if (IS_ERR(regulator)) { - if (PTR_ERR(regulator) != -EPROBE_DEFER) - dev_err(&pdev->dev, "Unable to get vdd_mm regulator\n"); - return PTR_ERR(regulator); - } - devm_regulator_put(regulator); - clk_lucid_5lpe_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); clk_lucid_5lpe_pll_configure(&disp_cc_pll1, regmap, diff --git a/drivers/clk/qcom/videocc-lahaina.c b/drivers/clk/qcom/videocc-lahaina.c index c7e66be71f67..7de9e74b50d3 100644 --- a/drivers/clk/qcom/videocc-lahaina.c +++ b/drivers/clk/qcom/videocc-lahaina.c @@ -24,6 +24,9 @@ #include "reset.h" #include "vdd-level.h" +static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner); + enum { P_BI_TCXO, P_CHIP_SLEEP_CLK, @@ -63,6 +66,15 @@ static struct clk_alpha_pll video_pll0 = { .num_parents = 1, .ops = &clk_alpha_pll_lucid_5lpe_ops, }, + .vdd_data = { + .vdd_class = &vdd_mx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1600000000, + [VDD_NOMINAL] = 2000000000}, + }, }, }; @@ -93,6 +105,15 @@ static struct clk_alpha_pll video_pll1 = { .num_parents = 1, .ops = &clk_alpha_pll_lucid_5lpe_ops, }, + .vdd_data = { + .vdd_class = &vdd_mx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1600000000, + [VDD_NOMINAL] = 2000000000}, + }, }, }; @@ -185,6 +206,15 @@ static struct clk_rcg2 video_cc_mvs0_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 720000000, + [VDD_LOW] = 1014000000, + [VDD_LOW_L1] = 1098000000, + [VDD_NOMINAL] = 1332000000}, + }, }; static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { @@ -209,6 +239,14 @@ static struct clk_rcg2 video_cc_mvs1_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 840000000, + [VDD_LOW] = 1098000000, + [VDD_NOMINAL] = 1332000000}, + }, }; static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = { @@ -229,6 +267,12 @@ static struct clk_rcg2 video_cc_sleep_clk_src = { .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, + .clkr.vdd_data = { + .vdd_class = &vdd_mm, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 32000}, + }, }; static struct clk_rcg2 video_cc_xo_clk_src = { @@ -518,9 +562,22 @@ static int video_cc_lahaina_probe(struct platform_device *pdev) { struct regmap *regmap; struct clk *clk; - struct regulator *regulator; int ret; + vdd_mm.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mm"); + if (IS_ERR(vdd_mm.regulator[0])) { + if (PTR_ERR(vdd_mm.regulator[0]) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_mm regulator\n"); + return PTR_ERR(vdd_mm.regulator[0]); + } + + vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx"); + if (IS_ERR(vdd_mx.regulator[0])) { + if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n"); + return PTR_ERR(vdd_mx.regulator[0]); + } + regmap = qcom_cc_map(pdev, &video_cc_lahaina_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); @@ -533,14 +590,6 @@ static int video_cc_lahaina_probe(struct platform_device *pdev) } devm_clk_put(&pdev->dev, clk); - regulator = devm_regulator_get(&pdev->dev, "vdd_mm"); - if (IS_ERR(regulator)) { - if (PTR_ERR(regulator) != -EPROBE_DEFER) - dev_err(&pdev->dev, "Unable to get vdd_mm regulator\n"); - return PTR_ERR(regulator); - } - devm_regulator_put(regulator); - clk_lucid_5lpe_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_5lpe_pll_configure(&video_pll1, regmap, &video_pll1_config);