From e656f3b745f2f6f3c24d98c0229b081fd4da6cf9 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Thu, 28 Jan 2021 17:04:48 +0530 Subject: [PATCH 1/7] ARM: dts: msm: add trusted vm display dtsi files for yupik target Add trusted VM display device tree files for yupik. Change-Id: I3ecef743c38a5751d3db13ee0d4f72fc00b2b15c --- display/trustedvm-yupik-sde-display.dtsi | 26 +++++++++++ display/trustedvm-yupik-sde.dtsi | 55 ++++++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 display/trustedvm-yupik-sde-display.dtsi create mode 100644 display/trustedvm-yupik-sde.dtsi diff --git a/display/trustedvm-yupik-sde-display.dtsi b/display/trustedvm-yupik-sde-display.dtsi new file mode 100644 index 000000000000..7919d11a4a16 --- /dev/null +++ b/display/trustedvm-yupik-sde-display.dtsi @@ -0,0 +1,26 @@ +#include "yupik-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>, + <&clock_cpucc PCLK_MUX_0_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_SRC_0_CLK>, + <&clock_cpucc PCLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + qcom,panel-te-source = <0>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; +}; + + +&mdss_mdp { + connectors = <&sde_dsi>; +}; diff --git a/display/trustedvm-yupik-sde.dtsi b/display/trustedvm-yupik-sde.dtsi new file mode 100644 index 000000000000..a80a08afb696 --- /dev/null +++ b/display/trustedvm-yupik-sde.dtsi @@ -0,0 +1,55 @@ +#include "yupik-sde-common.dtsi" +#include + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>, + <0x0ae8f000 0x02c>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,sde-hw-version = <0x70020000>; + + clocks = + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc GCC_DISP_SF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_cpucc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + qcom,sde-trusted-vm-env; + qcom,vram-size = <0x200000>; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; From 8a47423d1134b21b60f352fbac6f0216cea85893 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Tue, 2 Feb 2021 11:50:23 +0530 Subject: [PATCH 2/7] ARM: dts: msm: remove display related SPMI address for yupik target Remove display related SPMI address for yupik target. Change-Id: Ic42daf564cf9ed2edcd57ccc61d6662e32f8501e --- display/yupik-sde-common.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index fcdf37a6c5d4..16846daaf579 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -193,10 +193,6 @@ qcom,sde-secure-sid-mask = <0x901 0xD01>; - /* SPMI address related to display */ - qcom,pmic-arb = <&spmi_bus>; - qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; - qcom,sde-reg-bus,vectors-KBps = <0 0>, <0 74000>, <0 148000>, From 86798cd792f0a56bfb9c7ee00f8d472442fdea08 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 2 Feb 2021 18:09:12 +0530 Subject: [PATCH 3/7] ARM: dts: msm: Add 120Hz Video mode support on yupik Add 120Hz nt36672e Video mode panel support on yupik idp platform. Also, enable DFPS and ESD feature for the panel. Change-Id: Ic8e0bf998c3ebf83fba917389754326b39bbac96 --- display/yupik-sde-display-common.dtsi | 16 ++++++++++++++++ display/yupik-sde-display-idp.dtsi | 8 ++++++++ display/yupik-sde-display.dtsi | 9 +++++++++ 3 files changed, 33 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 4412e52d98c2..237b335586e3 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -1,4 +1,5 @@ #include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-120-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" @@ -139,6 +140,21 @@ }; }; +&dsi_nt36672e_fhd_plus_120_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-supported-dfps-list = <120 60 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 + 08 08 02 04 00 1b 18]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index d3886dad50f1..4fcaf173b2b8 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -8,6 +8,14 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_nt36672e_fhd_plus_120_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 6a9ebe422387..82bc6fd4768d 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -59,6 +59,15 @@ qcom,mdss-dsi-panel-status-read-length = <1>; }; +&dsi_nt36672e_fhd_plus_120_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + &dsi_r66451_amoled_60hz_cmd_cphy { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; From 2cbef2e554e660f17f1be30d590adc9f05213e10 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Wed, 3 Feb 2021 18:22:16 +0530 Subject: [PATCH 4/7] ARM: dts: msm: enable qsync along with VRR in yupik target This change enables qsync support for yupik target along with existing VRR. Change-Id: I6c238fa1bce3102744c10b2b3a2c678773adb922 --- display/yupik-sde-display-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 237b335586e3..4de9ed87f6fa 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -130,6 +130,7 @@ qcom,dsi-supported-dfps-list = <144 120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-qsync-min-refresh-rate = <48>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 @@ -145,6 +146,7 @@ qcom,dsi-supported-dfps-list = <120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-qsync-min-refresh-rate = <48>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 From 4fb81e7ec851b51c9137592a297f0cce59abc1cc Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Fri, 5 Feb 2021 17:46:07 +0530 Subject: [PATCH 5/7] ARM: dts: msm: Add display support for r66451 120fps panel Add r66451 120fps display cphy panel support on Yupik target. Change-Id: Ia295e22add42916343e7c12b3fdd64375ebb8d08 --- display/yupik-sde-display-idp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 4fcaf173b2b8..045d7c6ac25f 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -34,6 +34,16 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_r66451_amoled_120hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_r66451_amoled_144hz_cmd_cphy { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From eb8600cf9ace74f00ca3647bf24b17bca3fc559c Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 1 Feb 2021 21:00:23 +0530 Subject: [PATCH 6/7] ARM: dts: msm: Enable Dynamic clock on yupik IDP Enable Dynamic clock for 144Hz and 120Hz Video mode panel on yupik IDP platform. Change-Id: Ic1df031247fdcc3782d3a2ce231c02524deba74e --- display/yupik-sde-display-common.dtsi | 16 ++++++++++++++-- display/yupik-sde.dtsi | 1 + 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 4de9ed87f6fa..acb348abab67 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -126,11 +126,17 @@ }; &dsi_nt36672e_fhd_plus_144_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; qcom,dsi-supported-dfps-list = <144 120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-qsync-min-refresh-rate = <48>; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <953341056 946720632 950030848>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 @@ -142,11 +148,17 @@ }; &dsi_nt36672e_fhd_plus_120_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; qcom,dsi-supported-dfps-list = <120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-qsync-min-refresh-rate = <48>; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <901327680 893816616 897572152>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index f664f6d65855..43f616b8e540 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -207,5 +207,6 @@ vdda-0p9-supply = <&L10C>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; }; From 8f91e06a17ad79ac91f833e62844291737fe8938 Mon Sep 17 00:00:00 2001 From: Chandan Uddaraju Date: Fri, 29 Jan 2021 17:35:57 -0800 Subject: [PATCH 7/7] ARM: dts: msm: add dispcc clock reference for dsi-display nodes Currently the dsi clock handles are under the dsi controller DT node. As soon as the controller probe finishes, the dispcc sync state can get called before the dsi_display probe potentially disturbing the clock votes for cont_splash use case. dsi_display adds its component to the list of components hence controlling the bind which adds the dsi clock votes. There is no separate component for the dsi_ctrl. Hence we are no longer protected by the component model in this case against the disp cc sync state getting triggered after the dsi_ctrl probe. To protect against this incorrect sync state trigger add a dummy MDP clk vote handle to the dsi_display DT node. Since the dsi_display driver does not parse MDP clock nodes, no actual vote shall be added and this change is done just to satisfy sync state requirements. Change-Id: I47c458f4f6f2937effdd1212496b41eacab4e052 --- display/lahaina-sde-display.dtsi | 41 ++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 685fd53fd828..c448cca46045 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -1,4 +1,5 @@ #include "lahaina-sde-display-common.dtsi" +#include &tlmm { display_panel_avdd_default: display_panel_avdd_default { @@ -59,7 +60,22 @@ <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 SHADOW_CPHY_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", @@ -69,7 +85,8 @@ "cphy_byte_clk1", "cphy_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", "shadow_byte_clk1", "shadow_pixel_clk1", - "shadow_cphybyte_clk1", "shadow_cphypixel_clk1"; + "shadow_cphybyte_clk1", "shadow_cphypixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -93,11 +110,27 @@ <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; + "cphy_byte_clk1", "cphy_pixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;