From 1e58fea0aec71ead347f01701f6d3d38473e48d2 Mon Sep 17 00:00:00 2001
From: "Isaac J. Manjarres" <isaacm@quicinc.com>
Date: Fri, 2 Aug 2019 12:02:49 -0700
Subject: [PATCH] ARM: dts: msm: Enable the graphics SMMU on Lahaina

Fix the size of the register space for the graphics SMMU,
and enable it, as well as the associated test devices.

Change-Id: I5963b9d5a5fb0ad1d55a1e2011ee1bfb5d961fee
---
 qcom/msm-arm-smmu-lahaina.dtsi | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/qcom/msm-arm-smmu-lahaina.dtsi b/qcom/msm-arm-smmu-lahaina.dtsi
index 832bffd3008a..45fde47e0cbe 100644
--- a/qcom/msm-arm-smmu-lahaina.dtsi
+++ b/qcom/msm-arm-smmu-lahaina.dtsi
@@ -3,7 +3,7 @@
 &soc {
 	kgsl_smmu: kgsl-smmu@3da0000 {
 		compatible = "qcom,qsmmu-v500";
-		reg = <0x3DA0000 0x10000>,
+		reg = <0x3DA0000 0x20000>,
 			<0x3DC2000 0x20>;
 		reg-names = "base", "tcu-base";
 		#iommu-cells = <2>;
@@ -13,7 +13,6 @@
 		#size-cells = <1>;
 		#address-cells = <1>;
 		ranges;
-		status = "disabled";
 
 		clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
 			 <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
@@ -43,7 +42,6 @@
 				<0x3DC2200 0x8>;
 			reg-names = "base", "status-reg";
 			qcom,stream-id-range = <0x0 0x400>;
-			status = "disabled";
 		};
 
 		gfx_1_tbu: gfx_1_tbu@3dc9000 {
@@ -52,7 +50,6 @@
 				<0x3DC2208 0x8>;
 			reg-names = "base", "status-reg";
 			qcom,stream-id-range = <0x400 0x400>;
-			status = "disabled";
 		};
 	};
 
@@ -272,14 +269,12 @@
 	};
 
 	kgsl_iommu_test_device {
-		status = "disabled";
 		compatible = "iommu-debug-test";
 		iommus = <&kgsl_smmu 0x7 0>;
 		qcom,iommu-dma = "disabled";
 	};
 
 	kgsl_iommu_coherent_test_device {
-		status = "disabled";
 		compatible = "iommu-debug-test";
 		iommus = <&kgsl_smmu 0x9 0>;
 		qcom,iommu-dma = "disabled";