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arm64: dts: Amlogic updates for v5.2, round 2
- add display/gfx support for G12a boards - enable USB for g12a boards -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAly8ghgACgkQWTcYmtP7 xmXqyg/9HtVrO5aNLEmGi3l/YySSH7fSp5BNnvTzlT8SpB1vBAKLXWjemVss2XVE QEE7d1UyUoXwgE4GoAyguuuj0Ov+JwYRTQb+OZKliALPlHfQQkklN8FKVMnDzEz7 u1ivVqmoXzwqW32NW3a24AyGLgQXgJi2+ctAZSGNd+pLydwANLCB+Ffc1I4fTmW0 kwLnqBgyVMxhbgRw6Blj9nh+ZlQOLwktpiMfrOwIpV0WLT3LZdRMrY1M/SnP+4+B Pq2BEzBAaHC5cNjQ3TjEj+nckXnrncJ0V6DepT+UIOC8L61rsb/tQAx8ecVVoHcW TTsQ3fewNcqIrKLRFpyNpXEAEAzlciwpV8lDczY5fLv5/j0MHiRSwBctj1pcK+CF Rsl2NygGZv0SuU0hDsDfEzVGLPjD1VYVGSJezWaaNzhjLw4sDUylBsKOcMNui4fW IUT3ahdjtvp03xjlGWAd1NI/MkYuu3RxJ2wR28vPEUGu2JEVpI8PtkR1FVqRIwBU Qd20x3bAn76zxMSWrsmDiTAa0+HMqjUbhzyeJxKPV5ON5k7RbmADrQ2rvxx+E4Uj FR3S6iulwaXDxIrvKZvTJDX3Myf2EL0bck5/XlKrD/B8tN5dCBgySA+SGHLhIiwZ XpCQmP6nLzZayeU4TX7jvAQdbhmR5GYCpO7SsIFTz7fJr6Vb8lM= =T6Im -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.2, round 2 - add display/gfx support for G12a boards - enable USB for g12a boards * tag 'amlogic-dt64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (26 commits) arm64: dts: meson-g12a-u200: Add support for Video Display arm64: dts: meson-g12a-sei510: Add support for Video Display arm64: dts: meson-g12a-x96-max: Add support for Video Display arm64: dts: meson-g12a: Add AO-CEC nodes arm64: dts: meson-g12a: Add VPU and HDMI related nodes arm64: dts: meson-g12a-x96-max: Enable USB arm64: dts: meson-g12a-u200: Enable USB arm64: dts: meson-g12a-sei510: Enable USB arm64: dts: meson-g12a-sei510: Add ADC Key and BT support arm64: dts: meson-g12a-u200: add regulators arm64: dts: meson: g12a: Add mali-g31 gpu node arm64: dts: meson: g12a: Add G12A USB nodes arm64: dts: meson: g12a: Add SAR ADC node dt-bindings: power: amlogic, meson-gx-pwrc: Add G12A compatible arm64: dts: meson-gxm: Add Mali-T820 node dt-bindings: gpu: mali-midgard: Add resets property dt-bindings: clock: meson8b: export the video decoder clocks dt-bindings: clock: meson8b: export the VPU clock dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN dt-bindings: clock: meson8b: drop the "ABP" clock definition ... Signed-off-by: Olof Johansson <[email protected]>
This commit is contained in:
commit
1e67323721
14 changed files with 654 additions and 25 deletions
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@ -7,26 +7,6 @@
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#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
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#define __AXG_AUDIO_CLKC_BINDINGS_H
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#define AUD_CLKID_SLV_SCLK0 9
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#define AUD_CLKID_SLV_SCLK1 10
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#define AUD_CLKID_SLV_SCLK2 11
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#define AUD_CLKID_SLV_SCLK3 12
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#define AUD_CLKID_SLV_SCLK4 13
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#define AUD_CLKID_SLV_SCLK5 14
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#define AUD_CLKID_SLV_SCLK6 15
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#define AUD_CLKID_SLV_SCLK7 16
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#define AUD_CLKID_SLV_SCLK8 17
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#define AUD_CLKID_SLV_SCLK9 18
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#define AUD_CLKID_SLV_LRCLK0 19
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#define AUD_CLKID_SLV_LRCLK1 20
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#define AUD_CLKID_SLV_LRCLK2 21
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#define AUD_CLKID_SLV_LRCLK3 22
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#define AUD_CLKID_SLV_LRCLK4 23
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#define AUD_CLKID_SLV_LRCLK5 24
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#define AUD_CLKID_SLV_LRCLK6 25
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#define AUD_CLKID_SLV_LRCLK7 26
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#define AUD_CLKID_SLV_LRCLK8 27
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#define AUD_CLKID_SLV_LRCLK9 28
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#define AUD_CLKID_DDR_ARB 29
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#define AUD_CLKID_PDM 30
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#define AUD_CLKID_TDMIN_A 31
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@ -26,7 +26,9 @@
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#define CLKID_AO_M4_FCLK 13
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#define CLKID_AO_M4_HCLK 14
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#define CLKID_AO_CLK81 15
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#define CLKID_AO_SAR_ADC_SEL 16
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#define CLKID_AO_SAR_ADC_CLK 18
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#define CLKID_AO_CTS_OSCIN 19
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#define CLKID_AO_32K 23
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#define CLKID_AO_CEC 27
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#define CLKID_AO_CTS_RTC_OSCIN 28
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@ -131,5 +131,10 @@
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#define CLKID_MALI_1 174
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#define CLKID_MALI 175
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#define CLKID_MPLL_5OM 177
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#define CLKID_CPU_CLK 187
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#define CLKID_PCIE_PLL 201
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#define CLKID_VDEC_1 204
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#define CLKID_VDEC_HEVC 207
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#define CLKID_VDEC_HEVCF 210
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#endif /* __G12A_CLKC_H */
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@ -103,10 +103,14 @@
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#define CLKID_MPLL1 94
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#define CLKID_MPLL2 95
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#define CLKID_NAND_CLK 112
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#define CLKID_ABP 124
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#define CLKID_APB 124
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#define CLKID_PERIPH 126
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#define CLKID_AXI 128
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#define CLKID_L2_DRAM 130
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#define CLKID_VPU 190
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#define CLKID_VDEC_1 196
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#define CLKID_VDEC_HCODEC 199
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#define CLKID_VDEC_2 202
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#define CLKID_VDEC_HEVC 206
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#endif /* __MESON8B_CLKC_H */
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@ -51,7 +51,10 @@
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#define RESET_SD_EMMC_A 44
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#define RESET_SD_EMMC_B 45
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#define RESET_SD_EMMC_C 46
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/* 47-60 */
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/* 47 */
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#define RESET_USB_PHY20 48
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#define RESET_USB_PHY21 49
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/* 50-60 */
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#define RESET_AUDIO_CODEC 61
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/* 62-63 */
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/* RESET2 */
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