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Merge "msm: kgsl: Add support for A619 GPU"

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This commit is contained in:
qctecmdr 2020-04-21 15:45:48 -07:00 • committed by Gerrit - the friendly Code Review server
commit 1f2f05026e
3 changed files with 34 additions and 6 deletions
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31
drivers/gpu/msm/adreno-gpulist.h
View file

@ -739,7 +739,7 @@ static const struct adreno_reglist a630_vbif_regs[] = {
};
/* For a615, a616, a618, a630, a640 and a680 */
/* For a615, a616, a618, A619, a630, a640 and a680 */
static const struct a6xx_protected_regs a630_protected_regs[] = {
{ A6XX_CP_PROTECT_REG + 0, 0x00000, 0x004ff, 0 },
{ A6XX_CP_PROTECT_REG + 1, 0x00501, 0x00506, 0 },
@ -803,7 +803,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = {
.highest_bank_bit = 15,
};
/* For a615, a616 and a618 */
/* For a615, a616, a618 and a619 */
static const struct adreno_reglist a615_hwcg_regs[] = {
{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
@ -870,7 +870,7 @@ static const struct adreno_reglist a615_hwcg_regs[] = {
{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}
};
/* For a615, a616 and a618 */
/* For a615, a616, a618 and a619 */
static const struct adreno_reglist a615_gbif_regs[] = {
{A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3},
};
@ -929,6 +929,30 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
.highest_bank_bit = 14,
};
static const struct adreno_a6xx_core adreno_gpu_core_a619 = {
.base = {
DEFINE_ADRENO_REV(ADRENO_REV_A619, 6, 1, 9, ANY_ID),
.features = ADRENO_RPMH | ADRENO_PREEMPTION |
ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
ADRENO_IOCOHERENT,
.gpudev = &adreno_a6xx_gpudev,
.gmem_size = SZ_512K,
.bus_width = 32,
},
.prim_fifo_threshold = 0x0018000,
.gmu_major = 1,
.gmu_minor = 9,
.sqefw_name = "a630_sqe.fw",
.gmufw_name = "a619_gmu.bin",
.zap_name = "a615_zap",
.hwcg = a615_hwcg_regs,
.hwcg_count = ARRAY_SIZE(a615_hwcg_regs),
.vbif = a615_gbif_regs,
.vbif_count = ARRAY_SIZE(a615_gbif_regs),
.hang_detect_cycles = 0x3fffff,
.protected_regs = a630_protected_regs,
};
static const struct adreno_reglist a620_hwcg_regs[] = {
{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
@ -1549,6 +1573,7 @@ static const struct adreno_gpu_core *adreno_gpulist[] = {
&adreno_gpu_core_a630v2.base,
&adreno_gpu_core_a615.base,
&adreno_gpu_core_a618.base,
&adreno_gpu_core_a619.base,
&adreno_gpu_core_a620.base,
&adreno_gpu_core_a640.base,
&adreno_gpu_core_a650.base,

6
drivers/gpu/msm/adreno.h
View file

@ -189,6 +189,7 @@ enum adreno_gpurev {
ADRENO_REV_A615 = 615,
ADRENO_REV_A616 = 616,
ADRENO_REV_A618 = 618,
ADRENO_REV_A619 = 619,
ADRENO_REV_A620 = 620,
ADRENO_REV_A630 = 630,
ADRENO_REV_A640 = 640,
@ -1009,6 +1010,7 @@ static inline int adreno_is_a660v1(struct adreno_device *adreno_dev)
ADRENO_TARGET(a610, ADRENO_REV_A610)
ADRENO_TARGET(a612, ADRENO_REV_A612)
ADRENO_TARGET(a618, ADRENO_REV_A618)
ADRENO_TARGET(a619, ADRENO_REV_A619)
ADRENO_TARGET(a620, ADRENO_REV_A620)
ADRENO_TARGET(a630, ADRENO_REV_A630)
ADRENO_TARGET(a640, ADRENO_REV_A640)
@ -1018,14 +1020,14 @@ ADRENO_TARGET(a680, ADRENO_REV_A680)
/*
* All the derived chipsets from A615 needs to be added to this
* list such as A616, A618 etc.
* list such as A616, A618, A619 etc.
*/
static inline int adreno_is_a615_family(struct adreno_device *adreno_dev)
{
unsigned int rev = ADRENO_GPUREV(adreno_dev);
return (rev == ADRENO_REV_A615 || rev == ADRENO_REV_A616 ||
rev == ADRENO_REV_A618);
rev == ADRENO_REV_A618 || rev == ADRENO_REV_A619);
}
/*

3
drivers/gpu/msm/adreno_a6xx_gmu.c
View file

@ -248,7 +248,8 @@ static int a6xx_load_pdc_ucode(struct kgsl_device *device)
_regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET, 0x10108);
_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET, cx_res_addr);
if (adreno_is_a618(adreno_dev) || adreno_is_a650_family(adreno_dev))
if (adreno_is_a618(adreno_dev) || adreno_is_a619(adreno_dev) ||
adreno_is_a650_family(adreno_dev))
_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET, 0x2);
else
_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET, 0x3);