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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 06:09:23 -04:00
pinctrl: qcom: add pinctrl driver for SLPI
Sensor Low Power Island (SLPI) has a Pin controller which can support 14 pin configurations, add pinctrl driver to handle pins of SLPI from APPS. The snapshot of this driver is taken from msm-4.14 commit "e4483b491ed60". Change-Id: Id44ccb34f23a285edf0eaccb501ba4d2296a7b87 Signed-off-by: Vivek Kumar <vivekuma@codeaurora.org>
This commit is contained in:
Vivek Kumar
Shreyas K K
parent
aa860b5b17
commit
1f46e62d77
3 changed files with 468 additions and 0 deletions
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@ -300,4 +300,14 @@ config PINCTRL_MONACO
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Say Y here to compile statically, or M here to compile it as a module.
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If unsure, say N.
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config PINCTRL_SLPI
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tristate "Qualcomm Technologies, Inc SLPI pin controller driver"
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depends on GPIOLIB && OF
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help
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Sensor Low Power Island(SLPI) has a Pin controller which can support
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14 pin configurations. This is the pinctrl, pinmux and pinconf
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driver for the SLPI pin controller block.
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Say Y here to compile statically, or M here to compile it as a module.
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If unsure, say N.
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endif
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@ -33,3 +33,4 @@ obj-$(CONFIG_PINCTRL_SCUBA) += pinctrl-scuba.o
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obj-$(CONFIG_PINCTRL_SDXLEMUR) += pinctrl-sdxlemur.o
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obj-$(CONFIG_PINCTRL_SDXNIGHTJAR) += pinctrl-sdxnightjar.o
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obj-$(CONFIG_PINCTRL_MONACO) += pinctrl-monaco.o
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obj-$(CONFIG_PINCTRL_SLPI) += pinctrl-slpi.o
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457
drivers/pinctrl/qcom/pinctrl-slpi.c
Normal file
457
drivers/pinctrl/qcom/pinctrl-slpi.c
Normal file
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@ -0,0 +1,457 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include "../core.h"
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#include "../pinctrl-utils.h"
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/**
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* struct slpi_pin - SLPI pin definition
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* @name: Name of the pin.
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* @ctl_reg: Offset of the register holding control bits for this group.
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* @io_reg: Offset of the register holding input/output bits for this group.
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* @pull_bit: Offset in @ctl_reg for the bias configuration.
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* @mux_bit: Offset in @ctl_reg for the pinmux function selection.
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* @drv_bit: Offset in @ctl_reg for the drive strength configuration.
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* @oe_bit: Offset in @ctl_reg for controlling output enable.
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* @in_bit: Offset in @io_reg for the input bit value.
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* @out_bit: Offset in @io_reg for the output bit value.
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*/
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struct slpi_pin {
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void __iomem *base;
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unsigned int offset;
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unsigned int ctl_reg;
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unsigned int io_reg;
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unsigned int pull_bit:5;
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unsigned int mux_bit:5;
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unsigned int drv_bit:5;
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unsigned int oe_bit:5;
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unsigned int in_bit:5;
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unsigned int out_bit:5;
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};
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/* The index of each function in slpi_pin_functions[] array */
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enum slpi_pin_func_index {
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SLPI_PIN_FUNC_INDEX_GPIO = 0x00,
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SLPI_PIN_FUNC_INDEX_FUNC1 = 0x01,
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SLPI_PIN_FUNC_INDEX_FUNC2 = 0x02,
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SLPI_PIN_FUNC_INDEX_FUNC3 = 0x03,
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SLPI_PIN_FUNC_INDEX_FUNC4 = 0x04,
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SLPI_PIN_FUNC_INDEX_FUNC5 = 0x05,
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};
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#define SLPI_PIN_FUNC_GPIO "gpio"
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#define SLPI_PIN_FUNC_FUNC1 "func1"
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#define SLPI_PIN_FUNC_FUNC2 "func2"
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#define SLPI_PIN_FUNC_FUNC3 "func3"
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#define SLPI_PIN_FUNC_FUNC4 "func4"
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#define SLPI_PIN_FUNC_FUNC5 "func5"
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static const char *const slpi_gpio_groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
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"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
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"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
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"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
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"gpio29", "gpio30", "gpio31",
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};
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static const char *const slpi_pin_functions[] = {
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[SLPI_PIN_FUNC_INDEX_GPIO] = SLPI_PIN_FUNC_GPIO,
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[SLPI_PIN_FUNC_INDEX_FUNC1] = SLPI_PIN_FUNC_FUNC1,
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[SLPI_PIN_FUNC_INDEX_FUNC2] = SLPI_PIN_FUNC_FUNC2,
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[SLPI_PIN_FUNC_INDEX_FUNC3] = SLPI_PIN_FUNC_FUNC3,
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[SLPI_PIN_FUNC_INDEX_FUNC4] = SLPI_PIN_FUNC_FUNC4,
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[SLPI_PIN_FUNC_INDEX_FUNC5] = SLPI_PIN_FUNC_FUNC5,
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};
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static unsigned int slpi_read(struct slpi_pin *pin, u32 reg)
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{
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return readl_relaxed(pin->base + pin->offset + reg);
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}
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static void slpi_write(u32 val, struct slpi_pin *pin, u32 reg)
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{
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return writel_relaxed(val, pin->base + pin->offset + reg);
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}
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static int slpi_get_groups_count(struct pinctrl_dev *pctldev)
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{
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/* Every PIN is a group */
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return pctldev->desc->npins;
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}
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static const char *slpi_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int pin)
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{
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return pctldev->desc->pins[pin].name;
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}
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static int slpi_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned int pin,
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const unsigned int **pins,
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unsigned int *num_pins)
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{
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*pins = &pctldev->desc->pins[pin].number;
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*num_pins = 1;
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return 0;
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}
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static const struct pinctrl_ops slpi_pinctrl_ops = {
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.get_groups_count = slpi_get_groups_count,
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.get_group_name = slpi_get_group_name,
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.get_group_pins = slpi_get_group_pins,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
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.dt_free_map = pinctrl_utils_free_map,
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};
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static int slpi_get_functions_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(slpi_pin_functions);
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}
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static const char *slpi_get_function_name(struct pinctrl_dev *pctldev,
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unsigned int function)
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{
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return slpi_pin_functions[function];
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}
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static int slpi_get_function_groups(struct pinctrl_dev *pctldev,
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unsigned int function,
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const char * const **groups,
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unsigned int * const num_groups)
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{
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*groups = slpi_gpio_groups;
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*num_groups = pctldev->desc->npins;
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return 0;
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}
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static int slpi_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned int function,
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unsigned int pin_index)
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{
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struct slpi_pin *pin;
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u32 val;
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pin = pctldev->desc->pins[pin_index].drv_data;
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if (WARN_ON(function >= ARRAY_SIZE(slpi_pin_functions)))
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return -EINVAL;
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val = slpi_read(pin, pin->ctl_reg);
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val &= ~(0x7 << pin->mux_bit);
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val |= function << pin->mux_bit;
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slpi_write(val, pin, pin->ctl_reg);
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return 0;
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}
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static const struct pinmux_ops slpi_pinmux_ops = {
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.get_functions_count = slpi_get_functions_count,
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.get_function_name = slpi_get_function_name,
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.get_function_groups = slpi_get_function_groups,
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.set_mux = slpi_pinmux_set_mux,
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};
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static int slpi_config_reg(const struct slpi_pin *pin,
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unsigned int param,
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unsigned int *mask,
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unsigned int *bit)
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{
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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case PIN_CONFIG_BIAS_BUS_HOLD:
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case PIN_CONFIG_BIAS_PULL_UP:
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*bit = pin->pull_bit;
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*mask = 3;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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*bit = pin->drv_bit;
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*mask = 7;
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break;
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case PIN_CONFIG_OUTPUT:
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case PIN_CONFIG_INPUT_ENABLE:
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*bit = pin->oe_bit;
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*mask = 1;
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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#define MSM_NO_PULL 0
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#define MSM_PULL_DOWN 1
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#define MSM_KEEPER 2
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#define MSM_PULL_UP 3
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static unsigned int slpi_regval_to_drive(u32 val)
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{
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return (val + 1) * 2;
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}
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static int slpi_config_group_get(struct pinctrl_dev *pctldev,
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unsigned int pin_index,
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unsigned long *config)
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{
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unsigned int param = pinconf_to_config_param(*config);
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struct slpi_pin *pin;
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unsigned int mask;
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unsigned int arg;
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unsigned int bit;
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int ret;
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u32 val;
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pin = pctldev->desc->pins[pin_index].drv_data;
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ret = slpi_config_reg(pin, param, &mask, &bit);
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if (ret < 0)
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return ret;
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val = slpi_read(pin, pin->ctl_reg);
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arg = (val >> bit) & mask;
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/* Convert register value to pinconf value */
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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arg = arg == MSM_NO_PULL;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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arg = arg == MSM_PULL_DOWN;
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break;
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case PIN_CONFIG_BIAS_BUS_HOLD:
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arg = arg == MSM_KEEPER;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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arg = arg == MSM_PULL_UP;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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arg = slpi_regval_to_drive(arg);
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break;
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case PIN_CONFIG_OUTPUT:
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/* Pin is not output */
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if (!arg)
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return -EINVAL;
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val = slpi_read(pin, pin->io_reg);
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arg = !!(val & BIT(pin->in_bit));
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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/* Pin is output */
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if (arg)
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return -EINVAL;
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arg = 1;
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break;
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default:
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return -EOPNOTSUPP;
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}
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*config = pinconf_to_config_packed(param, arg);
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return 0;
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}
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static int slpi_config_group_set(struct pinctrl_dev *pctldev,
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unsigned int pin_index,
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unsigned long *configs,
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unsigned int num_configs)
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{
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struct slpi_pin *pin;
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unsigned int param;
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unsigned int mask;
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unsigned int arg;
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unsigned int bit;
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int ret;
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u32 val;
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int i;
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pin = pctldev->desc->pins[pin_index].drv_data;
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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arg = pinconf_to_config_argument(configs[i]);
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ret = slpi_config_reg(pin, param, &mask, &bit);
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if (ret < 0)
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return ret;
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/* Convert pinconf values to register values */
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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arg = MSM_NO_PULL;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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arg = MSM_PULL_DOWN;
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break;
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case PIN_CONFIG_BIAS_BUS_HOLD:
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arg = MSM_KEEPER;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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arg = MSM_PULL_UP;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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/* Check for invalid values */
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if (arg > 16 || arg < 2 || (arg % 2) != 0)
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arg = -1;
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else
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arg = (arg / 2) - 1;
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break;
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case PIN_CONFIG_OUTPUT:
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/* set output value */
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val = slpi_read(pin, pin->io_reg);
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if (arg)
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val |= BIT(pin->out_bit);
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else
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val &= ~BIT(pin->out_bit);
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slpi_write(val, pin, pin->io_reg);
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/* enable output */
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arg = 1;
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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/* disable output */
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arg = 0;
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break;
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default:
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dev_err(pctldev->dev, "Unsupported config parameter: %x\n",
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param);
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return -EINVAL;
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}
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/* Range-check user-supplied value */
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if (arg & ~mask) {
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dev_err(pctldev->dev, "config %x: %x is invalid\n",
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param, arg);
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return -EINVAL;
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}
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val = slpi_read(pin, pin->ctl_reg);
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val &= ~(mask << bit);
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val |= arg << bit;
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slpi_write(val, pin, pin->ctl_reg);
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}
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return 0;
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}
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static const struct pinconf_ops slpi_pinconf_ops = {
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.is_generic = true,
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.pin_config_group_get = slpi_config_group_get,
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.pin_config_group_set = slpi_config_group_set,
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};
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static int slpi_pinctrl_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct pinctrl_dev *pctldev;
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struct pinctrl_pin_desc *pindesc;
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struct pinctrl_desc *pctrldesc;
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struct slpi_pin *pin, *pins;
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struct resource *res;
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int ret, npins, i;
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void __iomem *base;
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dev_err(dev, "SLPI probe called !!!!!!\n");
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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ret = of_property_read_u32(dev->of_node, "qcom,num-pins", &npins);
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if (ret < 0)
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return ret;
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pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
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if (!pindesc)
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return -ENOMEM;
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WARN_ON(npins > ARRAY_SIZE(slpi_gpio_groups));
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pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
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if (!pins)
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return -ENOMEM;
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pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
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if (!pctrldesc)
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return -ENOMEM;
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pctrldesc->pctlops = &slpi_pinctrl_ops;
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pctrldesc->pmxops = &slpi_pinmux_ops;
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pctrldesc->confops = &slpi_pinconf_ops;
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pctrldesc->owner = THIS_MODULE;
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pctrldesc->name = dev_name(&pdev->dev);
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pctrldesc->pins = pindesc;
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pctrldesc->npins = npins;
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for (i = 0; i < npins; i++, pindesc++) {
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pin = &pins[i];
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pindesc->drv_data = pin;
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pindesc->number = i;
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pindesc->name = slpi_gpio_groups[i];
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pin->base = base;
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pin->offset = i * 0x1000;
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pin->ctl_reg = 0x0;
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pin->io_reg = 0x4;
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pin->pull_bit = 0;
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pin->out_bit = 1;
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pin->mux_bit = 2;
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pin->oe_bit = 9;
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pin->drv_bit = 6;
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pin->in_bit = 0;
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}
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pctldev = devm_pinctrl_register(&pdev->dev, pctrldesc, NULL);
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if (IS_ERR(pctldev)) {
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dev_err(dev, "Failed to register pinctrl device\n");
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return PTR_ERR(pctldev);
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}
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dev_err(dev, "Registered pinctrl SLPI !!!!!!\n");
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return 0;
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}
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static const struct of_device_id slpi_pinctrl_of_match[] = {
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{ .compatible = "qcom,slpi-pinctrl" }, /* Generic */
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{ },
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};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, slpi_pinctrl_of_match);
|
||||
|
||||
static struct platform_driver slpi_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "qcom-slpi-pinctrl",
|
||||
.of_match_table = slpi_pinctrl_of_match,
|
||||
},
|
||||
.probe = slpi_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init slpi_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&slpi_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(slpi_pinctrl_init);
|
||||
|
||||
static void __exit slpi_pinctrl_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&slpi_pinctrl_driver);
|
||||
}
|
||||
module_exit(slpi_pinctrl_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI SLPI GPIO pin control driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in a new issue