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qcacld-3.0: Add support for 11ax draft3.0 spec

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Add support for 11ax draft3.0 spec.

Change-Id: I272d9f4ec6b3a2a23ad708265dd0afaf289c1b95
CRs-Fixed: 2294255
This commit is contained in:
Kiran Kumar Lokere 2018-08-22 14:47:11 -07:00 • committed by nshrivas
commit 1f96b4af34
16 changed files with 1686 additions and 1262 deletions
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2
Kbuild Executable file → Normal file
View file

@ -14,7 +14,6 @@ ifeq ($(KERNEL_BUILD), y)
WLAN_COMMON_ROOT := ../qca-wifi-host-cmn
WLAN_COMMON_INC := $(WLAN_ROOT)/$(WLAN_COMMON_ROOT)
endif
WLAN_COMMON_ROOT ?= ../qca-wifi-host-cmn
WLAN_COMMON_INC ?= $(WLAN_ROOT)/$(WLAN_COMMON_ROOT)
@ -2214,6 +2213,7 @@ endif
cppflags-$(CONFIG_WLAN_FEATURE_11AX) += -DWLAN_FEATURE_11AX
cppflags-$(CONFIG_WLAN_FEATURE_11AX) += -DWLAN_FEATURE_11AX_BSS_COLOR
cppflags-$(CONFIG_WLAN_FEATURE_11AX) += -DSUPPORT_11AX_D3
cppflags-$(CONFIG_LITHIUM) += -DFEATURE_AST

47
core/hdd/src/wlan_hdd_he.c
View file

@ -67,18 +67,20 @@ void hdd_update_tgt_he_cap(struct hdd_context *hdd_ctx,
QDF_MIN(he_cap->fragmentation,
hdd_ctx->config->he_dynamic_frag_support));
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MAX_FRAG_MSDU,
he_cap->max_num_frag_msdu);
he_cap->max_num_frag_msdu_amsdu_exp);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MIN_FRAG_SIZE,
he_cap->min_frag_size);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TRIG_PAD,
he_cap->trigger_frm_mac_pad);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MTID_AGGR,
he_cap->multi_tid_aggr);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MTID_AGGR_RX,
he_cap->multi_tid_aggr_rx_supp);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MTID_AGGR_TX,
he_cap->multi_tid_aggr_tx_supp);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_LINK_ADAPTATION,
he_cap->he_link_adaptation);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_ALL_ACK, he_cap->all_ack);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_UL_MU_RSP_SCHEDULING,
he_cap->ul_mu_rsp_sched);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TRIGD_RSP_SCHEDULING,
he_cap->trigd_rsp_sched);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_BUFFER_STATUS_RPT,
he_cap->a_bsr);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_BCAST_TWT,
@ -89,11 +91,10 @@ void hdd_update_tgt_he_cap(struct hdd_context *hdd_ctx,
he_cap->mu_cascade);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MULTI_TID,
he_cap->ack_enabled_multitid);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_DL_MU_BA, he_cap->dl_mu_ba);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_OMI, he_cap->omi_a_ctrl);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_OFDMA_RA, he_cap->ofdma_ra);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MAX_AMPDU_LEN,
he_cap->max_ampdu_len);
he_cap->max_ampdu_len_exp_ext);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_AMSDU_FRAG, he_cap->amsdu_frag);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_FLEX_TWT_SCHED,
he_cap->flex_twt_sched);
@ -103,17 +104,19 @@ void hdd_update_tgt_he_cap(struct hdd_context *hdd_ctx,
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_QTP, he_cap->qtp);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_A_BQR, he_cap->a_bqr);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_SR_RESPONDER,
he_cap->sr_responder);
he_cap->spatial_reuse_param_rspder);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_NDP_FEEDBACK_SUPP,
he_cap->ndp_feedback_supp);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_OPS_SUPP,
he_cap->ops_supp);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_AMSDU_IN_AMPDU,
he_cap->amsdu_in_ampdu);
he_cap->dual_band = ((cfg->band_cap == BAND_ALL) &&
(hdd_ctx->config->nBandCapability == BAND_ALL));
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_DUAL_BAND, he_cap->dual_band);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_SUB_CH_SEL_TX,
he_cap->he_sub_ch_sel_tx_supp);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_UL_2X996_RU,
he_cap->ul_2x996_tone_ru_supp);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX,
he_cap->om_ctrl_ul_mu_data_dis_rx);
chan_width = HE_CH_WIDTH_COMBINE(he_cap->chan_width_0,
he_cap->chan_width_1, he_cap->chan_width_2,
he_cap->chan_width_3, he_cap->chan_width_4,
@ -128,7 +131,7 @@ void hdd_update_tgt_he_cap(struct hdd_context *hdd_ctx,
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_LTF_PPDU,
he_cap->he_1x_ltf_800_gi_ppdu);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS,
he_cap->midamble_rx_max_nsts);
he_cap->midamble_tx_rx_max_nsts);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_LTF_NDP,
he_cap->he_4x_ltf_3200_gi_ndp);
if (config->enableRxSTBC) {
@ -215,8 +218,22 @@ void hdd_update_tgt_he_cap(struct hdd_context *hdd_ctx,
he_cap->he_ppdu_80_in_160_80p80Mhz);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_ER_1X_HE_LTF_GI,
he_cap->er_1x_he_ltf_gi);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MIDAMBLE_RX_1X_HE_LTF,
he_cap->midamble_rx_1x_he_ltf);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF,
he_cap->midamble_tx_rx_1x_he_ltf);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_DCM_MAX_BW,
he_cap->dcm_max_bw);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM,
he_cap->longer_than_16_he_sigb_ofdm_sym);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TX_1024_QAM_LT_242_RU,
he_cap->tx_1024_qam_lt_242_tone_ru);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_1024_QAM_LT_242_RU,
he_cap->rx_1024_qam_lt_242_tone_ru);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK,
he_cap->non_trig_cqi_feedback);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB,
he_cap->rx_full_bw_su_he_mu_compress_sigb);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB,
he_cap->rx_full_bw_su_he_mu_non_cmpr_sigb);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_RX_MCS_MAP_LT_80,
he_cap->rx_he_mcs_map_lt_80);
hdd_he_set_wni_cfg(hdd_ctx, WNI_CFG_HE_TX_MCS_MAP_LT_80,

178
core/mac/inc/sir_mac_prot_def.h
View file

@ -2082,42 +2082,46 @@ struct he_cap_network_endian {
uint32_t twt_request:1;
uint32_t twt_responder:1;
uint32_t fragmentation:2;
uint32_t max_num_frag_msdu:3;
uint32_t max_num_frag_msdu_amsdu_exp:3;
uint32_t min_frag_size:2;
uint32_t trigger_frm_mac_pad:2;
uint32_t multi_tid_aggr:3;
uint32_t multi_tid_aggr_rx_supp:3;
uint32_t he_link_adaptation:2;
uint32_t all_ack:1;
uint32_t ul_mu_rsp_sched:1;
uint32_t trigd_rsp_sched:1;
uint32_t a_bsr:1;
uint32_t broadcast_twt:1;
uint32_t ba_32bit_bitmap:1;
uint32_t mu_cascade:1;
uint32_t ack_enabled_multitid:1;
uint32_t dl_mu_ba:1;
uint32_t reserved:1;
uint32_t omi_a_ctrl:1;
uint32_t ofdma_ra:1;
uint32_t max_ampdu_len:2;
uint32_t max_ampdu_len_exp_ext:2;
uint32_t amsdu_frag:1;
uint32_t flex_twt_sched:1;
uint32_t rx_ctrl_frame:1;
uint8_t bsrp_ampdu_aggr:1;
uint8_t qtp:1;
uint8_t a_bqr:1;
uint8_t sr_responder:1;
uint8_t ndp_feedback_supp:1;
uint8_t ops_supp:1;
uint8_t amsdu_in_ampdu:1;
uint8_t reserved1:1;
uint16_t bsrp_ampdu_aggr:1;
uint16_t qtp:1;
uint16_t a_bqr:1;
uint16_t spatial_reuse_param_rspder:1;
uint16_t ndp_feedback_supp:1;
uint16_t ops_supp:1;
uint16_t amsdu_in_ampdu:1;
uint16_t multi_tid_aggr_tx_supp:3;
uint16_t he_sub_ch_sel_tx_supp:1;
uint16_t ul_2x996_tone_ru_supp:1;
uint16_t om_ctrl_ul_mu_data_dis_rx:1;
uint16_t reserved1:3;
uint32_t dual_band:1;
uint32_t reserved2:1;
uint32_t chan_width:7;
uint32_t rx_pream_puncturing:4;
uint32_t device_class:1;
uint32_t ldpc_coding:1;
uint32_t he_1x_ltf_800_gi_ppdu:1;
uint32_t midamble_rx_max_nsts:2;
uint32_t midamble_tx_rx_max_nsts:2;
uint32_t he_4x_ltf_3200_gi_ndp:1;
uint32_t tx_stbc_lt_80mhz:1;
uint32_t rx_stbc_lt_80mhz:1;
@ -2149,13 +2153,22 @@ struct he_cap_network_endian {
uint32_t tx_stbc_gt_80mhz:1;
uint32_t rx_stbc_gt_80mhz:1;
uint8_t er_he_ltf_800_gi_4x:1;
uint8_t he_ppdu_20_in_40Mhz_2G:1;
uint8_t he_ppdu_20_in_160_80p80Mhz:1;
uint8_t he_ppdu_80_in_160_80p80Mhz:1;
uint8_t er_1x_he_ltf_gi:1;
uint8_t midamble_rx_1x_he_ltf:1;
uint8_t reserved2:2;
uint16_t er_he_ltf_800_gi_4x:1;
uint16_t he_ppdu_20_in_40Mhz_2G:1;
uint16_t he_ppdu_20_in_160_80p80Mhz:1;
uint16_t he_ppdu_80_in_160_80p80Mhz:1;
uint16_t er_1x_he_ltf_gi:1;
uint16_t midamble_tx_rx_1x_he_ltf:1;
uint16_t dcm_max_bw:2;
uint16_t longer_than_16_he_sigb_ofdm_sym:1;
uint16_t non_trig_cqi_feedback:1;
uint16_t tx_1024_qam_lt_242_tone_ru:1;
uint16_t rx_1024_qam_lt_242_tone_ru:1;
uint16_t rx_full_bw_su_he_mu_compress_sigb:1;
uint16_t rx_full_bw_su_he_mu_non_cmpr_sigb:1;
uint16_t reserved3:2;
uint8_t reserved4;
uint16_t rx_he_mcs_map_lt_80;
uint16_t tx_he_mcs_map_lt_80;
@ -2169,12 +2182,11 @@ struct he_ops_network_endian {
uint32_t bss_color:6;
uint32_t default_pe:3;
uint32_t twt_required:1;
uint32_t rts_threshold:10;
uint32_t txop_rts_threshold:10;
uint32_t partial_bss_col:1;
uint32_t vht_oper_present:1;
uint32_t reserved1:6;
uint32_t mbssid_ap:1;
uint32_t tx_bssid_ind:1;
uint32_t co_located_bss:1;
uint32_t bss_col_disabled:1;
uint32_t reserved2:1;
uint8_t basic_mcs_nss[2];
@ -2188,7 +2200,7 @@ struct he_ops_network_endian {
union {
struct {
uint8_t data;
} info; /* mbssid_ap = 1 */
} info; /* co_located_bss = 1 */
} maxbssid_ind;
} qdf_packed;
@ -2198,35 +2210,39 @@ struct he_capability_info {
uint32_t rx_ctrl_frame:1;
uint32_t flex_twt_sched:1;
uint32_t amsdu_frag:1;
uint32_t max_ampdu_len:2;
uint32_t max_ampdu_len_exp_ext:2;
uint32_t ofdma_ra:1;
uint32_t omi_a_ctrl:1;
uint32_t dl_mu_ba:1;
uint32_t reserved:1;
uint32_t ack_enabled_multitid:1;
uint32_t mu_cascade:1;
uint32_t ba_32bit_bitmap:1;
uint32_t broadcast_twt:1;
uint32_t a_bsr:1;
uint32_t ul_mu_rsp_sched:1;
uint32_t trigd_rsp_sched:1;
uint32_t all_ack:1;
uint32_t he_link_adaptation:2;
uint32_t multi_tid_aggr:3;
uint32_t multi_tid_aggr_rx_supp:3;
uint32_t trigger_frm_mac_pad:2;
uint32_t min_frag_size:2;
uint32_t max_num_frag_msdu:3;
uint32_t max_num_frag_msdu_amsdu_exp:3;
uint32_t fragmentation:2;
uint32_t twt_responder:1;
uint32_t twt_request:1;
uint32_t htc_he:1;
uint8_t reserved1:1;
uint8_t amsdu_in_ampdu:1;
uint8_t ops_supp:1;
uint8_t ndp_feedback_supp:1;
uint8_t sr_responder:1;
uint8_t a_bqr:1;
uint8_t qtp:1;
uint8_t bsrp_ampdu_aggr:1;
uint16_t reserved1:3;
uint16_t om_ctrl_ul_mu_data_dis_rx:1;
uint16_t ul_2x996_tone_ru_supp:1;
uint16_t he_sub_ch_sel_tx_supp:1;
uint16_t multi_tid_aggr_tx_supp:3;
uint16_t amsdu_in_ampdu:1;
uint16_t ops_supp:1;
uint16_t ndp_feedback_supp:1;
uint16_t spatial_reuse_param_rspder:1;
uint16_t a_bqr:1;
uint16_t qtp:1;
uint16_t bsrp_ampdu_aggr:1;
uint32_t su_beamformer:1;
uint32_t ul_he_mu:1;
@ -2237,13 +2253,13 @@ struct he_capability_info {
uint32_t rx_stbc_lt_80mhz:1;
uint32_t tx_stbc_lt_80mhz:1;
uint32_t he_4x_ltf_3200_gi_ndp:1;
uint32_t midamble_rx_max_nsts:2;
uint32_t midamble_tx_rx_max_nsts:2;
uint32_t he_1x_ltf_800_gi_ppdu:1;
uint32_t ldpc_coding:1;
uint32_t device_class:1;
uint32_t rx_pream_puncturing:4;
uint32_t chan_width:7;
uint32_t dual_band:1;
uint32_t reserved2:1;
uint32_t rx_stbc_gt_80mhz:1;
uint32_t tx_stbc_gt_80mhz:1;
@ -2266,13 +2282,22 @@ struct he_capability_info {
uint32_t mu_beamformer:1;
uint32_t su_beamformee:1;
uint8_t reserved2:2;
uint8_t midamble_rx_1x_he_ltf:1;
uint8_t er_1x_he_ltf_gi:1;
uint8_t he_ppdu_80_in_160_80p80Mhz:1;
uint8_t he_ppdu_20_in_160_80p80Mhz:1;
uint8_t he_ppdu_20_in_40Mhz_2G:1;
uint8_t er_he_ltf_800_gi_4x:1;
uint16_t reserved3:2;
uint16_t rx_full_bw_su_he_mu_non_cmpr_sigb:1;
uint16_t rx_full_bw_su_he_mu_compress_sigb:1;
uint16_t rx_1024_qam_lt_242_tone_ru:1;
uint16_t tx_1024_qam_lt_242_tone_ru:1;
uint16_t non_trig_cqi_feedback:1;
uint16_t longer_than_16_he_sigb_ofdm_sym:1;
uint16_t dcm_max_bw:2;
uint16_t midamble_tx_rx_1x_he_ltf:1;
uint16_t er_1x_he_ltf_gi:1;
uint16_t he_ppdu_80_in_160_80p80Mhz:1;
uint16_t he_ppdu_20_in_160_80p80Mhz:1;
uint16_t he_ppdu_20_in_40Mhz_2G:1;
uint16_t er_he_ltf_800_gi_4x:1;
uint8_t reserved4;
uint16_t tx_he_mcs_map_80_80;
uint16_t rx_he_mcs_map_80_80;
@ -2285,42 +2310,46 @@ struct he_capability_info {
uint32_t twt_request:1;
uint32_t twt_responder:1;
uint32_t fragmentation:2;
uint32_t max_num_frag_msdu:3;
uint32_t max_num_frag_msdu_amsdu_exp:3;
uint32_t min_frag_size:2;
uint32_t trigger_frm_mac_pad:2;
uint32_t multi_tid_aggr:3;
uint32_t multi_tid_aggr_rx_supp:3;
uint32_t he_link_adaptation:2;
uint32_t all_ack:1;
uint32_t ul_mu_rsp_sched:1;
uint32_t trigd_rsp_sched:1;
uint32_t a_bsr:1;
uint32_t broadcast_twt:1;
uint32_t ba_32bit_bitmap:1;
uint32_t mu_cascade:1;
uint32_t ack_enabled_multitid:1;
uint32_t dl_mu_ba:1;
uint32_t reserved:1;
uint32_t omi_a_ctrl:1;
uint32_t ofdma_ra:1;
uint32_t max_ampdu_len:2;
uint32_t max_ampdu_len_exp_ext:2;
uint32_t amsdu_frag:1;
uint32_t flex_twt_sched:1;
uint32_t rx_ctrl_frame:1;
uint8_t bsrp_ampdu_aggr:1;
uint8_t qtp:1;
uint8_t a_bqr:1;
uint8_t sr_responder:1;
uint8_t ndp_feedback_supp:1;
uint8_t ops_supp:1;
uint8_t amsdu_in_ampdu:1;
uint8_t reserved1:1;
uint16_t bsrp_ampdu_aggr:1;
uint16_t qtp:1;
uint16_t a_bqr:1;
uint16_t spatial_reuse_param_rspder:1;
uint16_t ndp_feedback_supp:1;
uint16_t ops_supp:1;
uint16_t amsdu_in_ampdu:1;
uint16_t multi_tid_aggr_tx_supp:3;
uint16_t he_sub_ch_sel_tx_supp:1;
uint16_t ul_2x996_tone_ru_supp:1;
uint16_t om_ctrl_ul_mu_data_dis_rx:1;
uint16_t reserved1:3;
uint32_t dual_band:1;
uint32_t reserved2:1;
uint32_t chan_width:7;
uint32_t rx_pream_puncturing:4;
uint32_t device_class:1;
uint32_t ldpc_coding:1;
uint32_t he_1x_ltf_800_gi_ppdu:1;
uint32_t midamble_rx_max_nsts:2;
uint32_t midamble_tx_rx_max_nsts:2;
uint32_t he_4x_ltf_3200_gi_ndp:1;
uint32_t tx_stbc_lt_80mhz:1;
uint32_t rx_stbc_lt_80mhz:1;
@ -2352,13 +2381,22 @@ struct he_capability_info {
uint32_t tx_stbc_gt_80mhz:1;
uint32_t rx_stbc_gt_80mhz:1;
uint8_t er_he_ltf_800_gi_4x:1;
uint8_t he_ppdu_20_in_40Mhz_2G:1;
uint8_t he_ppdu_20_in_160_80p80Mhz:1;
uint8_t he_ppdu_80_in_160_80p80Mhz:1;
uint8_t er_1x_he_ltf_gi:1;
uint8_t midamble_rx_1x_he_ltf:1;
uint8_t reserved2:2;
uint16_t er_he_ltf_800_gi_4x:1;
uint16_t he_ppdu_20_in_40Mhz_2G:1;
uint16_t he_ppdu_20_in_160_80p80Mhz:1;
uint16_t he_ppdu_80_in_160_80p80Mhz:1;
uint16_t er_1x_he_ltf_gi:1;
uint16_t midamble_tx_rx_1x_he_ltf:1;
uint16_t dcm_max_bw:2;
uint16_t longer_than_16_he_sigb_ofdm_sym:1;
uint16_t non_trig_cqi_feedback:1;
uint16_t tx_1024_qam_lt_242_tone_ru:1;
uint16_t rx_1024_qam_lt_242_tone_ru:1;
uint16_t rx_full_bw_su_he_mu_compress_sigb:1;
uint16_t rx_full_bw_su_he_mu_non_cmpr_sigb:1;
uint16_t reserved3:2;
uint8_t reserved4;
uint16_t rx_he_mcs_map_lt_80;
uint16_t tx_he_mcs_map_lt_80;

82
core/mac/inc/wni_cfg.h
View file

@ -209,10 +209,10 @@ enum {
WNI_CFG_HE_MAX_FRAG_MSDU,
WNI_CFG_HE_MIN_FRAG_SIZE,
WNI_CFG_HE_TRIG_PAD,
WNI_CFG_HE_MTID_AGGR,
WNI_CFG_HE_MTID_AGGR_RX,
WNI_CFG_HE_LINK_ADAPTATION,
WNI_CFG_HE_ALL_ACK,
WNI_CFG_HE_UL_MU_RSP_SCHEDULING,
WNI_CFG_HE_TRIGD_RSP_SCHEDULING,
WNI_CFG_HE_BUFFER_STATUS_RPT,
WNI_CFG_HE_BCAST_TWT,
WNI_CFG_HE_BA_32BIT,
@ -232,7 +232,10 @@ enum {
WNI_CFG_HE_NDP_FEEDBACK_SUPP,
WNI_CFG_HE_OPS_SUPP,
WNI_CFG_HE_AMSDU_IN_AMPDU,
WNI_CFG_HE_DUAL_BAND,
WNI_CFG_HE_MTID_AGGR_TX,
WNI_CFG_HE_SUB_CH_SEL_TX,
WNI_CFG_HE_UL_2X996_RU,
WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX,
WNI_CFG_HE_CHAN_WIDTH,
WNI_CFG_HE_RX_PREAM_PUNC,
WNI_CFG_HE_CLASS_OF_DEVICE,
@ -273,7 +276,14 @@ enum {
WNI_CFG_HE_PPDU_20_IN_160_80P80MHZ,
WNI_CFG_HE_PPDU_80_IN_160_80P80MHZ,
WNI_CFG_HE_ER_1X_HE_LTF_GI,
WNI_CFG_HE_MIDAMBLE_RX_1X_HE_LTF,
WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF,
WNI_CFG_HE_DCM_MAX_BW,
WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM,
WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK,
WNI_CFG_HE_TX_1024_QAM_LT_242_RU,
WNI_CFG_HE_RX_1024_QAM_LT_242_RU,
WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB,
WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB,
WNI_CFG_HE_RX_MCS_MAP_LT_80,
WNI_CFG_HE_TX_MCS_MAP_LT_80,
WNI_CFG_HE_RX_MCS_MAP_160,
@ -1247,9 +1257,9 @@ enum {
#define WNI_CFG_HE_TRIG_PAD_STAMAX 2
#define WNI_CFG_HE_TRIG_PAD_STADEF 0
#define WNI_CFG_HE_MTID_AGGR_STAMIN 0
#define WNI_CFG_HE_MTID_AGGR_STAMAX 0x7
#define WNI_CFG_HE_MTID_AGGR_STADEF 0
#define WNI_CFG_HE_MTID_AGGR_RX_STAMIN 0
#define WNI_CFG_HE_MTID_AGGR_RX_STAMAX 0x7
#define WNI_CFG_HE_MTID_AGGR_RX_STADEF 0
#define WNI_CFG_HE_LINK_ADAPTATION_STAMIN 0
#define WNI_CFG_HE_LINK_ADAPTATION_STAMAX 0x3
@ -1259,9 +1269,9 @@ enum {
#define WNI_CFG_HE_ALL_ACK_STAMAX 1
#define WNI_CFG_HE_ALL_ACK_STADEF 0
#define WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STAMIN 0
#define WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STAMAX 1
#define WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STADEF 0
#define WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STAMIN 0
#define WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STAMAX 1
#define WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STADEF 0
#define WNI_CFG_HE_BUFFER_STATUS_RPT_STAMIN 0
#define WNI_CFG_HE_BUFFER_STATUS_RPT_STAMAX 1
@ -1339,9 +1349,21 @@ enum {
#define WNI_CFG_HE_AMSDU_IN_AMPDU_MAX 1
#define WNI_CFG_HE_AMSDU_IN_AMPDU_DEF 0
#define WNI_CFG_HE_DUAL_BAND_STAMIN 0
#define WNI_CFG_HE_DUAL_BAND_STAMAX 1
#define WNI_CFG_HE_DUAL_BAND_STADEF 1
#define WNI_CFG_HE_MTID_AGGR_TX_MIN 0
#define WNI_CFG_HE_MTID_AGGR_TX_MAX 0x7
#define WNI_CFG_HE_MTID_AGGR_TX_DEF 0
#define WNI_CFG_HE_SUB_CH_SEL_TX_MIN 0
#define WNI_CFG_HE_SUB_CH_SEL_TX_MAX 1
#define WNI_CFG_HE_SUB_CH_SEL_TX_DEF 0
#define WNI_CFG_HE_UL_2X996_RU_MIN 0
#define WNI_CFG_HE_UL_2X996_RU_MAX 1
#define WNI_CFG_HE_UL_2X996_RU_DEF 0
#define WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_MIN 0
#define WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_MAX 1
#define WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_DEF 0
#define WNI_CFG_HE_CHAN_WIDTH_STAMIN 0
#define WNI_CFG_HE_CHAN_WIDTH_STAMAX 0x3F
@ -1503,9 +1525,37 @@ enum {
#define WNI_CFG_HE_ER_1X_HE_LTF_GI_MAX 1
#define WNI_CFG_HE_ER_1X_HE_LTF_GI_DEF 0
#define WNI_CFG_HE_MIDAMBLE_RX_1X_HE_LTF_MIN 0
#define WNI_CFG_HE_MIDAMBLE_RX_1X_HE_LTF_MAX 1
#define WNI_CFG_HE_MIDAMBLE_RX_1X_HE_LTF_DEF 0
#define WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_MIN 0
#define WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_MAX 1
#define WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_DEF 0
#define WNI_CFG_HE_DCM_MAX_BW_MIN 0
#define WNI_CFG_HE_DCM_MAX_BW_MAX 3
#define WNI_CFG_HE_DCM_MAX_BW_DEF 0
#define WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_MIN 0
#define WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_MAX 1
#define WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_DEF 0
#define WNI_CFG_HE_TX_1024_QAM_LT_242_RU_MIN 0
#define WNI_CFG_HE_TX_1024_QAM_LT_242_RU_MAX 1
#define WNI_CFG_HE_TX_1024_QAM_LT_242_RU_DEF 0
#define WNI_CFG_HE_RX_1024_QAM_LT_242_RU_MIN 0
#define WNI_CFG_HE_RX_1024_QAM_LT_242_RU_MAX 1
#define WNI_CFG_HE_RX_1024_QAM_LT_242_RU_DEF 0
#define WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_MIN 0
#define WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_MAX 1
#define WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_DEF 0
#define WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_MIN 0
#define WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_MAX 1
#define WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_DEF 0
#define WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_MIN 0
#define WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_MAX 1
#define WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_DEF 0
#define WNI_CFG_HE_RX_MCS_MAP_LT_80_MIN 0x0000
#define WNI_CFG_HE_RX_MCS_MAP_LT_80_MAX 0xFFFF

57
core/mac/src/cfg/cfgUtil/dot11f.frms
View file

@ -2836,22 +2836,22 @@ IE he_cap (EID_EXTN_ID_ELEMENT) OUI (0x23)
twt_request:1;
twt_responder:1;
fragmentation:2;
max_num_frag_msdu:3;
max_num_frag_msdu_amsdu_exp:3;
min_frag_size:2;
trigger_frm_mac_pad:2;
multi_tid_aggr:3;
multi_tid_aggr_rx_supp:3;
he_link_adaptation:2;
all_ack:1;
ul_mu_rsp_sched:1;
trigd_rsp_sched:1;
a_bsr:1;
broadcast_twt:1;
ba_32bit_bitmap:1;
mu_cascade:1;
ack_enabled_multitid:1;
dl_mu_ba:1;
reserved:1;
omi_a_ctrl:1;
ofdma_ra:1;
max_ampdu_len:2;
max_ampdu_len_exp_ext:2;
amsdu_frag:1;
flex_twt_sched:1;
rx_ctrl_frame:1;
@ -2860,14 +2860,18 @@ IE he_cap (EID_EXTN_ID_ELEMENT) OUI (0x23)
bsrp_ampdu_aggr:1;
qtp:1;
a_bqr:1;
sr_responder:1;
spatial_reuse_param_rspder:1;
ndp_feedback_supp:1;
ops_supp:1;
amsdu_in_ampdu:1;
reserved1:1;
multi_tid_aggr_tx_supp:3;
he_sub_ch_sel_tx_supp:1;
ul_2x996_tone_ru_supp:1;
om_ctrl_ul_mu_data_dis_rx:1;
reserved1:3;
}
{
dual_band:1;
reserved2:1;
chan_width_0:1;
chan_width_1:1;
chan_width_2:1;
@ -2879,7 +2883,7 @@ IE he_cap (EID_EXTN_ID_ELEMENT) OUI (0x23)
device_class:1;
ldpc_coding:1;
he_1x_ltf_800_gi_ppdu:1;
midamble_rx_max_nsts:2;
midamble_tx_rx_max_nsts:2;
he_4x_ltf_3200_gi_ndp:1;
tx_stbc_lt_80mhz:1;
rx_stbc_lt_80mhz:1;
@ -2918,9 +2922,17 @@ IE he_cap (EID_EXTN_ID_ELEMENT) OUI (0x23)
he_ppdu_20_in_160_80p80Mhz:1;
he_ppdu_80_in_160_80p80Mhz:1;
er_1x_he_ltf_gi:1;
midamble_rx_1x_he_ltf:1;
reserved2:2;
midamble_tx_rx_1x_he_ltf:1;
dcm_max_bw:2;
longer_than_16_he_sigb_ofdm_sym:1;
non_trig_cqi_feedback:1;
tx_1024_qam_lt_242_tone_ru:1;
rx_1024_qam_lt_242_tone_ru:1;
rx_full_bw_su_he_mu_compress_sigb:1;
rx_full_bw_su_he_mu_non_cmpr_sigb:1;
reserved3:2;
}
reserved4, 1;
rx_he_mcs_map_lt_80, 2;
tx_he_mcs_map_lt_80, 2;
rx_he_mcs_map_160[2][0..1] COUNTIS chan_width_2;
@ -2939,17 +2951,20 @@ IE he_cap (EID_EXTN_ID_ELEMENT) OUI (0x23)
IE he_op (EID_EXTN_ID_ELEMENT) OUI (0x24)
{
{
bss_color: 6;
default_pe: 3;
twt_required: 1;
rts_threshold: 10;
partial_bss_col: 1;
txop_rts_threshold: 10;
vht_oper_present: 1;
reserved1: 6;
mbssid_ap: 1;
tx_bssid_ind: 1;
bss_col_disabled: 1;
reserved2: 1;
co_located_bss: 1;
}
{
er_su_disable: 1;
reserved2: 7;
}
{
bss_color:6;
partial_bss_col:1;
bss_col_disabled:1;
}
basic_mcs_nss[2];
OPTIONAL UNION vht_oper (DISCRIMINATOR vht_oper_present)
@ -2961,9 +2976,9 @@ IE he_op (EID_EXTN_ID_ELEMENT) OUI (0x24)
center_freq_seg1, 1;
}
};
OPTIONAL UNION maxbssid_ind (DISCRIMINATOR mbssid_ap)
OPTIONAL UNION maxbssid_ind (DISCRIMINATOR co_located_bss)
{
info (mbssid_ap IS 1)
info (co_located_bss IS 1)
{
data, 1;
}

16
core/mac/src/cfg/cfg_param_name.c
View file

@ -223,10 +223,11 @@ const char *cfg_get_string(uint16_t cfg_id)
CASE_RETURN_STRING(WNI_CFG_HE_MAX_FRAG_MSDU);
CASE_RETURN_STRING(WNI_CFG_HE_MIN_FRAG_SIZE);
CASE_RETURN_STRING(WNI_CFG_HE_TRIG_PAD);
CASE_RETURN_STRING(WNI_CFG_HE_MTID_AGGR);
CASE_RETURN_STRING(WNI_CFG_HE_MTID_AGGR_RX);
CASE_RETURN_STRING(WNI_CFG_HE_MTID_AGGR_TX);
CASE_RETURN_STRING(WNI_CFG_HE_LINK_ADAPTATION);
CASE_RETURN_STRING(WNI_CFG_HE_ALL_ACK);
CASE_RETURN_STRING(WNI_CFG_HE_UL_MU_RSP_SCHEDULING);
CASE_RETURN_STRING(WNI_CFG_HE_TRIGD_RSP_SCHEDULING);
CASE_RETURN_STRING(WNI_CFG_HE_BUFFER_STATUS_RPT);
CASE_RETURN_STRING(WNI_CFG_HE_BCAST_TWT);
CASE_RETURN_STRING(WNI_CFG_HE_BA_32BIT);
@ -245,7 +246,9 @@ const char *cfg_get_string(uint16_t cfg_id)
CASE_RETURN_STRING(WNI_CFG_HE_SR_RESPONDER);
CASE_RETURN_STRING(WNI_CFG_HE_NDP_FEEDBACK_SUPP);
CASE_RETURN_STRING(WNI_CFG_HE_OPS_SUPP);
CASE_RETURN_STRING(WNI_CFG_HE_DUAL_BAND);
CASE_RETURN_STRING(WNI_CFG_HE_SUB_CH_SEL_TX);
CASE_RETURN_STRING(WNI_CFG_HE_UL_2X996_RU);
CASE_RETURN_STRING(WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX);
CASE_RETURN_STRING(WNI_CFG_HE_CHAN_WIDTH);
CASE_RETURN_STRING(WNI_CFG_HE_RX_PREAM_PUNC);
CASE_RETURN_STRING(WNI_CFG_HE_CLASS_OF_DEVICE);
@ -281,6 +284,13 @@ const char *cfg_get_string(uint16_t cfg_id)
CASE_RETURN_STRING(WNI_CFG_HE_TX_STBC_GT80);
CASE_RETURN_STRING(WNI_CFG_HE_RX_STBC_GT80);
CASE_RETURN_STRING(WNI_CFG_HE_ER_4x_LTF_GI);
CASE_RETURN_STRING(WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF);
CASE_RETURN_STRING(WNI_CFG_HE_DCM_MAX_BW);
CASE_RETURN_STRING(WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM);
CASE_RETURN_STRING(WNI_CFG_HE_TX_1024_QAM_LT_242_RU);
CASE_RETURN_STRING(WNI_CFG_HE_RX_1024_QAM_LT_242_RU);
CASE_RETURN_STRING(WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB);
CASE_RETURN_STRING(WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB);
CASE_RETURN_STRING(WNI_CFG_HE_RX_MCS_MAP_LT_80);
CASE_RETURN_STRING(WNI_CFG_HE_TX_MCS_MAP_LT_80);
CASE_RETURN_STRING(WNI_CFG_HE_RX_MCS_MAP_160);

81
core/mac/src/cfg/cfg_proc_msg.c
View file

@ -958,10 +958,10 @@ cgstatic cfg_static[CFG_PARAM_MAX_NUM] = {
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_TRIG_PAD_STAMIN, WNI_CFG_HE_TRIG_PAD_STAMAX,
WNI_CFG_HE_TRIG_PAD_STADEF},
{WNI_CFG_HE_MTID_AGGR,
{WNI_CFG_HE_MTID_AGGR_RX,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_MTID_AGGR_STAMIN, WNI_CFG_HE_MTID_AGGR_STAMAX,
WNI_CFG_HE_MTID_AGGR_STADEF},
WNI_CFG_HE_MTID_AGGR_RX_STAMIN, WNI_CFG_HE_MTID_AGGR_RX_STAMAX,
WNI_CFG_HE_MTID_AGGR_RX_STADEF},
{WNI_CFG_HE_LINK_ADAPTATION,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_LINK_ADAPTATION_STAMIN, WNI_CFG_HE_LINK_ADAPTATION_STAMAX,
@ -970,11 +970,11 @@ cgstatic cfg_static[CFG_PARAM_MAX_NUM] = {
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_ALL_ACK_STAMIN, WNI_CFG_HE_ALL_ACK_STAMAX,
WNI_CFG_HE_ALL_ACK_STADEF},
{WNI_CFG_HE_UL_MU_RSP_SCHEDULING,
{WNI_CFG_HE_TRIGD_RSP_SCHEDULING,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STAMIN,
WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STAMAX,
WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STADEF},
WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STAMIN,
WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STAMAX,
WNI_CFG_HE_TRIGD_RSP_SCHEDULING_STADEF},
{WNI_CFG_HE_BUFFER_STATUS_RPT,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_BUFFER_STATUS_RPT_STAMIN,
@ -1050,14 +1050,30 @@ cgstatic cfg_static[CFG_PARAM_MAX_NUM] = {
WNI_CFG_HE_AMSDU_IN_AMPDU_MIN,
WNI_CFG_HE_AMSDU_IN_AMPDU_MAX,
WNI_CFG_HE_AMSDU_IN_AMPDU_DEF},
{WNI_CFG_HE_MTID_AGGR_TX,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_MTID_AGGR_TX_MIN,
WNI_CFG_HE_MTID_AGGR_TX_MAX,
WNI_CFG_HE_MTID_AGGR_TX_DEF},
{WNI_CFG_HE_SUB_CH_SEL_TX,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_SUB_CH_SEL_TX_MIN,
WNI_CFG_HE_SUB_CH_SEL_TX_MAX,
WNI_CFG_HE_SUB_CH_SEL_TX_DEF},
{WNI_CFG_HE_UL_2X996_RU,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_UL_2X996_RU_MIN,
WNI_CFG_HE_UL_2X996_RU_MAX,
WNI_CFG_HE_UL_2X996_RU_DEF},
{WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_MIN,
WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_MAX,
WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX_DEF},
{WNI_CFG_HE_A_BQR,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_A_BQR_STAMIN, WNI_CFG_HE_A_BQR_STAMAX,
WNI_CFG_HE_A_BQR_STADEF},
{WNI_CFG_HE_DUAL_BAND,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_DUAL_BAND_STAMIN, WNI_CFG_HE_DUAL_BAND_STAMAX,
WNI_CFG_HE_DUAL_BAND_STADEF},
{WNI_CFG_HE_CHAN_WIDTH,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_CHAN_WIDTH_STAMIN, WNI_CFG_HE_CHAN_WIDTH_STAMAX,
@ -1222,11 +1238,46 @@ cgstatic cfg_static[CFG_PARAM_MAX_NUM] = {
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_ER_1X_HE_LTF_GI_MIN, WNI_CFG_HE_ER_1X_HE_LTF_GI_MAX,
WNI_CFG_HE_ER_1X_HE_LTF_GI_DEF},
{WNI_CFG_HE_MIDAMBLE_RX_1X_HE_LTF,
{WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_MIDAMBLE_RX_1X_HE_LTF_MIN,
WNI_CFG_HE_MIDAMBLE_RX_1X_HE_LTF_MAX,
WNI_CFG_HE_MIDAMBLE_RX_1X_HE_LTF_DEF},
WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_MIN,
WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_MAX,
WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF_DEF},
{WNI_CFG_HE_DCM_MAX_BW,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_DCM_MAX_BW_MIN,
WNI_CFG_HE_DCM_MAX_BW_MAX,
WNI_CFG_HE_DCM_MAX_BW_DEF},
{WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_MIN,
WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_MAX,
WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM_DEF},
{WNI_CFG_HE_TX_1024_QAM_LT_242_RU,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_TX_1024_QAM_LT_242_RU_MIN,
WNI_CFG_HE_TX_1024_QAM_LT_242_RU_MAX,
WNI_CFG_HE_TX_1024_QAM_LT_242_RU_DEF},
{WNI_CFG_HE_RX_1024_QAM_LT_242_RU,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_RX_1024_QAM_LT_242_RU_MIN,
WNI_CFG_HE_RX_1024_QAM_LT_242_RU_MAX,
WNI_CFG_HE_RX_1024_QAM_LT_242_RU_DEF},
{WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_MIN,
WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_MAX,
WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK_DEF},
{WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_MIN,
WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_MAX,
WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB_DEF},
{WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_MIN,
WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_MAX,
WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB_DEF},
{WNI_CFG_HE_RX_MCS_MAP_LT_80,
CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,

83
core/mac/src/include/dot11f.h
View file

@ -8804,34 +8804,38 @@ typedef struct sDot11fIEhe_cap {
uint32_t twt_request:1;
uint32_t twt_responder:1;
uint32_t fragmentation:2;
uint32_t max_num_frag_msdu:3;
uint32_t max_num_frag_msdu_amsdu_exp:3;
uint32_t min_frag_size:2;
uint32_t trigger_frm_mac_pad:2;
uint32_t multi_tid_aggr:3;
uint32_t multi_tid_aggr_rx_supp:3;
uint32_t he_link_adaptation:2;
uint32_t all_ack:1;
uint32_t ul_mu_rsp_sched:1;
uint32_t trigd_rsp_sched:1;
uint32_t a_bsr:1;
uint32_t broadcast_twt:1;
uint32_t ba_32bit_bitmap:1;
uint32_t mu_cascade:1;
uint32_t ack_enabled_multitid:1;
uint32_t dl_mu_ba:1;
uint32_t reserved:1;
uint32_t omi_a_ctrl:1;
uint32_t ofdma_ra:1;
uint32_t max_ampdu_len:2;
uint32_t max_ampdu_len_exp_ext:2;
uint32_t amsdu_frag:1;
uint32_t flex_twt_sched:1;
uint32_t rx_ctrl_frame:1;
uint8_t bsrp_ampdu_aggr:1;
uint8_t qtp:1;
uint8_t a_bqr:1;
uint8_t sr_responder:1;
uint8_t ndp_feedback_supp:1;
uint8_t ops_supp:1;
uint8_t amsdu_in_ampdu:1;
uint8_t reserved1:1;
uint32_t dual_band:1;
uint16_t bsrp_ampdu_aggr:1;
uint16_t qtp:1;
uint16_t a_bqr:1;
uint16_t spatial_reuse_param_rspder:1;
uint16_t ndp_feedback_supp:1;
uint16_t ops_supp:1;
uint16_t amsdu_in_ampdu:1;
uint16_t multi_tid_aggr_tx_supp:3;
uint16_t he_sub_ch_sel_tx_supp:1;
uint16_t ul_2x996_tone_ru_supp:1;
uint16_t om_ctrl_ul_mu_data_dis_rx:1;
uint16_t reserved1:3;
uint32_t reserved2:1;
uint32_t chan_width_0:1;
uint32_t chan_width_1:1;
uint32_t chan_width_2:1;
@ -8843,7 +8847,7 @@ typedef struct sDot11fIEhe_cap {
uint32_t device_class:1;
uint32_t ldpc_coding:1;
uint32_t he_1x_ltf_800_gi_ppdu:1;
uint32_t midamble_rx_max_nsts:2;
uint32_t midamble_tx_rx_max_nsts:2;
uint32_t he_4x_ltf_3200_gi_ndp:1;
uint32_t tx_stbc_lt_80mhz:1;
uint32_t rx_stbc_lt_80mhz:1;
@ -8873,13 +8877,21 @@ typedef struct sDot11fIEhe_cap {
uint32_t max_nc:3;
uint32_t tx_stbc_gt_80mhz:1;
uint32_t rx_stbc_gt_80mhz:1;
uint8_t er_he_ltf_800_gi_4x:1;
uint8_t he_ppdu_20_in_40Mhz_2G:1;
uint8_t he_ppdu_20_in_160_80p80Mhz:1;
uint8_t he_ppdu_80_in_160_80p80Mhz:1;
uint8_t er_1x_he_ltf_gi:1;
uint8_t midamble_rx_1x_he_ltf:1;
uint8_t reserved2:2;
uint16_t er_he_ltf_800_gi_4x:1;
uint16_t he_ppdu_20_in_40Mhz_2G:1;
uint16_t he_ppdu_20_in_160_80p80Mhz:1;
uint16_t he_ppdu_80_in_160_80p80Mhz:1;
uint16_t er_1x_he_ltf_gi:1;
uint16_t midamble_tx_rx_1x_he_ltf:1;
uint16_t dcm_max_bw:2;
uint16_t longer_than_16_he_sigb_ofdm_sym:1;
uint16_t non_trig_cqi_feedback:1;
uint16_t tx_1024_qam_lt_242_tone_ru:1;
uint16_t rx_1024_qam_lt_242_tone_ru:1;
uint16_t rx_full_bw_su_he_mu_compress_sigb:1;
uint16_t rx_full_bw_su_he_mu_non_cmpr_sigb:1;
uint16_t reserved3:2;
uint8_t reserved4;
uint16_t rx_he_mcs_map_lt_80;
uint16_t tx_he_mcs_map_lt_80;
uint8_t rx_he_mcs_map_160[1][2];
@ -8897,9 +8909,9 @@ typedef struct sDot11fIEhe_cap {
#define DOT11F_EID_HE_CAP (255)
/* N.B. These #defines do *not* include the EID & length */
#define DOT11F_IE_HE_CAP_MIN_LEN (18)
#define DOT11F_IE_HE_CAP_MIN_LEN (21)
#define DOT11F_IE_HE_CAP_MAX_LEN (51)
#define DOT11F_IE_HE_CAP_MAX_LEN (54)
#ifdef __cplusplus
extern "C" {
@ -8930,17 +8942,16 @@ uint32_t dot11f_get_packed_ie_he_cap(
/* EID 255 (0xff) Extended EID 36 (0x24) */
typedef struct sDot11fIEhe_op {
uint8_t present;
uint32_t bss_color:6;
uint32_t default_pe:3;
uint32_t twt_required:1;
uint32_t rts_threshold:10;
uint32_t partial_bss_col:1;
uint32_t vht_oper_present:1;
uint32_t reserved1:6;
uint32_t mbssid_ap:1;
uint32_t tx_bssid_ind:1;
uint32_t bss_col_disabled:1;
uint32_t reserved2:1;
uint16_t default_pe:3;
uint16_t twt_required:1;
uint16_t txop_rts_threshold:10;
uint16_t vht_oper_present:1;
uint16_t co_located_bss:1;
uint8_t er_su_disable:1;
uint8_t reserved2:7;
uint8_t bss_color:6;
uint8_t partial_bss_col:1;
uint8_t bss_col_disabled:1;
uint8_t basic_mcs_nss[2];
union {
struct {
@ -8952,7 +8963,7 @@ typedef struct sDot11fIEhe_op {
union {
struct {
uint8_t data;
} info; /* mbssid_ap = 1 */
} info; /* co_located_bss = 1 */
} maxbssid_ind;
} tDot11fIEhe_op;

108
core/mac/src/pe/lim/lim_utils.c
View file

@ -7424,9 +7424,8 @@ void lim_decide_he_op(tpAniSirGlobal mac_ctx, tpAddBssParams add_bss,
}
he_ops->default_pe = he_ops_from_ie->default_pe;
he_ops->twt_required = he_ops_from_ie->twt_required;
he_ops->rts_threshold = he_ops_from_ie->rts_threshold;
he_ops->txop_rts_threshold = he_ops_from_ie->txop_rts_threshold;
he_ops->partial_bss_col = he_ops_from_ie->partial_bss_col;
he_ops->tx_bssid_ind = he_ops_from_ie->tx_bssid_ind;
he_ops->bss_col_disabled = he_ops_from_ie->bss_col_disabled;
if (QDF_STATUS_SUCCESS != wlan_cfg_get_int(mac_ctx,
@ -7438,10 +7437,10 @@ void lim_decide_he_op(tpAniSirGlobal mac_ctx, tpAddBssParams add_bss,
pe_debug("HE Op: bss_color: 0x%0x, default_pe_duration: 0x%0x",
he_ops->bss_color, he_ops->default_pe);
pe_debug("He Op: twt_required: 0x%0x, rts_threshold: 0x%0x",
he_ops->twt_required, he_ops->rts_threshold);
pe_debug("HE Op: partial_bss_color: 0x%0x, Tx BSSID Indicator: 0x%0x",
he_ops->partial_bss_col, he_ops->tx_bssid_ind);
pe_debug("He Op: twt_required: 0x%0x, txop_rts_threshold: 0x%0x",
he_ops->twt_required, he_ops->txop_rts_threshold);
pe_debug("HE Op: partial_bss_color: 0x%0x",
he_ops->partial_bss_col);
pe_debug("HE Op: BSS color disabled: 0x%0x",
he_ops->bss_col_disabled);
pe_debug("HE Op: Basic MCS NSS: 0x%04x",
@ -7492,17 +7491,17 @@ void lim_log_he_cap(tpAniSirGlobal mac, tDot11fIEhe_cap *he_cap)
pe_debug("\tFragmentation support: 0x%02x",
he_cap->fragmentation);
pe_debug("\tMax no.of frag MSDUs: 0x%03x",
he_cap->max_num_frag_msdu);
he_cap->max_num_frag_msdu_amsdu_exp);
pe_debug("\tMin. frag size: 0x%02x", he_cap->min_frag_size);
pe_debug("\tTrigger MAC pad duration: 0x%02x",
he_cap->trigger_frm_mac_pad);
pe_debug("\tMulti-TID aggr support: 0x%03x",
he_cap->multi_tid_aggr);
pe_debug("\tMulti-TID aggr Rx support: 0x%03x",
he_cap->multi_tid_aggr_rx_supp);
pe_debug("\tLink adaptation: 0x%02x",
he_cap->he_link_adaptation);
pe_debug("\tAll ACK support: 0x%01x", he_cap->all_ack);
pe_debug("\tUL MU resp. scheduling: 0x%01x",
he_cap->ul_mu_rsp_sched);
pe_debug("\tTriggered resp. scheduling: 0x%01x",
he_cap->trigd_rsp_sched);
pe_debug("\tA-Buff status report: 0x%01x", he_cap->a_bsr);
pe_debug("\tBroadcast TWT support: 0x%01x",
he_cap->broadcast_twt);
@ -7512,12 +7511,11 @@ void lim_log_he_cap(tpAniSirGlobal mac, tDot11fIEhe_cap *he_cap)
he_cap->mu_cascade);
pe_debug("\tACK enabled Multi-TID: 0x%01x",
he_cap->ack_enabled_multitid);
pe_debug("\tMulti-STA BA in DL MU: 0x%01x", he_cap->dl_mu_ba);
pe_debug("\tOMI A-Control support: 0x%01x",
he_cap->omi_a_ctrl);
pe_debug("\tOFDMA RA support: 0x%01x", he_cap->ofdma_ra);
pe_debug("\tMax A-MPDU Length: 0x%02x",
he_cap->max_ampdu_len);
he_cap->max_ampdu_len_exp_ext);
pe_debug("\tA-MSDU Fragmentation: 0x%01x",
he_cap->amsdu_frag);
pe_debug("\tFlex. TWT sched support: 0x%01x",
@ -7528,13 +7526,20 @@ void lim_log_he_cap(tpAniSirGlobal mac, tDot11fIEhe_cap *he_cap)
he_cap->bsrp_ampdu_aggr);
pe_debug("\tQuite Time Period support: 0x%01x", he_cap->qtp);
pe_debug("\tA-BQR support: 0x%01x", he_cap->a_bqr);
pe_debug("\tSR Reponder support: 0x%01x", he_cap->sr_responder);
pe_debug("\tSR Reponder support: 0x%01x",
he_cap->spatial_reuse_param_rspder);
pe_debug("\tNDP Feedback support: 0x%01x", he_cap->ndp_feedback_supp);
pe_debug("\tOPS support: 0x%01x", he_cap->ops_supp);
pe_debug("\tOPS support: 0x%01x", he_cap->amsdu_in_ampdu);
pe_debug("\tAMSDU in AMPDU: 0x%01x", he_cap->amsdu_in_ampdu);
pe_debug("\tMulti-TID aggr Tx support: 0x%03x",
he_cap->multi_tid_aggr_tx_supp);
pe_debug("\tHE sub ch sel tx supp: 0x%01x",
he_cap->he_sub_ch_sel_tx_supp);
pe_debug("\tUL 2x996 tone RU supp: 0x%01x",
he_cap->ul_2x996_tone_ru_supp);
pe_debug("\tOM ctrl UL MU data dis rx supp: 0x%01x",
he_cap->om_ctrl_ul_mu_data_dis_rx);
/* HE PHY capabilities */
pe_debug("\tDual band support: 0x%01x", he_cap->dual_band);
chan_width = HE_CH_WIDTH_COMBINE(he_cap->chan_width_0,
he_cap->chan_width_1, he_cap->chan_width_2,
he_cap->chan_width_3, he_cap->chan_width_4,
@ -7548,8 +7553,8 @@ void lim_log_he_cap(tpAniSirGlobal mac, tDot11fIEhe_cap *he_cap)
he_cap->ldpc_coding);
pe_debug("\tLTF and GI for HE PPDUs: 0x%02x",
he_cap->he_1x_ltf_800_gi_ppdu);
pe_debug("\tMidamble Rx MAX NSTS: 0x%02x",
he_cap->midamble_rx_max_nsts);
pe_debug("\tMidamble TX Rx MAX NSTS: 0x%02x",
he_cap->midamble_tx_rx_max_nsts);
pe_debug("\tLTF and GI for NDP: 0x%02x",
he_cap->he_4x_ltf_3200_gi_ndp);
pe_debug("\tSTBC Tx support (<= 80MHz): 0x%01x",
@ -7559,7 +7564,7 @@ void lim_log_he_cap(tpAniSirGlobal mac, tDot11fIEhe_cap *he_cap)
pe_debug("\tDoppler support: 0x%02x", he_cap->doppler);
pe_debug("\tUL MU: 0x%02x", he_cap->ul_mu);
pe_debug("\tDCM encoding Tx: 0x%03x", he_cap->dcm_enc_tx);
pe_debug("\tDCM encoding Tx: 0x%03x", he_cap->dcm_enc_rx);
pe_debug("\tDCM encoding Rx: 0x%03x", he_cap->dcm_enc_rx);
pe_debug("\tHE MU PPDU payload support: 0x%01x",
he_cap->ul_he_mu);
pe_debug("\tSU Beamformer: 0x%01x", he_cap->su_beamformer);
@ -7597,16 +7602,30 @@ void lim_log_he_cap(tpAniSirGlobal mac, tDot11fIEhe_cap *he_cap)
he_cap->rx_stbc_gt_80mhz);
pe_debug("\tMax Nc: 0x%03x", he_cap->max_nc);
pe_debug("\tER 4x HE LTF support: 0x%01x", he_cap->er_he_ltf_800_gi_4x);
pe_debug("\tER 4x HE LTF support: 0x%01x",
pe_debug("\tHE ppdu 20 in 40M in 2.4G: 0x%01x",
he_cap->he_ppdu_20_in_40Mhz_2G);
pe_debug("\tER 4x HE LTF support: 0x%01x",
pe_debug("\tHE ppdu 20 in 160 and 80p80: 0x%01x",
he_cap->he_ppdu_20_in_160_80p80Mhz);
pe_debug("\tER 4x HE LTF support: 0x%01x",
pe_debug("\tHE ppdu 80 in 160 and 80p80: 0x%01x",
he_cap->he_ppdu_80_in_160_80p80Mhz);
pe_debug("\tER 4x HE LTF support: 0x%01x",
pe_debug("\tER 1x HE LTF GI support: 0x%01x",
he_cap->er_1x_he_ltf_gi);
pe_debug("\tER 4x HE LTF support: 0x%01x",
he_cap->midamble_rx_1x_he_ltf);
pe_debug("\tmidamble txrx 1x he LTF: 0x%01x",
he_cap->midamble_tx_rx_1x_he_ltf);
pe_debug("\tDCM max BW: 0x%02x",
he_cap->dcm_max_bw);
pe_debug("\tlonger_than_16_he_sigb_ofdm_sym: 0x%01x",
he_cap->longer_than_16_he_sigb_ofdm_sym);
pe_debug("\tnon_trig_cqi_feedback: 0x%01x",
he_cap->non_trig_cqi_feedback);
pe_debug("\ttx_1024_qam_lt_242_tone_ru: 0x%01x",
he_cap->tx_1024_qam_lt_242_tone_ru);
pe_debug("\trx_1024_qam_lt_242_tone_ru: 0x%01x",
he_cap->rx_1024_qam_lt_242_tone_ru);
pe_debug("\trx_full_bw_su_he_mu_compress_sigb: 0x%01x",
he_cap->rx_full_bw_su_he_mu_compress_sigb);
pe_debug("\trx_full_bw_su_he_mu_non_cmpr_sigb: 0x%01x",
he_cap->rx_full_bw_su_he_mu_non_cmpr_sigb);
pe_debug("\tRx MCS map for <= 80 Mhz: 0x%04x",
he_cap->rx_he_mcs_map_lt_80);
pe_debug("\tTx MCS map for <= 80 Mhz: 0x%04x",
@ -7630,13 +7649,13 @@ void lim_log_he_cap(tpAniSirGlobal mac, tDot11fIEhe_cap *he_cap)
void lim_log_he_op(tpAniSirGlobal mac, tDot11fIEhe_op *he_ops)
{
pe_debug("bss_color: %0x, default_pe_duration: %0x, twt_required: %0x, rts_threshold: %0x, vht_oper_present: %0x",
he_ops->bss_color, he_ops->default_pe,
he_ops->twt_required, he_ops->rts_threshold,
he_ops->vht_oper_present);
pe_debug("\tpartial_bss_color: %0x, MBSSID AP: %0x, Tx BSSID Indicator: %0x, BSS color disabled: %0x",
he_ops->partial_bss_col, he_ops->mbssid_ap,
he_ops->tx_bssid_ind, he_ops->bss_col_disabled);
pe_debug("bss_color: %0x, default_pe_duration: %0x, twt_required: %0x, txop_rts_threshold: %0x, vht_oper_present: %0x",
he_ops->bss_color, he_ops->default_pe,
he_ops->twt_required, he_ops->txop_rts_threshold,
he_ops->vht_oper_present);
pe_debug("\tpart_bss_color %0x, Co-located BSS %0x, BSS color dis %0x",
he_ops->partial_bss_col, he_ops->co_located_bss,
he_ops->bss_col_disabled);
pe_debug("he basic mcs nss: 0x%04x",
*((uint16_t *)he_ops->basic_mcs_nss));
@ -7713,22 +7732,23 @@ void lim_set_he_caps(tpAniSirGlobal mac, tpPESession session, uint8_t *ie_start,
he_cap->twt_request = dot11_cap.twt_request;
he_cap->twt_responder = dot11_cap.twt_responder;
he_cap->fragmentation = dot11_cap.fragmentation;
he_cap->max_num_frag_msdu = dot11_cap.max_num_frag_msdu;
he_cap->max_num_frag_msdu_amsdu_exp =
dot11_cap.max_num_frag_msdu_amsdu_exp;
he_cap->min_frag_size = dot11_cap.min_frag_size;
he_cap->trigger_frm_mac_pad = dot11_cap.trigger_frm_mac_pad;
he_cap->multi_tid_aggr = dot11_cap.multi_tid_aggr;
he_cap->multi_tid_aggr_rx_supp =
dot11_cap.multi_tid_aggr_rx_supp;
he_cap->he_link_adaptation = dot11_cap.he_link_adaptation;
he_cap->all_ack = dot11_cap.all_ack;
he_cap->ul_mu_rsp_sched = dot11_cap.ul_mu_rsp_sched;
he_cap->trigd_rsp_sched = dot11_cap.trigd_rsp_sched;
he_cap->a_bsr = dot11_cap.a_bsr;
he_cap->broadcast_twt = dot11_cap.broadcast_twt;
he_cap->ba_32bit_bitmap = dot11_cap.ba_32bit_bitmap;
he_cap->mu_cascade = dot11_cap.mu_cascade;
he_cap->ack_enabled_multitid = dot11_cap.ack_enabled_multitid;
he_cap->dl_mu_ba = dot11_cap.dl_mu_ba;
he_cap->omi_a_ctrl = dot11_cap.omi_a_ctrl;
he_cap->ofdma_ra = dot11_cap.ofdma_ra;
he_cap->max_ampdu_len = dot11_cap.max_ampdu_len;
he_cap->max_ampdu_len_exp_ext = dot11_cap.max_ampdu_len_exp_ext;
he_cap->amsdu_frag = dot11_cap.amsdu_frag;
he_cap->flex_twt_sched = dot11_cap.flex_twt_sched;
he_cap->rx_ctrl_frame = dot11_cap.rx_ctrl_frame;
@ -7736,14 +7756,13 @@ void lim_set_he_caps(tpAniSirGlobal mac, tpPESession session, uint8_t *ie_start,
he_cap->bsrp_ampdu_aggr = dot11_cap.bsrp_ampdu_aggr;
he_cap->qtp = dot11_cap.qtp;
he_cap->a_bqr = dot11_cap.a_bqr;
he_cap->sr_responder = dot11_cap.sr_responder;
he_cap->spatial_reuse_param_rspder =
dot11_cap.spatial_reuse_param_rspder;
he_cap->ops_supp = dot11_cap.ops_supp;
he_cap->ndp_feedback_supp = dot11_cap.ndp_feedback_supp;
he_cap->amsdu_in_ampdu = dot11_cap.amsdu_in_ampdu;
he_cap->reserved1 = dot11_cap.reserved1;
he_cap->dual_band = dot11_cap.dual_band;
he_cap->chan_width = HE_CH_WIDTH_COMBINE(dot11_cap.chan_width_0,
dot11_cap.chan_width_1, dot11_cap.chan_width_2,
dot11_cap.chan_width_3, dot11_cap.chan_width_4,
@ -7753,7 +7772,8 @@ void lim_set_he_caps(tpAniSirGlobal mac, tpPESession session, uint8_t *ie_start,
he_cap->device_class = dot11_cap.device_class;
he_cap->ldpc_coding = dot11_cap.ldpc_coding;
he_cap->he_1x_ltf_800_gi_ppdu = dot11_cap.he_1x_ltf_800_gi_ppdu;
he_cap->midamble_rx_max_nsts = dot11_cap.midamble_rx_max_nsts;
he_cap->midamble_tx_rx_max_nsts =
dot11_cap.midamble_tx_rx_max_nsts;
he_cap->he_4x_ltf_3200_gi_ndp = dot11_cap.he_4x_ltf_3200_gi_ndp;
he_cap->tx_stbc_lt_80mhz = dot11_cap.tx_stbc_lt_80mhz;
he_cap->rx_stbc_lt_80mhz = dot11_cap.rx_stbc_lt_80mhz;
@ -7794,8 +7814,8 @@ void lim_set_he_caps(tpAniSirGlobal mac, tpPESession session, uint8_t *ie_start,
dot11_cap.he_ppdu_80_in_160_80p80Mhz;
he_cap->er_1x_he_ltf_gi =
dot11_cap.er_1x_he_ltf_gi;
he_cap->midamble_rx_1x_he_ltf =
dot11_cap.midamble_rx_1x_he_ltf;
he_cap->midamble_tx_rx_1x_he_ltf =
dot11_cap.midamble_tx_rx_1x_he_ltf;
he_cap->reserved2 = dot11_cap.reserved2;
he_cap->rx_he_mcs_map_lt_80 = dot11_cap.rx_he_mcs_map_lt_80;

1940
core/mac/src/sys/legacy/src/utils/src/dot11f.c
View file

File diff suppressed because it is too large Load diff

52
core/mac/src/sys/legacy/src/utils/src/parser_api.c
View file

@ -6126,20 +6126,20 @@ QDF_STATUS populate_dot11f_he_caps(tpAniSirGlobal mac_ctx, tpPESession session,
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_FRAGMENTATION, value);
he_cap->fragmentation = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_MAX_FRAG_MSDU, value);
he_cap->max_num_frag_msdu = value;
he_cap->max_num_frag_msdu_amsdu_exp = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_MIN_FRAG_SIZE, value);
he_cap->min_frag_size = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_TRIG_PAD, value);
he_cap->trigger_frm_mac_pad = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_MTID_AGGR, value);
he_cap->multi_tid_aggr = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_MTID_AGGR_RX, value);
he_cap->multi_tid_aggr_rx_supp = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_LINK_ADAPTATION, value);
he_cap->he_link_adaptation = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_ALL_ACK, value);
he_cap->all_ack = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_UL_MU_RSP_SCHEDULING,
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_TRIGD_RSP_SCHEDULING,
value);
he_cap->ul_mu_rsp_sched = value;
he_cap->trigd_rsp_sched = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_BUFFER_STATUS_RPT,
value);
he_cap->a_bsr = value;
@ -6151,14 +6151,12 @@ QDF_STATUS populate_dot11f_he_caps(tpAniSirGlobal mac_ctx, tpPESession session,
he_cap->mu_cascade = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_MULTI_TID, value);
he_cap->ack_enabled_multitid = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_DL_MU_BA, value);
he_cap->dl_mu_ba = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_OMI, value);
he_cap->omi_a_ctrl = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_OFDMA_RA, value);
he_cap->ofdma_ra = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_MAX_AMPDU_LEN, value);
he_cap->max_ampdu_len = value;
he_cap->max_ampdu_len_exp_ext = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_AMSDU_FRAG, value);
he_cap->amsdu_frag = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_FLEX_TWT_SCHED, value);
@ -6172,7 +6170,7 @@ QDF_STATUS populate_dot11f_he_caps(tpAniSirGlobal mac_ctx, tpPESession session,
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_A_BQR, value);
he_cap->a_bqr = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_SR_RESPONDER, value);
he_cap->sr_responder = value;
he_cap->spatial_reuse_param_rspder = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_NDP_FEEDBACK_SUPP,
value);
he_cap->ndp_feedback_supp = value;
@ -6180,9 +6178,14 @@ QDF_STATUS populate_dot11f_he_caps(tpAniSirGlobal mac_ctx, tpPESession session,
he_cap->ops_supp = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_AMSDU_IN_AMPDU, value);
he_cap->amsdu_in_ampdu = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_SUB_CH_SEL_TX, value);
he_cap->he_sub_ch_sel_tx_supp = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_UL_2X996_RU, value);
he_cap->ul_2x996_tone_ru_supp = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX,
value);
he_cap->om_ctrl_ul_mu_data_dis_rx = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_DUAL_BAND, value);
he_cap->dual_band = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_CHAN_WIDTH, value);
he_cap->chan_width_0 = HE_CH_WIDTH_GET_BIT(value, 0);
he_cap->chan_width_1 = HE_CH_WIDTH_GET_BIT(value, 1);
@ -6202,7 +6205,7 @@ QDF_STATUS populate_dot11f_he_caps(tpAniSirGlobal mac_ctx, tpPESession session,
he_cap->he_1x_ltf_800_gi_ppdu = value;
CFG_GET_INT(status, mac_ctx,
WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS, value);
he_cap->midamble_rx_max_nsts = value;
he_cap->midamble_tx_rx_max_nsts = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_LTF_NDP, value);
he_cap->he_4x_ltf_3200_gi_ndp = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_TX_STBC_LT80, value);
@ -6275,8 +6278,29 @@ QDF_STATUS populate_dot11f_he_caps(tpAniSirGlobal mac_ctx, tpPESession session,
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_ER_1X_HE_LTF_GI, value);
he_cap->er_1x_he_ltf_gi = value;
CFG_GET_INT(status, mac_ctx,
WNI_CFG_HE_MIDAMBLE_RX_1X_HE_LTF, value);
he_cap->midamble_rx_1x_he_ltf = value;
WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF, value);
he_cap->midamble_tx_rx_1x_he_ltf = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_DCM_MAX_BW, value);
he_cap->dcm_max_bw = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM,
value);
he_cap->longer_than_16_he_sigb_ofdm_sym = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_TX_1024_QAM_LT_242_RU,
value);
he_cap->tx_1024_qam_lt_242_tone_ru = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_RX_1024_QAM_LT_242_RU,
value);
he_cap->rx_1024_qam_lt_242_tone_ru = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK,
value);
he_cap->non_trig_cqi_feedback = value;
CFG_GET_INT(status, mac_ctx, WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB,
value);
he_cap->rx_full_bw_su_he_mu_compress_sigb = value;
CFG_GET_INT(status, mac_ctx,
WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB,
value);
he_cap->rx_full_bw_su_he_mu_non_cmpr_sigb = value;
CFG_GET_INT(status, mac_ctx,
WNI_CFG_HE_RX_MCS_MAP_LT_80, value);
he_cap->rx_he_mcs_map_lt_80 = value;

45
core/sme/src/csr/csr_api_roam.c
View file

@ -2508,19 +2508,19 @@ void csr_update_session_he_cap(tpAniSirGlobal mac_ctx,
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_FRAGMENTATION, &value);
he_cap->fragmentation = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_MAX_FRAG_MSDU, &value);
he_cap->max_num_frag_msdu = value;
he_cap->max_num_frag_msdu_amsdu_exp = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_MIN_FRAG_SIZE, &value);
he_cap->min_frag_size = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_TRIG_PAD, &value);
he_cap->trigger_frm_mac_pad = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_MTID_AGGR, &value);
he_cap->multi_tid_aggr = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_MTID_AGGR_RX, &value);
he_cap->multi_tid_aggr_rx_supp = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_LINK_ADAPTATION, &value);
he_cap->he_link_adaptation = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_ALL_ACK, &value);
he_cap->all_ack = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_UL_MU_RSP_SCHEDULING, &value);
he_cap->ul_mu_rsp_sched = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_TRIGD_RSP_SCHEDULING, &value);
he_cap->trigd_rsp_sched = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_BUFFER_STATUS_RPT, &value);
he_cap->a_bsr = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_BCAST_TWT, &value);
@ -2531,14 +2531,12 @@ void csr_update_session_he_cap(tpAniSirGlobal mac_ctx,
he_cap->mu_cascade = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_MULTI_TID, &value);
he_cap->ack_enabled_multitid = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_DL_MU_BA, &value);
he_cap->dl_mu_ba = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_OMI, &value);
he_cap->omi_a_ctrl = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_OFDMA_RA, &value);
he_cap->ofdma_ra = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_MAX_AMPDU_LEN, &value);
he_cap->max_ampdu_len = value;
he_cap->max_ampdu_len_exp_ext = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_AMSDU_FRAG, &value);
he_cap->amsdu_frag = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_FLEX_TWT_SCHED, &value);
@ -2552,16 +2550,20 @@ void csr_update_session_he_cap(tpAniSirGlobal mac_ctx,
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_A_BQR, &value);
he_cap->a_bqr = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_SR_RESPONDER, &value);
he_cap->sr_responder = value;
he_cap->spatial_reuse_param_rspder = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_NDP_FEEDBACK_SUPP, &value);
he_cap->ndp_feedback_supp = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_OPS_SUPP, &value);
he_cap->ops_supp = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_AMSDU_IN_AMPDU, &value);
he_cap->amsdu_in_ampdu = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_SUB_CH_SEL_TX, &value);
he_cap->he_sub_ch_sel_tx_supp = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_UL_2X996_RU, &value);
he_cap->ul_2x996_tone_ru_supp = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_OM_CTRL_UL_MU_DIS_RX, &value);
he_cap->om_ctrl_ul_mu_data_dis_rx = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_DUAL_BAND, &value);
he_cap->dual_band = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_CHAN_WIDTH, &value);
he_cap->chan_width_0 = HE_CH_WIDTH_GET_BIT(value, 0);
he_cap->chan_width_1 = HE_CH_WIDTH_GET_BIT(value, 1);
@ -2580,7 +2582,7 @@ void csr_update_session_he_cap(tpAniSirGlobal mac_ctx,
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_LTF_PPDU, &value);
he_cap->he_1x_ltf_800_gi_ppdu = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_MIDAMBLE_RX_MAX_NSTS, &value);
he_cap->midamble_rx_max_nsts = value;
he_cap->midamble_tx_rx_max_nsts = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_LTF_NDP, &value);
he_cap->he_4x_ltf_3200_gi_ndp = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_TX_STBC_LT80, &value);
@ -2660,8 +2662,23 @@ void csr_update_session_he_cap(tpAniSirGlobal mac_ctx,
he_cap->he_ppdu_80_in_160_80p80Mhz = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_ER_1X_HE_LTF_GI, &value);
he_cap->er_1x_he_ltf_gi = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_MIDAMBLE_RX_1X_HE_LTF, &value);
he_cap->midamble_rx_1x_he_ltf = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF, &value);
he_cap->midamble_tx_rx_1x_he_ltf = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_DCM_MAX_BW, &value);
he_cap->dcm_max_bw = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_LONGER_16_SIGB_OFDM_SYM, &value);
he_cap->longer_than_16_he_sigb_ofdm_sym = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_TX_1024_QAM_LT_242_RU, &value);
he_cap->tx_1024_qam_lt_242_tone_ru = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_RX_1024_QAM_LT_242_RU, &value);
he_cap->rx_1024_qam_lt_242_tone_ru = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_NON_TRIG_CQI_FEEDBACK, &value);
he_cap->non_trig_cqi_feedback = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_RX_FULL_BW_MU_CMPR_SIGB, &value);
he_cap->rx_full_bw_su_he_mu_compress_sigb = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB,
&value);
he_cap->rx_full_bw_su_he_mu_non_cmpr_sigb = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_RX_MCS_MAP_LT_80, &value);
he_cap->rx_he_mcs_map_lt_80 = value;
sme_cfg_get_int(mac_hdl, WNI_CFG_HE_TX_MCS_MAP_LT_80, &value);

4
core/wma/inc/wma_api.h
View file

@ -76,8 +76,8 @@ struct wma_caps_per_phy {
uint32_t ht_5g;
uint32_t vht_2g;
uint32_t vht_5g;
uint32_t he_2g;
uint32_t he_5g;
uint32_t he_2g[PSOC_HOST_MAX_MAC_SIZE];
uint32_t he_5g[PSOC_HOST_MAX_MAC_SIZE];
uint32_t tx_chain_mask_2G;
uint32_t rx_chain_mask_2G;
uint32_t tx_chain_mask_5G;

20
core/wma/inc/wma_he.h
View file

@ -59,14 +59,24 @@ void wma_print_he_ppet(void *ppet);
void wma_print_he_phy_cap(uint32_t *phy_cap);
/**
* wma_print_he_mac_cap() - Print HE MAC Capability
* wma_print_he_mac_cap_w1() - Print HE MAC Capability
* @mac_cap: MAC Capability
*
* This function prints HE MAC Capability received from FW.
*
* Return: none
*/
void wma_print_he_mac_cap(uint32_t mac_cap);
void wma_print_he_mac_cap_w1(uint32_t mac_cap);
/**
* wma_print_he_mac_cap_w2() - Print HE MAC Capability
* @mac_cap: MAC Capability
*
* This function prints HE MAC Capability received from FW.
*
* Return: none
*/
void wma_print_he_mac_cap_w2(uint32_t mac_cap);
/**
* wma_print_he_op() - Print HE Operation
@ -243,7 +253,11 @@ static inline void wma_print_he_phy_cap(uint32_t *phy_cap)
{
}
static inline void wma_print_he_mac_cap(uint32_t mac_cap)
static inline void wma_print_he_mac_cap_w1(uint32_t mac_cap)
{
}
static inline void wma_print_he_mac_cap_w2(uint32_t mac_cap)
{
}

360
core/wma/src/wma_he.c
View file

@ -169,7 +169,7 @@ static void wma_convert_he_ppet(uint8_t *he_ppet,
*
* Return: None
*/
static void wma_convert_he_cap(tDot11fIEhe_cap *he_cap, uint32_t mac_cap,
static void wma_convert_he_cap(tDot11fIEhe_cap *he_cap, uint32_t *mac_cap,
uint32_t *phy_cap, uint32_t supp_mcs,
uint32_t tx_chain_mask, uint32_t rx_chain_mask)
{
@ -181,38 +181,47 @@ static void wma_convert_he_cap(tDot11fIEhe_cap *he_cap, uint32_t mac_cap,
he_cap->present = true;
/* HE MAC capabilities */
he_cap->htc_he = WMI_HECAP_MAC_HECTRL_GET(mac_cap);
he_cap->twt_request = WMI_HECAP_MAC_TWTREQ_GET(mac_cap);
he_cap->twt_responder = WMI_HECAP_MAC_TWTRSP_GET(mac_cap);
he_cap->fragmentation = WMI_HECAP_MAC_HEFRAG_GET(mac_cap);
he_cap->max_num_frag_msdu = WMI_HECAP_MAC_MAXFRAGMSDU_GET(mac_cap);
he_cap->min_frag_size = WMI_HECAP_MAC_MINFRAGSZ_GET(mac_cap);
he_cap->trigger_frm_mac_pad = WMI_HECAP_MAC_TRIGPADDUR_GET(mac_cap);
he_cap->multi_tid_aggr = WMI_HECAP_MAC_ACKMTIDAMPDU_GET(mac_cap);
he_cap->he_link_adaptation = WMI_HECAP_MAC_HELKAD_GET(mac_cap);
he_cap->all_ack = WMI_HECAP_MAC_AACK_GET(mac_cap);
he_cap->ul_mu_rsp_sched = WMI_HECAP_MAC_ULMURSP_GET(mac_cap);
he_cap->a_bsr = WMI_HECAP_MAC_BSR_GET(mac_cap);
he_cap->broadcast_twt = WMI_HECAP_MAC_BCSTTWT_GET(mac_cap);
he_cap->ba_32bit_bitmap = WMI_HECAP_MAC_32BITBA_GET(mac_cap);
he_cap->mu_cascade = WMI_HECAP_MAC_MUCASCADE_GET(mac_cap);
he_cap->ack_enabled_multitid = WMI_HECAP_MAC_ACKMTIDAMPDU_GET(mac_cap);
he_cap->dl_mu_ba = WMI_HECAP_MAC_GROUPMSTABA_GET(mac_cap);
he_cap->omi_a_ctrl = WMI_HECAP_MAC_OMI_GET(mac_cap);
he_cap->ofdma_ra = WMI_HECAP_MAC_OFDMARA_GET(mac_cap);
he_cap->max_ampdu_len = WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET(mac_cap);
he_cap->amsdu_frag = WMI_HECAP_MAC_AMSDUFRAG_GET(mac_cap);
he_cap->flex_twt_sched = WMI_HECAP_MAC_FLEXTWT_GET(mac_cap);
he_cap->rx_ctrl_frame = WMI_HECAP_MAC_MBSS_GET(mac_cap);
he_cap->bsrp_ampdu_aggr = WMI_HECAP_MAC_BSRPAMPDU_GET(mac_cap);
he_cap->qtp = WMI_HECAP_MAC_QTP_GET(mac_cap);
he_cap->a_bqr = WMI_HECAP_MAC_ABQR_GET(mac_cap);
he_cap->sr_responder = WMI_HECAP_MAC_SRRESP_GET(mac_cap);
he_cap->ndp_feedback_supp = WMI_HECAP_MAC_NDPFDBKRPT_GET(mac_cap);
he_cap->ops_supp = WMI_HECAP_MAC_OPS_GET(mac_cap);
he_cap->amsdu_in_ampdu = WMI_HECAP_MAC_AMSDUINAMPDU_GET(mac_cap);
he_cap->htc_he = WMI_HECAP_MAC_HECTRL_GET(mac_cap[0]);
he_cap->twt_request = WMI_HECAP_MAC_TWTREQ_GET(mac_cap[0]);
he_cap->twt_responder = WMI_HECAP_MAC_TWTRSP_GET(mac_cap[0]);
he_cap->fragmentation = WMI_HECAP_MAC_HEFRAG_GET(mac_cap[0]);
he_cap->max_num_frag_msdu_amsdu_exp =
WMI_HECAP_MAC_MAXFRAGMSDU_GET(mac_cap[0]);
he_cap->min_frag_size = WMI_HECAP_MAC_MINFRAGSZ_GET(mac_cap[0]);
he_cap->trigger_frm_mac_pad = WMI_HECAP_MAC_TRIGPADDUR_GET(mac_cap[0]);
he_cap->multi_tid_aggr_rx_supp =
WMI_HECAP_MAC_ACKMTIDAMPDU_GET(mac_cap[0]);
he_cap->he_link_adaptation = WMI_HECAP_MAC_HELINK_ADPT_GET(mac_cap[0]);
he_cap->all_ack = WMI_HECAP_MAC_AACK_GET(mac_cap[0]);
he_cap->trigd_rsp_sched = WMI_HECAP_MAC_TRS_GET(mac_cap[0]);
he_cap->a_bsr = WMI_HECAP_MAC_BSR_GET(mac_cap[0]);
he_cap->broadcast_twt = WMI_HECAP_MAC_BCSTTWT_GET(mac_cap[0]);
he_cap->ba_32bit_bitmap = WMI_HECAP_MAC_32BITBA_GET(mac_cap[0]);
he_cap->mu_cascade = WMI_HECAP_MAC_MUCASCADE_GET(mac_cap[0]);
he_cap->ack_enabled_multitid =
WMI_HECAP_MAC_ACKMTIDAMPDU_GET(mac_cap[0]);
he_cap->omi_a_ctrl = WMI_HECAP_MAC_OMI_GET(mac_cap[0]);
he_cap->ofdma_ra = WMI_HECAP_MAC_OFDMARA_GET(mac_cap[0]);
he_cap->max_ampdu_len_exp_ext =
WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET(mac_cap[0]);
he_cap->amsdu_frag = WMI_HECAP_MAC_AMSDUFRAG_GET(mac_cap[0]);
he_cap->flex_twt_sched = WMI_HECAP_MAC_FLEXTWT_GET(mac_cap[0]);
he_cap->rx_ctrl_frame = WMI_HECAP_MAC_MBSS_GET(mac_cap[0]);
he_cap->bsrp_ampdu_aggr = WMI_HECAP_MAC_BSRPAMPDU_GET(mac_cap[1]);
he_cap->qtp = WMI_HECAP_MAC_QTP_GET(mac_cap[1]);
he_cap->a_bqr = WMI_HECAP_MAC_ABQR_GET(mac_cap[1]);
he_cap->spatial_reuse_param_rspder =
WMI_HECAP_MAC_SRPRESP_GET(mac_cap[1]);
he_cap->ndp_feedback_supp = WMI_HECAP_MAC_NDPFDBKRPT_GET(mac_cap[1]);
he_cap->ops_supp = WMI_HECAP_MAC_OPS_GET(mac_cap[1]);
he_cap->amsdu_in_ampdu = WMI_HECAP_MAC_AMSDUINAMPDU_GET(mac_cap[1]);
he_cap->multi_tid_aggr_tx_supp = WMI_HECAP_MAC_MTID_TX_GET(mac_cap[1]);
he_cap->he_sub_ch_sel_tx_supp =
WMI_HECAP_MAC_SUBCHANSELTX_GET(mac_cap[1]);
he_cap->ul_2x996_tone_ru_supp = WMI_HECAP_MAC_UL2X996RU_GET(mac_cap[1]);
he_cap->om_ctrl_ul_mu_data_dis_rx =
WMI_HECAP_MAC_OMCULMUDDIS_GET(mac_cap[1]);
/* HE PHY capabilities */
he_cap->dual_band = WMI_HECAP_PHY_DB_GET(phy_cap);
chan_width = WMI_HECAP_PHY_CBW_GET(phy_cap);
he_cap->chan_width_0 = HE_CH_WIDTH_GET_BIT(chan_width, 0);
he_cap->chan_width_1 = HE_CH_WIDTH_GET_BIT(chan_width, 1);
@ -225,8 +234,8 @@ static void wma_convert_he_cap(tDot11fIEhe_cap *he_cap, uint32_t mac_cap,
he_cap->device_class = WMI_HECAP_PHY_COD_GET(phy_cap);
he_cap->ldpc_coding = WMI_HECAP_PHY_LDPC_GET(phy_cap);
he_cap->he_1x_ltf_800_gi_ppdu = WMI_HECAP_PHY_LTFGIFORHE_GET(phy_cap);
he_cap->midamble_rx_max_nsts =
WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_GET(phy_cap);
he_cap->midamble_tx_rx_max_nsts =
WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_GET(phy_cap);
he_cap->he_4x_ltf_3200_gi_ndp = WMI_HECAP_PHY_LTFGIFORNDP_GET(phy_cap);
he_cap->rx_stbc_lt_80mhz = WMI_HECAP_PHY_RXSTBC_GET(phy_cap);
he_cap->tx_stbc_lt_80mhz = WMI_HECAP_PHY_TXSTBC_GET(phy_cap);
@ -234,7 +243,7 @@ static void wma_convert_he_cap(tDot11fIEhe_cap *he_cap, uint32_t mac_cap,
he_cap->tx_stbc_gt_80mhz = WMI_HECAP_PHY_STBCTXGT80_GET(phy_cap);
he_cap->doppler = (WMI_HECAP_PHY_RXDOPPLER_GET(phy_cap) << 1) |
WMI_HECAP_PHY_TXDOPPLER_GET(phy_cap);
WMI_HECAP_PHY_TXDOPPLER(phy_cap);
he_cap->ul_mu = (WMI_HECAP_PHY_ULMUMIMOOFDMA_GET(phy_cap) << 1) |
WMI_HECAP_PHY_UL_MU_MIMO_GET(phy_cap);
he_cap->dcm_enc_tx = WMI_HECAP_PHY_DCMTX_GET(phy_cap);
@ -243,7 +252,7 @@ static void wma_convert_he_cap(tDot11fIEhe_cap *he_cap, uint32_t mac_cap,
he_cap->su_beamformer = WMI_HECAP_PHY_SUBFMR_GET(phy_cap);
he_cap->su_beamformee = WMI_HECAP_PHY_SUBFME_GET(phy_cap);
he_cap->mu_beamformer = WMI_HECAP_PHY_MUBFMR_GET(phy_cap);
he_cap->bfee_sts_lt_80 = WMI_HECAP_PHY_SUBFMESTS_GET(phy_cap);
he_cap->bfee_sts_lt_80 = WMI_HECAP_PHY_BFMESTSLT80MHZ_GET(phy_cap);
he_cap->bfee_sts_gt_80 = WMI_HECAP_PHY_BFMESTSGT80MHZ_GET(phy_cap);
he_cap->num_sounding_lt_80 = WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET(phy_cap);
he_cap->num_sounding_gt_80 = WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET(phy_cap);
@ -264,6 +273,8 @@ static void wma_convert_he_cap(tDot11fIEhe_cap *he_cap, uint32_t mac_cap,
he_cap->he_ltf_800_gi_4x =
WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET(phy_cap);
he_cap->max_nc = WMI_HECAP_PHY_MAXNC_GET(phy_cap);
he_cap->tx_stbc_gt_80mhz = WMI_HECAP_PHY_STBCTXGT80_GET(phy_cap);
he_cap->rx_stbc_gt_80mhz = WMI_HECAP_PHY_STBCRXGT80_GET(phy_cap);
he_cap->er_he_ltf_800_gi_4x =
WMI_HECAP_PHY_ERSU4X800NSECGI_GET(phy_cap);
he_cap->he_ppdu_20_in_40Mhz_2G =
@ -273,8 +284,22 @@ static void wma_convert_he_cap(tDot11fIEhe_cap *he_cap, uint32_t mac_cap,
he_cap->he_ppdu_80_in_160_80p80Mhz =
WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET(phy_cap);
he_cap->er_1x_he_ltf_gi = WMI_HECAP_PHY_ERSU1X800NSECGI_GET(phy_cap);
he_cap->midamble_rx_1x_he_ltf =
WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_GET(phy_cap);
he_cap->midamble_tx_rx_1x_he_ltf =
WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_GET(phy_cap);
he_cap->dcm_max_bw = WMI_HECAP_PHY_DCMMAXBW_GET(phy_cap);
he_cap->longer_than_16_he_sigb_ofdm_sym =
WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_GET(phy_cap);
he_cap->non_trig_cqi_feedback =
WMI_HECAP_PHY_NONTRIGCQIFEEDBK_GET(phy_cap);
he_cap->tx_1024_qam_lt_242_tone_ru =
WMI_HECAP_PHY_TX1024QAM242RUSUPRT_GET(phy_cap);
he_cap->rx_1024_qam_lt_242_tone_ru =
WMI_HECAP_PHY_RX1024QAM242RUSUPRT_GET(phy_cap);
he_cap->rx_full_bw_su_he_mu_compress_sigb =
WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_GET(phy_cap);
he_cap->rx_full_bw_su_he_mu_non_cmpr_sigb =
WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_GET(phy_cap);
/*
* supp_mcs is split into 16 bits with lower indicating le_80 and
@ -331,21 +356,22 @@ static void wma_derive_ext_he_cap(tDot11fIEhe_cap *he_cap,
new_cap->twt_responder);
he_cap->fragmentation = QDF_MIN(he_cap->fragmentation,
new_cap->fragmentation);
he_cap->max_num_frag_msdu = QDF_MIN(he_cap->max_num_frag_msdu,
new_cap->max_num_frag_msdu);
he_cap->max_num_frag_msdu_amsdu_exp = QDF_MIN(
he_cap->max_num_frag_msdu_amsdu_exp,
new_cap->max_num_frag_msdu_amsdu_exp);
he_cap->min_frag_size = QDF_MIN(he_cap->min_frag_size,
new_cap->min_frag_size);
he_cap->trigger_frm_mac_pad =
QDF_MIN(he_cap->trigger_frm_mac_pad,
new_cap->trigger_frm_mac_pad);
he_cap->multi_tid_aggr = QDF_MIN(he_cap->multi_tid_aggr,
new_cap->multi_tid_aggr);
he_cap->multi_tid_aggr_rx_supp = QDF_MIN(he_cap->multi_tid_aggr_rx_supp,
new_cap->multi_tid_aggr_rx_supp);
he_cap->he_link_adaptation = QDF_MIN(he_cap->he_link_adaptation,
new_cap->he_link_adaptation);
he_cap->all_ack = QDF_MIN(he_cap->all_ack,
new_cap->all_ack);
he_cap->ul_mu_rsp_sched = QDF_MIN(he_cap->ul_mu_rsp_sched,
new_cap->ul_mu_rsp_sched);
he_cap->trigd_rsp_sched = QDF_MIN(he_cap->trigd_rsp_sched,
new_cap->trigd_rsp_sched);
he_cap->a_bsr = QDF_MIN(he_cap->a_bsr,
new_cap->a_bsr);
he_cap->broadcast_twt = QDF_MIN(he_cap->broadcast_twt,
@ -357,14 +383,12 @@ static void wma_derive_ext_he_cap(tDot11fIEhe_cap *he_cap,
he_cap->ack_enabled_multitid =
QDF_MIN(he_cap->ack_enabled_multitid,
new_cap->ack_enabled_multitid);
he_cap->dl_mu_ba = QDF_MIN(he_cap->dl_mu_ba,
new_cap->dl_mu_ba);
he_cap->omi_a_ctrl = QDF_MIN(he_cap->omi_a_ctrl,
new_cap->omi_a_ctrl);
he_cap->ofdma_ra = QDF_MIN(he_cap->ofdma_ra,
new_cap->ofdma_ra);
he_cap->max_ampdu_len = QDF_MIN(he_cap->max_ampdu_len,
new_cap->max_ampdu_len);
he_cap->max_ampdu_len_exp_ext = QDF_MIN(he_cap->max_ampdu_len_exp_ext,
new_cap->max_ampdu_len_exp_ext);
he_cap->amsdu_frag = QDF_MIN(he_cap->amsdu_frag,
new_cap->amsdu_frag);
he_cap->flex_twt_sched = QDF_MIN(he_cap->flex_twt_sched,
@ -375,8 +399,9 @@ static void wma_derive_ext_he_cap(tDot11fIEhe_cap *he_cap,
new_cap->bsrp_ampdu_aggr);
he_cap->qtp = QDF_MIN(he_cap->qtp, new_cap->qtp);
he_cap->a_bqr = QDF_MIN(he_cap->a_bqr, new_cap->a_bqr);
he_cap->sr_responder = QDF_MIN(he_cap->sr_responder,
new_cap->sr_responder);
he_cap->spatial_reuse_param_rspder = QDF_MIN(
he_cap->spatial_reuse_param_rspder,
new_cap->spatial_reuse_param_rspder);
he_cap->ndp_feedback_supp = QDF_MIN(he_cap->ndp_feedback_supp,
new_cap->ndp_feedback_supp);
he_cap->ops_supp = QDF_MIN(he_cap->ops_supp, new_cap->ops_supp);
@ -385,9 +410,6 @@ static void wma_derive_ext_he_cap(tDot11fIEhe_cap *he_cap,
he_cap->reserved1 = QDF_MIN(he_cap->reserved1,
new_cap->reserved1);
he_cap->dual_band = QDF_MIN(he_cap->dual_band,
new_cap->dual_band);
he_cap->chan_width_0 = he_cap->chan_width_0 | new_cap->chan_width_0;
he_cap->chan_width_1 = he_cap->chan_width_1 | new_cap->chan_width_1;
he_cap->chan_width_2 = he_cap->chan_width_2 | new_cap->chan_width_2;
@ -406,9 +428,9 @@ static void wma_derive_ext_he_cap(tDot11fIEhe_cap *he_cap,
he_cap->he_1x_ltf_800_gi_ppdu =
QDF_MIN(he_cap->he_1x_ltf_800_gi_ppdu,
new_cap->he_1x_ltf_800_gi_ppdu);
he_cap->midamble_rx_max_nsts =
QDF_MIN(he_cap->midamble_rx_max_nsts,
new_cap->midamble_rx_max_nsts);
he_cap->midamble_tx_rx_max_nsts =
QDF_MIN(he_cap->midamble_tx_rx_max_nsts,
new_cap->midamble_tx_rx_max_nsts);
he_cap->he_4x_ltf_3200_gi_ndp =
QDF_MIN(he_cap->he_4x_ltf_3200_gi_ndp,
new_cap->he_4x_ltf_3200_gi_ndp);
@ -474,9 +496,9 @@ static void wma_derive_ext_he_cap(tDot11fIEhe_cap *he_cap,
new_cap->he_ppdu_80_in_160_80p80Mhz);
he_cap->er_1x_he_ltf_gi = QDF_MIN(he_cap->er_1x_he_ltf_gi,
new_cap->er_1x_he_ltf_gi);
he_cap->midamble_rx_1x_he_ltf =
QDF_MIN(he_cap->midamble_rx_1x_he_ltf,
new_cap->midamble_rx_1x_he_ltf);
he_cap->midamble_tx_rx_1x_he_ltf =
QDF_MIN(he_cap->midamble_tx_rx_1x_he_ltf,
new_cap->midamble_tx_rx_1x_he_ltf);
he_cap->reserved2 = QDF_MIN(he_cap->reserved2,
new_cap->reserved2);
@ -522,37 +544,46 @@ void wma_print_he_cap(tDot11fIEhe_cap *he_cap)
WMA_LOGD("\tTWT Requestor support: 0x%01x", he_cap->twt_request);
WMA_LOGD("\tTWT Responder support: 0x%01x", he_cap->twt_responder);
WMA_LOGD("\tFragmentation support: 0x%02x", he_cap->fragmentation);
WMA_LOGD("\tMax no.of frag MSDUs: 0x%03x", he_cap->max_num_frag_msdu);
WMA_LOGD("\tMax no.of frag MSDUs: 0x%03x",
he_cap->max_num_frag_msdu_amsdu_exp);
WMA_LOGD("\tMin. frag size: 0x%02x", he_cap->min_frag_size);
WMA_LOGD("\tTrigger MAC pad duration: 0x%02x",
he_cap->trigger_frm_mac_pad);
WMA_LOGD("\tMulti-TID aggr support: 0x%03x", he_cap->multi_tid_aggr);
WMA_LOGD("\tMulti-TID aggr RX support: 0x%03x",
he_cap->multi_tid_aggr_rx_supp);
WMA_LOGD("\tLink adaptation: 0x%02x", he_cap->he_link_adaptation);
WMA_LOGD("\tAll ACK support: 0x%01x", he_cap->all_ack);
WMA_LOGD("\tUL MU resp. scheduling: 0x%01x", he_cap->ul_mu_rsp_sched);
WMA_LOGD("\tTriggered resp. scheduling: 0x%01x",
he_cap->trigd_rsp_sched);
WMA_LOGD("\tA-Buff status report: 0x%01x", he_cap->a_bsr);
WMA_LOGD("\tBroadcast TWT support: 0x%01x", he_cap->broadcast_twt);
WMA_LOGD("\t32bit BA bitmap support: 0x%01x", he_cap->ba_32bit_bitmap);
WMA_LOGD("\tMU Cascading support: 0x%01x", he_cap->mu_cascade);
WMA_LOGD("\tACK enabled Multi-TID: 0x%01x",
he_cap->ack_enabled_multitid);
WMA_LOGD("\tMulti-STA BA in DL MU: 0x%01x", he_cap->dl_mu_ba);
WMA_LOGD("\tOMI A-Control support: 0x%01x", he_cap->omi_a_ctrl);
WMA_LOGD("\tOFDMA RA support: 0x%01x", he_cap->ofdma_ra);
WMA_LOGD("\tMax A-MPDU Length: 0x%02x", he_cap->max_ampdu_len);
WMA_LOGD("\tMax A-MPDU Length: 0x%02x", he_cap->max_ampdu_len_exp_ext);
WMA_LOGD("\tA-MSDU Fragmentation: 0x%01x", he_cap->amsdu_frag);
WMA_LOGD("\tFlex. TWT sched support: 0x%01x", he_cap->flex_twt_sched);
WMA_LOGD("\tRx Ctrl frame to MBSS: 0x%01x", he_cap->rx_ctrl_frame);
WMA_LOGD("\tBSRP A-MPDU Aggregation: 0x%01x", he_cap->bsrp_ampdu_aggr);
WMA_LOGD("\tQuite Time Period support: 0x%01x", he_cap->qtp);
WMA_LOGD("\tA-BQR support: 0x%01x", he_cap->a_bqr);
WMA_LOGD("\t SR Responder: 0x%01x", he_cap->sr_responder);
WMA_LOGD("\t ndp feedback supp: 0x%01x", he_cap->ndp_feedback_supp);
WMA_LOGD("\t ops supp: 0x%01x", he_cap->ops_supp);
WMA_LOGD("\t amsdu in ampdu: 0x%01x", he_cap->amsdu_in_ampdu);
WMA_LOGD("\tSR Responder: 0x%01x", he_cap->spatial_reuse_param_rspder);
WMA_LOGD("\tndp feedback supp: 0x%01x", he_cap->ndp_feedback_supp);
WMA_LOGD("\tops supp: 0x%01x", he_cap->ops_supp);
WMA_LOGD("\tamsdu in ampdu: 0x%01x", he_cap->amsdu_in_ampdu);
WMA_LOGD("\tMulti-TID aggr Tx support: 0x%03x",
he_cap->multi_tid_aggr_tx_supp);
WMA_LOGD("\tHE sub ch sel tx supp: 0x%01x",
he_cap->he_sub_ch_sel_tx_supp);
WMA_LOGD("\tUL 2x996 tone RU supp: 0x%01x",
he_cap->ul_2x996_tone_ru_supp);
WMA_LOGD("\tOM ctrl UL MU data dis rx supp: 0x%01x",
he_cap->om_ctrl_ul_mu_data_dis_rx);
/* HE PHY capabilities */
WMA_LOGD("\tDual band support: 0x%01x", he_cap->dual_band);
chan_width = HE_CH_WIDTH_COMBINE(he_cap->chan_width_0,
he_cap->chan_width_1, he_cap->chan_width_2,
he_cap->chan_width_3, he_cap->chan_width_4,
@ -565,15 +596,15 @@ void wma_print_he_cap(tDot11fIEhe_cap *he_cap)
WMA_LOGD("\tLDPC coding support: 0x%01x", he_cap->ldpc_coding);
WMA_LOGD("\tLTF and GI for HE PPDUs: 0x%02x",
he_cap->he_1x_ltf_800_gi_ppdu);
WMA_LOGD("\tMidamble Rx MAX NSTS: 0x%02x",
he_cap->midamble_rx_max_nsts);
WMA_LOGD("\tMidamble Tx Rx MAX NSTS: 0x%02x",
he_cap->midamble_tx_rx_max_nsts);
WMA_LOGD("\tLTF and GI for NDP: 0x%02x", he_cap->he_4x_ltf_3200_gi_ndp);
WMA_LOGD("\tSTBC Tx support <= 80M: 0x%01x", he_cap->tx_stbc_lt_80mhz);
WMA_LOGD("\tSTBC Rx support <= 80M: 0x%01x", he_cap->rx_stbc_lt_80mhz);
WMA_LOGD("\tDoppler support: 0x%02x", he_cap->doppler);
WMA_LOGD("\tUL MU: 0x%02x", he_cap->ul_mu);
WMA_LOGD("\tDCM encoding Tx: 0x%03x", he_cap->dcm_enc_tx);
WMA_LOGD("\tDCM encoding Tx: 0x%03x", he_cap->dcm_enc_rx);
WMA_LOGD("\tDCM encoding Rx: 0x%03x", he_cap->dcm_enc_rx);
WMA_LOGD("\tHE MU PPDU payload support: 0x%01x", he_cap->ul_he_mu);
WMA_LOGD("\tSU Beamformer: 0x%01x", he_cap->su_beamformer);
WMA_LOGD("\tSU Beamformee: 0x%01x", he_cap->su_beamformee);
@ -614,8 +645,22 @@ void wma_print_he_cap(tDot11fIEhe_cap *he_cap)
he_cap->he_ppdu_80_in_160_80p80Mhz);
WMA_LOGD("\ter_1x_he_ltf_gi: 0x%01x",
he_cap->er_1x_he_ltf_gi);
WMA_LOGD("\tmidamble_rx_1x_he_ltf: 0x%01x",
he_cap->midamble_rx_1x_he_ltf);
WMA_LOGD("\tmidamble_tx_rx_1x_he_ltf: 0x%01x",
he_cap->midamble_tx_rx_1x_he_ltf);
WMA_LOGD("\tDCM max BW: 0x%02x",
he_cap->dcm_max_bw);
WMA_LOGD("\tlonger_than_16_he_sigb_ofdm_sym: 0x%01x",
he_cap->longer_than_16_he_sigb_ofdm_sym);
WMA_LOGD("\tnon_trig_cqi_feedback: 0x%01x",
he_cap->non_trig_cqi_feedback);
WMA_LOGD("\ttx_1024_qam_lt_242_tone_ru: 0x%01x",
he_cap->tx_1024_qam_lt_242_tone_ru);
WMA_LOGD("\trx_1024_qam_lt_242_tone_ru: 0x%01x",
he_cap->rx_1024_qam_lt_242_tone_ru);
WMA_LOGD("\trx_full_bw_su_he_mu_compress_sigb: 0x%01x",
he_cap->rx_full_bw_su_he_mu_compress_sigb);
WMA_LOGD("\trx_full_bw_su_he_mu_non_cmpr_sigb: 0x%01x",
he_cap->rx_full_bw_su_he_mu_non_cmpr_sigb);
WMA_LOGD("\tRx MCS MAP for BW <= 80 MHz: 0x%x",
he_cap->rx_he_mcs_map_lt_80);
WMA_LOGD("\tTx MCS MAP for BW <= 80 MHz: 0x%x",
@ -687,8 +732,6 @@ void wma_print_he_phy_cap(uint32_t *phy_cap)
{
WMA_LOGD(FL("HE PHY Capabilities:"));
WMA_LOGD("\tDual band support: 0x%01x",
WMI_HECAP_PHY_DB_GET(phy_cap));
WMA_LOGD("\tChannel width support: 0x%07x",
WMI_HECAP_PHY_CBW_GET(phy_cap));
WMA_LOGD("\tPreamble puncturing Rx: 0x%04x",
@ -705,20 +748,20 @@ void wma_print_he_phy_cap(uint32_t *phy_cap)
WMI_HECAP_PHY_TXSTBC_GET(phy_cap));
WMA_LOGD("\tDoppler support: 0x%02x",
(WMI_HECAP_PHY_RXDOPPLER_GET(phy_cap) << 1) |
WMI_HECAP_PHY_TXDOPPLER_GET(phy_cap));
WMI_HECAP_PHY_TXDOPPLER(phy_cap));
WMA_LOGD("\tUL MU (Full BW): 0x%01x",
WMI_HECAP_PHY_UL_MU_MIMO_GET(phy_cap));
WMA_LOGD("\tUL MU (Partial BW): 0x%01x",
WMI_HECAP_PHY_ULMUMIMOOFDMA_GET(phy_cap));
WMA_LOGD("\tDCM encoding Tx: 0x%03x", WMI_HECAP_PHY_DCMTX_GET(phy_cap));
WMA_LOGD("\tDCM encoding Tx: 0x%03x", WMI_HECAP_PHY_DCMRX_GET(phy_cap));
WMA_LOGD("\tDCM encoding Rx: 0x%03x", WMI_HECAP_PHY_DCMRX_GET(phy_cap));
WMA_LOGD("\tHE MU PPDU payload support: 0x%01x",
WMI_HECAP_PHY_ULHEMU_GET(phy_cap));
WMA_LOGD("\tSU Beamformer: 0x%01x", WMI_HECAP_PHY_SUBFMR_GET(phy_cap));
WMA_LOGD("\tSU Beamformee: 0x%01x", WMI_HECAP_PHY_SUBFME_GET(phy_cap));
WMA_LOGD("\tMU Beamformer: 0x%01x", WMI_HECAP_PHY_MUBFMR_GET(phy_cap));
WMA_LOGD("\tBeamformee STS for <= 80Mhz: 0x%03x",
WMI_HECAP_PHY_SUBFMESTS_GET(phy_cap));
WMI_HECAP_PHY_BFMESTSLT80MHZ_GET(phy_cap));
WMA_LOGD("\tNSTS total for <= 80Mhz: 0x%03x",
WMI_HECAP_PHY_NSTSLT80MHZ_GET(phy_cap));
WMA_LOGD("\tBeamformee STS for > 80Mhz: 0x%03x",
@ -743,7 +786,8 @@ void wma_print_he_phy_cap(uint32_t *phy_cap)
WMI_HECAP_PHY_HEERSU_GET(phy_cap));
WMA_LOGD("\tDL MUMIMO on partial BW: 0x%01x",
WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET(phy_cap));
WMA_LOGD("\tPPET present: 0x%01x", WMI_HECAP_PHY_PADDING_GET(phy_cap));
WMA_LOGD("\tPPET present: 0x%01x",
WMI_HECAP_PHY_PETHRESPRESENT_GET(phy_cap));
WMA_LOGD("\tSRP based SR-support: 0x%01x",
WMI_HECAP_PHY_SRPSPRESENT_GET(phy_cap));
WMA_LOGD("\tPower boost factor: 0x%01x",
@ -759,7 +803,7 @@ void wma_print_he_phy_cap(uint32_t *phy_cap)
WMI_HECAP_PHY_ERSU4X800NSECGI_GET(phy_cap));
}
void wma_print_he_mac_cap(uint32_t mac_cap)
void wma_print_he_mac_cap_w1(uint32_t mac_cap)
{
WMA_LOGD(FL("HE MAC Capabilities:"));
@ -776,14 +820,14 @@ void wma_print_he_mac_cap(uint32_t mac_cap)
WMI_HECAP_MAC_MINFRAGSZ_GET(mac_cap));
WMA_LOGD("\tTrigger MAC pad duration: 0x%02x",
WMI_HECAP_MAC_TRIGPADDUR_GET(mac_cap));
WMA_LOGD("\tMulti-TID aggr support: 0x%03x",
WMI_HECAP_MAC_ACKMTIDAMPDU_GET(mac_cap));
WMA_LOGD("\tMulti-TID aggr Rx support: 0x%03x",
WMI_HECAP_MAC_MTID_RX_GET(mac_cap));
WMA_LOGD("\tLink adaptation: 0x%02x",
WMI_HECAP_MAC_HELKAD_GET(mac_cap));
WMI_HECAP_MAC_HELINK_ADPT_GET(mac_cap));
WMA_LOGD("\tAll ACK support: 0x%01x",
WMI_HECAP_MAC_AACK_GET(mac_cap));
WMA_LOGD("\tUL MU resp. scheduling: 0x%01x",
WMI_HECAP_MAC_ULMURSP_GET(mac_cap));
WMI_HECAP_MAC_TRS_GET(mac_cap));
WMA_LOGD("\tA-Buff status report: 0x%01x",
WMI_HECAP_MAC_BSR_GET(mac_cap));
WMA_LOGD("\tBroadcast TWT support: 0x%01x",
@ -794,8 +838,6 @@ void wma_print_he_mac_cap(uint32_t mac_cap)
WMI_HECAP_MAC_MUCASCADE_GET(mac_cap));
WMA_LOGD("\tACK enabled Multi-TID: 0x%01x",
WMI_HECAP_MAC_ACKMTIDAMPDU_GET(mac_cap));
WMA_LOGD("\tMulti-STA BA in DL MU: 0x%01x",
WMI_HECAP_MAC_GROUPMSTABA_GET(mac_cap));
WMA_LOGD("\tOMI A-Control support: 0x%01x",
WMI_HECAP_MAC_OMI_GET(mac_cap));
WMA_LOGD("\tOFDMA RA support: 0x%01x",
@ -808,17 +850,29 @@ void wma_print_he_mac_cap(uint32_t mac_cap)
WMI_HECAP_MAC_FLEXTWT_GET(mac_cap));
WMA_LOGD("\tRx Ctrl frame to MBSS: 0x%01x",
WMI_HECAP_MAC_MBSS_GET(mac_cap));
}
void wma_print_he_mac_cap_w2(uint32_t mac_cap)
{
WMA_LOGD("\tBSRP A-MPDU Aggregation: 0x%01x",
WMI_HECAP_MAC_BSRPAMPDU_GET(mac_cap));
WMA_LOGD("\tQuite Time Period support: 0x%01x",
WMI_HECAP_MAC_QTP_GET(mac_cap));
WMA_LOGD("\tA-BQR support: 0x%01x", WMI_HECAP_MAC_ABQR_GET(mac_cap));
WMA_LOGD("\tSR Responder support: 0x%01x",
WMI_HECAP_MAC_SRRESP_GET(mac_cap));
WMA_LOGD("\tOPS Support: 0x%01x",
WMI_HECAP_MAC_OPS_GET(mac_cap));
WMI_HECAP_MAC_SRPRESP_GET(mac_cap));
WMA_LOGD("\tNDP Feedback Support: 0x%01x",
WMI_HECAP_MAC_NDPFDBKRPT_GET(mac_cap));
WMA_LOGD("\tOPS Support: 0x%01x",
WMI_HECAP_MAC_OPS_GET(mac_cap));
WMA_LOGD("\tMulti-TID aggr Tx support: 0x%03x",
WMI_HECAP_MAC_MTID_TX_GET(mac_cap));
WMA_LOGD("\tSub Ch selective Tx support: 0x%01x",
WMI_HECAP_MAC_SUBCHANSELTX_GET(mac_cap));
WMA_LOGD("\tUL 2×996 tone RU: 0x%01x",
WMI_HECAP_MAC_UL2X996RU_GET(mac_cap));
WMA_LOGD("\tOM ctrl UL MU data disable Rx: 0x%01x",
WMI_HECAP_MAC_OMCULMUDDIS_GET(mac_cap));
}
void wma_update_target_ext_he_cap(struct target_psoc_info *tgt_hdl,
@ -916,13 +970,13 @@ void wma_he_update_tgt_services(struct wmi_unified *wmi_handle,
void wma_print_he_op(tDot11fIEhe_op *he_ops)
{
WMA_LOGD(FL("bss_color: %0x, default_pe_duration: %0x, twt_required: %0x, rts_threshold: %0x, vht_oper_present: %0x"),
he_ops->bss_color, he_ops->default_pe,
he_ops->twt_required, he_ops->rts_threshold,
he_ops->vht_oper_present);
WMA_LOGD(FL("\tpartial_bss_color: %0x, MBSSID AP: %0x, Tx BSSID Indicator: %0x, BSS color disabled: %0x"),
he_ops->partial_bss_col, he_ops->mbssid_ap,
he_ops->tx_bssid_ind, he_ops->bss_col_disabled);
WMA_LOGD(FL("bss_color %0x def_pe_dur %0x twt_req %0x txop_rts_thre %0x vht_oper %0x"),
he_ops->bss_color, he_ops->default_pe,
he_ops->twt_required, he_ops->txop_rts_threshold,
he_ops->vht_oper_present);
WMA_LOGD(FL("\tpart_bss_color: %0x, MBSSID AP: %0x, BSS color dis %0x"),
he_ops->partial_bss_col, he_ops->co_located_bss,
he_ops->bss_col_disabled);
}
/**
@ -1025,7 +1079,7 @@ void wma_populate_peer_he_cap(struct peer_assoc_params *peer,
tDot11fIEhe_cap *he_cap = &params->he_config;
tDot11fIEhe_op *he_op = &params->he_op;
uint32_t *phy_cap = peer->peer_he_cap_phyinfo;
uint32_t mac_cap = 0, he_ops = 0;
uint32_t mac_cap[PSOC_HOST_MAX_MAC_SIZE] = {0}, he_ops = 0;
uint8_t temp, i, chan_width;
if (params->he_capable)
@ -1034,40 +1088,49 @@ void wma_populate_peer_he_cap(struct peer_assoc_params *peer,
return;
/* HE MAC capabilities */
WMI_HECAP_MAC_HECTRL_SET(mac_cap, he_cap->htc_he);
WMI_HECAP_MAC_TWTREQ_SET(mac_cap, he_cap->twt_request);
WMI_HECAP_MAC_TWTRSP_SET(mac_cap, he_cap->twt_responder);
WMI_HECAP_MAC_HEFRAG_SET(mac_cap, he_cap->fragmentation);
WMI_HECAP_MAC_MAXFRAGMSDU_SET(mac_cap, he_cap->max_num_frag_msdu);
WMI_HECAP_MAC_MINFRAGSZ_SET(mac_cap, he_cap->min_frag_size);
WMI_HECAP_MAC_TRIGPADDUR_SET(mac_cap, he_cap->trigger_frm_mac_pad);
WMI_HECAP_MAC_ACKMTIDAMPDU_SET(mac_cap, he_cap->multi_tid_aggr);
WMI_HECAP_MAC_HELKAD_SET(mac_cap, he_cap->he_link_adaptation);
WMI_HECAP_MAC_AACK_SET(mac_cap, he_cap->all_ack);
WMI_HECAP_MAC_ULMURSP_SET(mac_cap, he_cap->ul_mu_rsp_sched);
WMI_HECAP_MAC_BSR_SET(mac_cap, he_cap->a_bsr);
WMI_HECAP_MAC_BCSTTWT_SET(mac_cap, he_cap->broadcast_twt);
WMI_HECAP_MAC_32BITBA_SET(mac_cap, he_cap->ba_32bit_bitmap);
WMI_HECAP_MAC_MUCASCADE_SET(mac_cap, he_cap->mu_cascade);
WMI_HECAP_MAC_ACKMTIDAMPDU_SET(mac_cap, he_cap->ack_enabled_multitid);
WMI_HECAP_MAC_GROUPMSTABA_SET(mac_cap, he_cap->dl_mu_ba);
WMI_HECAP_MAC_OMI_SET(mac_cap, he_cap->omi_a_ctrl);
WMI_HECAP_MAC_OFDMARA_SET(mac_cap, he_cap->ofdma_ra);
WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET(mac_cap, he_cap->max_ampdu_len);
WMI_HECAP_MAC_AMSDUFRAG_SET(mac_cap, he_cap->amsdu_frag);
WMI_HECAP_MAC_FLEXTWT_SET(mac_cap, he_cap->flex_twt_sched);
WMI_HECAP_MAC_MBSS_SET(mac_cap, he_cap->rx_ctrl_frame);
WMI_HECAP_MAC_BSRPAMPDU_SET(mac_cap, he_cap->bsrp_ampdu_aggr);
WMI_HECAP_MAC_QTP_SET(mac_cap, he_cap->qtp);
WMI_HECAP_MAC_ABQR_SET(mac_cap, he_cap->a_bqr);
WMI_HECAP_MAC_SRRESP_SET(mac_cap, he_cap->sr_responder);
WMI_HECAP_MAC_OPS_SET(mac_cap, he_cap->ops_supp);
WMI_HECAP_MAC_NDPFDBKRPT_SET(mac_cap, he_cap->ndp_feedback_supp);
WMI_HECAP_MAC_AMSDUINAMPDU_SET(mac_cap, he_cap->amsdu_in_ampdu);
peer->peer_he_cap_macinfo = mac_cap;
WMI_HECAP_MAC_HECTRL_SET(mac_cap[0], he_cap->htc_he);
WMI_HECAP_MAC_TWTREQ_SET(mac_cap[0], he_cap->twt_request);
WMI_HECAP_MAC_TWTRSP_SET(mac_cap[0], he_cap->twt_responder);
WMI_HECAP_MAC_HEFRAG_SET(mac_cap[0], he_cap->fragmentation);
WMI_HECAP_MAC_MAXFRAGMSDU_SET(mac_cap[0],
he_cap->max_num_frag_msdu_amsdu_exp);
WMI_HECAP_MAC_MINFRAGSZ_SET(mac_cap[0], he_cap->min_frag_size);
WMI_HECAP_MAC_TRIGPADDUR_SET(mac_cap[0], he_cap->trigger_frm_mac_pad);
WMI_HECAP_MAC_ACKMTIDAMPDU_SET(mac_cap[0],
he_cap->multi_tid_aggr_rx_supp);
WMI_HECAP_MAC_HELKAD_SET(mac_cap[0], he_cap->he_link_adaptation);
WMI_HECAP_MAC_AACK_SET(mac_cap[0], he_cap->all_ack);
WMI_HECAP_MAC_TRS_SET(mac_cap[0], he_cap->trigd_rsp_sched);
WMI_HECAP_MAC_BSR_SET(mac_cap[0], he_cap->a_bsr);
WMI_HECAP_MAC_BCSTTWT_SET(mac_cap[0], he_cap->broadcast_twt);
WMI_HECAP_MAC_32BITBA_SET(mac_cap[0], he_cap->ba_32bit_bitmap);
WMI_HECAP_MAC_MUCASCADE_SET(mac_cap[0], he_cap->mu_cascade);
WMI_HECAP_MAC_ACKMTIDAMPDU_SET(mac_cap[0],
he_cap->ack_enabled_multitid);
WMI_HECAP_MAC_OMI_SET(mac_cap[0], he_cap->omi_a_ctrl);
WMI_HECAP_MAC_OFDMARA_SET(mac_cap[0], he_cap->ofdma_ra);
WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET(mac_cap[0],
he_cap->max_ampdu_len_exp_ext);
WMI_HECAP_MAC_AMSDUFRAG_SET(mac_cap[0], he_cap->amsdu_frag);
WMI_HECAP_MAC_FLEXTWT_SET(mac_cap[0], he_cap->flex_twt_sched);
WMI_HECAP_MAC_MBSS_SET(mac_cap[0], he_cap->rx_ctrl_frame);
WMI_HECAP_MAC_BSRPAMPDU_SET(mac_cap[1], he_cap->bsrp_ampdu_aggr);
WMI_HECAP_MAC_QTP_SET(mac_cap[1], he_cap->qtp);
WMI_HECAP_MAC_ABQR_SET(mac_cap[1], he_cap->a_bqr);
WMI_HECAP_MAC_SRPRESP_SET(mac_cap[1],
he_cap->spatial_reuse_param_rspder);
WMI_HECAP_MAC_OPS_SET(mac_cap[1], he_cap->ops_supp);
WMI_HECAP_MAC_NDPFDBKRPT_SET(mac_cap[1], he_cap->ndp_feedback_supp);
WMI_HECAP_MAC_AMSDUINAMPDU_SET(mac_cap[1], he_cap->amsdu_in_ampdu);
WMI_HECAP_MAC_MTID_TX_SET(mac_cap[1], he_cap->multi_tid_aggr_tx_supp);
WMI_HECAP_MAC_SUBCHANSELTX_SET(mac_cap[1],
he_cap->he_sub_ch_sel_tx_supp);
WMI_HECAP_MAC_UL2X996RU_SET(mac_cap[1], he_cap->ul_2x996_tone_ru_supp);
WMI_HECAP_MAC_OMCULMUDDIS_SET(mac_cap[1],
he_cap->om_ctrl_ul_mu_data_dis_rx);
qdf_mem_copy(peer->peer_he_cap_macinfo, mac_cap, sizeof(mac_cap));
/* HE PHY capabilities */
WMI_HECAP_PHY_DB_SET(phy_cap, he_cap->dual_band);
chan_width = HE_CH_WIDTH_COMBINE(he_cap->chan_width_0,
he_cap->chan_width_1, he_cap->chan_width_2,
he_cap->chan_width_3, he_cap->chan_width_4,
@ -1077,8 +1140,8 @@ void wma_populate_peer_he_cap(struct peer_assoc_params *peer,
WMI_HECAP_PHY_COD_SET(phy_cap, he_cap->device_class);
WMI_HECAP_PHY_LDPC_SET(phy_cap, he_cap->ldpc_coding);
WMI_HECAP_PHY_LTFGIFORHE_SET(phy_cap, he_cap->he_1x_ltf_800_gi_ppdu);
WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_SET(phy_cap,
he_cap->midamble_rx_max_nsts);
WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_SET(phy_cap,
he_cap->midamble_tx_rx_max_nsts);
WMI_HECAP_PHY_LTFGIFORNDP_SET(phy_cap, he_cap->he_4x_ltf_3200_gi_ndp);
WMI_HECAP_PHY_RXSTBC_SET(phy_cap, he_cap->rx_stbc_lt_80mhz);
@ -1132,8 +1195,25 @@ void wma_populate_peer_he_cap(struct peer_assoc_params *peer,
WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET(phy_cap,
he_cap->he_ppdu_80_in_160_80p80Mhz);
WMI_HECAP_PHY_ERSU1X800NSECGI_SET(phy_cap, he_cap->er_1x_he_ltf_gi);
WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_SET(phy_cap,
he_cap->midamble_rx_1x_he_ltf);
WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_SET(phy_cap,
he_cap->
midamble_tx_rx_1x_he_ltf);
WMI_HECAP_PHY_DCMMAXBW_SET(phy_cap, he_cap->dcm_max_bw);
WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_SET(phy_cap,
he_cap->
longer_than_16_he_sigb_ofdm_sym);
WMI_HECAP_PHY_NONTRIGCQIFEEDBK_SET(phy_cap,
he_cap->non_trig_cqi_feedback);
WMI_HECAP_PHY_TX1024QAM242RUSUPRT_SET(phy_cap,
he_cap->
tx_1024_qam_lt_242_tone_ru);
WMI_HECAP_PHY_RX1024QAM242RUSUPRT_SET(phy_cap,
he_cap->
rx_1024_qam_lt_242_tone_ru);
WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_SET(phy_cap,
he_cap->rx_full_bw_su_he_mu_compress_sigb);
WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_SET(phy_cap,
he_cap->rx_full_bw_su_he_mu_non_cmpr_sigb);
/* as per 11ax draft 1.4 */
peer->peer_he_mcs_count = 1;
@ -1162,9 +1242,8 @@ void wma_populate_peer_he_cap(struct peer_assoc_params *peer,
WMI_HEOPS_COLOR_SET(he_ops, he_op->bss_color);
WMI_HEOPS_DEFPE_SET(he_ops, he_op->default_pe);
WMI_HEOPS_TWT_SET(he_ops, he_op->twt_required);
WMI_HEOPS_RTSTHLD_SET(he_ops, he_op->rts_threshold);
WMI_HEOPS_RTSTHLD_SET(he_ops, he_op->txop_rts_threshold);
WMI_HEOPS_PARTBSSCOLOR_SET(he_ops, he_op->partial_bss_col);
WMI_HEOPS_TXBSSID_SET(he_ops, he_op->tx_bssid_ind);
WMI_HEOPS_BSSCOLORDISABLE_SET(he_ops, he_op->bss_col_disabled);
peer->peer_he_ops = he_ops;
@ -1173,7 +1252,8 @@ void wma_populate_peer_he_cap(struct peer_assoc_params *peer,
wma_print_he_cap(he_cap);
WMA_LOGD(FL("Peer HE Capabilities:"));
wma_print_he_phy_cap(phy_cap);
wma_print_he_mac_cap(mac_cap);
wma_print_he_mac_cap_w1(mac_cap[0]);
wma_print_he_mac_cap_w2(mac_cap[1]);
wma_print_he_ppet(&peer->peer_ppet);
return;
@ -1190,9 +1270,8 @@ void wma_update_vdev_he_ops(struct wma_vdev_start_req *req,
WMI_HEOPS_COLOR_SET(he_ops, he_op->bss_color);
WMI_HEOPS_DEFPE_SET(he_ops, he_op->default_pe);
WMI_HEOPS_TWT_SET(he_ops, he_op->twt_required);
WMI_HEOPS_RTSTHLD_SET(he_ops, he_op->rts_threshold);
WMI_HEOPS_RTSTHLD_SET(he_ops, he_op->txop_rts_threshold);
WMI_HEOPS_PARTBSSCOLOR_SET(he_ops, he_op->partial_bss_col);
WMI_HEOPS_TXBSSID_SET(he_ops, he_op->tx_bssid_ind);
WMI_HEOPS_BSSCOLORDISABLE_SET(he_ops, he_op->bss_col_disabled);
req->he_ops = he_ops;
@ -1267,9 +1346,8 @@ QDF_STATUS wma_update_he_ops_ie(tp_wma_handle wma, uint8_t vdev_id,
WMI_HEOPS_COLOR_SET(dword_he_op, he_op->bss_color);
WMI_HEOPS_DEFPE_SET(dword_he_op, he_op->default_pe);
WMI_HEOPS_TWT_SET(dword_he_op, he_op->twt_required);
WMI_HEOPS_RTSTHLD_SET(dword_he_op, he_op->rts_threshold);
WMI_HEOPS_RTSTHLD_SET(dword_he_op, he_op->txop_rts_threshold);
WMI_HEOPS_PARTBSSCOLOR_SET(dword_he_op, he_op->partial_bss_col);
WMI_HEOPS_TXBSSID_SET(dword_he_op, he_op->tx_bssid_ind);
WMI_HEOPS_BSSCOLORDISABLE_SET(dword_he_op, he_op->bss_col_disabled);
WMA_LOGD("vdev_id: %d HE_OPs: 0x%x", vdev_id, dword_he_op);

31
core/wma/src/wma_main.c
View file

@ -6097,8 +6097,10 @@ QDF_STATUS wma_get_caps_for_phyidx_hwmode(struct wma_caps_per_phy *caps_per_phy,
caps_per_phy->vht_2g = vht_cap_info;
caps_per_phy->vht_5g = vht_cap_info;
/* legacy platform doesn't support HE IE */
caps_per_phy->he_2g = 0;
caps_per_phy->he_5g = 0;
caps_per_phy->he_2g[0] = 0;
caps_per_phy->he_2g[1] = 0;
caps_per_phy->he_5g[0] = 0;
caps_per_phy->he_5g[1] = 0;
return QDF_STATUS_SUCCESS;
}
@ -6121,8 +6123,10 @@ QDF_STATUS wma_get_caps_for_phyidx_hwmode(struct wma_caps_per_phy *caps_per_phy,
caps_per_phy->ht_5g = mac_phy_cap[phyid].ht_cap_info_5G;
caps_per_phy->vht_2g = mac_phy_cap[phyid].vht_cap_info_2G;
caps_per_phy->vht_5g = mac_phy_cap[phyid].vht_cap_info_5G;
caps_per_phy->he_2g = mac_phy_cap[phyid].he_cap_info_2G;
caps_per_phy->he_5g = mac_phy_cap[phyid].he_cap_info_5G;
qdf_mem_copy(caps_per_phy->he_2g, mac_phy_cap[phyid].he_cap_info_2G,
sizeof(caps_per_phy->he_2g));
qdf_mem_copy(caps_per_phy->he_5g, mac_phy_cap[phyid].he_cap_info_5G,
sizeof(caps_per_phy->he_5g));
caps_per_phy->tx_chain_mask_2G = mac_phy_cap->tx_chain_mask_2G;
caps_per_phy->rx_chain_mask_2G = mac_phy_cap->rx_chain_mask_2G;
@ -6200,7 +6204,8 @@ bool wma_is_rx_ldpc_supported_for_channel(uint32_t channel)
static void wma_print_mac_phy_capabilities(struct wlan_psoc_host_mac_phy_caps
*cap, int index)
{
uint32_t mac_2G, mac_5G;
uint32_t mac_2G[PSOC_HOST_MAX_MAC_SIZE];
uint32_t mac_5G[PSOC_HOST_MAX_MAC_SIZE];
uint32_t phy_2G[WMI_MAX_HECAP_PHY_SIZE];
uint32_t phy_5G[WMI_MAX_HECAP_PHY_SIZE];
struct wlan_psoc_host_ppe_threshold ppet_2G, ppet_5G;
@ -6229,12 +6234,14 @@ static void wma_print_mac_phy_capabilities(struct wlan_psoc_host_mac_phy_caps
WMA_LOGD("\t: vht_supp_mcs_5G[%d]", cap->vht_supp_mcs_5G);
WMA_LOGD("\t: tx_chain_mask_5G[%d]", cap->tx_chain_mask_5G);
WMA_LOGD("\t: rx_chain_mask_5G[%d]", cap->rx_chain_mask_5G);
WMA_LOGD("\t: he_cap_info_2G[%08x]", cap->he_cap_info_2G);
WMA_LOGD("\t: he_cap_info_2G[0][%08x]", cap->he_cap_info_2G[0]);
WMA_LOGD("\t: he_cap_info_2G[1][%08x]", cap->he_cap_info_2G[1]);
WMA_LOGD("\t: he_supp_mcs_2G[%08x]", cap->he_supp_mcs_2G);
WMA_LOGD("\t: he_cap_info_5G[%08x]", cap->he_cap_info_5G);
WMA_LOGD("\t: he_cap_info_5G[0][%08x]", cap->he_cap_info_5G[0]);
WMA_LOGD("\t: he_cap_info_5G[1][%08x]", cap->he_cap_info_5G[1]);
WMA_LOGD("\t: he_supp_mcs_5G[%08x]", cap->he_supp_mcs_5G);
mac_2G = cap->he_cap_info_2G;
mac_5G = cap->he_cap_info_5G;
qdf_mem_copy(mac_2G, cap->he_cap_info_2G, sizeof(mac_2G));
qdf_mem_copy(mac_5G, cap->he_cap_info_5G, sizeof(mac_5G));
qdf_mem_copy(phy_2G, cap->he_cap_phy_info_2G,
WMI_MAX_HECAP_PHY_SIZE * 4);
qdf_mem_copy(phy_5G, cap->he_cap_phy_info_5G,
@ -6242,10 +6249,12 @@ static void wma_print_mac_phy_capabilities(struct wlan_psoc_host_mac_phy_caps
ppet_2G = cap->he_ppet2G;
ppet_5G = cap->he_ppet5G;
wma_print_he_mac_cap(mac_2G);
wma_print_he_mac_cap_w1(mac_2G[0]);
wma_print_he_mac_cap_w2(mac_2G[1]);
wma_print_he_phy_cap(phy_2G);
wma_print_he_ppet(&ppet_2G);
wma_print_he_mac_cap(mac_5G);
wma_print_he_mac_cap_w1(mac_5G[0]);
wma_print_he_mac_cap_w1(mac_5G[1]);
wma_print_he_phy_cap(phy_5G);
wma_print_he_ppet(&ppet_5G);
}