diff --git a/drivers/clk/qcom/dispcc-monaco.c b/drivers/clk/qcom/dispcc-monaco.c
index 6f8f3f0c7383..64a3fb1faead 100644
--- a/drivers/clk/qcom/dispcc-monaco.c
+++ b/drivers/clk/qcom/dispcc-monaco.c
@@ -254,7 +254,6 @@ static struct clk_rcg2 disp_cc_sleep_clk_src = {
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_4,
 	.freq_tbl = ftbl_disp_cc_sleep_clk_src,
-	.enable_safe_config = true,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_sleep_clk_src",
 		.parent_data = disp_cc_parent_data_4,
diff --git a/drivers/clk/qcom/gpucc-monaco.c b/drivers/clk/qcom/gpucc-monaco.c
index c2df50d774a9..9adf0895e93d 100644
--- a/drivers/clk/qcom/gpucc-monaco.c
+++ b/drivers/clk/qcom/gpucc-monaco.c
@@ -311,7 +311,7 @@ static struct clk_branch gpu_cc_cxo_aon_clk = {
 
 static struct clk_branch gpu_cc_cxo_clk = {
 	.halt_reg = 0x418c,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x418c,
 		.enable_mask = BIT(0),
@@ -329,7 +329,7 @@ static struct clk_branch gpu_cc_cxo_clk = {
 
 static struct clk_branch gpu_cc_gx_cxo_clk = {
 	.halt_reg = 0x416c,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x416c,
 		.enable_mask = BIT(0),