From 1fdcce591e97b9ff7bc5e2ce09cbc706b7c5cfd2 Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Mon, 31 May 2021 16:15:45 +0530 Subject: [PATCH] clk: qcom: Update the clk structure parameters for GPUCC/DISPCC clks Update the halt check for gpu clocks and remove the enable_safe_config for dispcc for MONACO. Change-Id: I97f6a1b7b5d7f8aef862455f0bbf23f9b8612d79 Signed-off-by: Saurabh Sahu --- drivers/clk/qcom/dispcc-monaco.c | 1 - drivers/clk/qcom/gpucc-monaco.c | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/dispcc-monaco.c b/drivers/clk/qcom/dispcc-monaco.c index 6f8f3f0c7383..64a3fb1faead 100644 --- a/drivers/clk/qcom/dispcc-monaco.c +++ b/drivers/clk/qcom/dispcc-monaco.c @@ -254,7 +254,6 @@ static struct clk_rcg2 disp_cc_sleep_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_4, .freq_tbl = ftbl_disp_cc_sleep_clk_src, - .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_sleep_clk_src", .parent_data = disp_cc_parent_data_4, diff --git a/drivers/clk/qcom/gpucc-monaco.c b/drivers/clk/qcom/gpucc-monaco.c index c2df50d774a9..9adf0895e93d 100644 --- a/drivers/clk/qcom/gpucc-monaco.c +++ b/drivers/clk/qcom/gpucc-monaco.c @@ -311,7 +311,7 @@ static struct clk_branch gpu_cc_cxo_aon_clk = { static struct clk_branch gpu_cc_cxo_clk = { .halt_reg = 0x418c, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x418c, .enable_mask = BIT(0), @@ -329,7 +329,7 @@ static struct clk_branch gpu_cc_cxo_clk = { static struct clk_branch gpu_cc_gx_cxo_clk = { .halt_reg = 0x416c, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x416c, .enable_mask = BIT(0),