From 2012eebff1317fc2f57730a35304db467774e6fb Mon Sep 17 00:00:00 2001 From: Amir Vajid Date: Wed, 22 Jul 2020 22:03:04 -0700 Subject: [PATCH] ARM: dts: msm: Add cpu7 L3 latfloor device on Lahaina Create an L3 latfloor device for L3 voting of compute workloads running on cpu7. Change-Id: I0935ad9b4fce221cf00d297ce1a4130160a67ae1 --- qcom/lahaina-v2.dtsi | 6 ++++++ qcom/lahaina.dtsi | 18 ++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/qcom/lahaina-v2.dtsi b/qcom/lahaina-v2.dtsi index f78b79f08a35..7f9632dab8ff 100644 --- a/qcom/lahaina-v2.dtsi +++ b/qcom/lahaina-v2.dtsi @@ -158,6 +158,12 @@ < 2814600 1593600000 >; }; +&cpu7_l3_computemon { + qcom,core-dev-table = + < 2726400 300000000 >, + < 2814600 1593600000 >; +}; + &cpu0_cpu_llcc_latmon { qcom,core-dev-table = < 300000 MHZ_TO_MBPS( 150, 16) >, diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 2525552dd229..f50b2eef1211 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -3744,6 +3744,16 @@ &epss_l3_cpu SLAVE_EPSS_L3_CPU7>; }; + cpu7_cpu_l3_latfloor: qcom,cpu7-cpu-l3-latfloor { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "compute"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_SHARED>; + }; + snoop_l3_bw: qcom,snoop-l3-bw { compatible = "qcom,devfreq-icc-l3bw"; reg = <0x18590100 0xa0>; @@ -3964,6 +3974,14 @@ qcom,core-dev-table = <&cpu4_cpu_l3_tbl>; }; + cpu7_l3_computemon: qcom,cpu7-l3-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu7_cpu_l3_latfloor>; + qcom,core-dev-table = + < 2304000 300000000 >, + < 2400000 1516800000 >; + }; + cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;