From 2b91009d30192e515be09d85ae2abed0247394dc Mon Sep 17 00:00:00 2001
From: Gaurav Singhal <gsinghal@qti.qualcomm.com>
Date: Sat, 29 Feb 2020 10:32:23 +0530
Subject: [PATCH] ARM: dts: msm: Add NFC I3C device node for Lahaina

Device node changes required on lahaina describing
the GPIO configuration for NFC I3C controller chip.

Modified corresponding NFC device node for
MTP, CDP and QRD platforms.

Change-Id: I93ffc68c70dc0a1a06a1c36c63531be8f0802ffb
---
 qcom/lahaina-cdp.dtsi     | 20 +++++++++
 qcom/lahaina-mtp.dtsi     | 20 +++++++++
 qcom/lahaina-pinctrl.dtsi | 86 +++++++++++++++++++++++++++++++++++++++
 qcom/lahaina-qrd.dtsi     | 20 +++++++++
 4 files changed, 146 insertions(+)

diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi
index 7290b1eaf842..b1f0643275df 100644
--- a/qcom/lahaina-cdp.dtsi
+++ b/qcom/lahaina-cdp.dtsi
@@ -76,6 +76,26 @@
 	};
 };
 
+&i3c3 {
+	se-clock-frequency = <19200000>;
+	i3c-scl-hz = <3500000>;
+	i2c-scl-hz = <400000>;
+	status = "ok";
+
+	sn@0,23600000000 {
+		compatible = "qcom,sn-nci-i3c";
+		reg = <0x0 0x236 0x00000000>;
+		qcom,sn-ven = <&tlmm 62 0x00>;
+		qcom,sn-firm = <&tlmm 86 0x00>;
+		qcom,sn-clkreq = <&tlmm 63 0x00>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&nfc_enable_active &nfc_fwdl_active
+					&nfc_clk_req_active>;
+		pinctrl-1 = <&nfc_enable_suspend &nfc_fwdl_suspend
+					&nfc_clk_req_suspend>;
+	};
+};
+
 &sdhc_2 {
 	vdd-supply = <&pm8350c_l9>;
 	qcom,vdd-voltage-level = <2950000 2960000>;
diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi
index f6b90a75e644..6e6de5592879 100644
--- a/qcom/lahaina-mtp.dtsi
+++ b/qcom/lahaina-mtp.dtsi
@@ -78,6 +78,26 @@
 	};
 };
 
+&i3c3 {
+	se-clock-frequency = <19200000>;
+	i3c-scl-hz = <3500000>;
+	i2c-scl-hz = <400000>;
+	status = "ok";
+
+	sn@0,23600000000 {
+		compatible = "qcom,sn-nci-i3c";
+		reg = <0x0 0x236 0x00000000>;
+		qcom,sn-ven = <&tlmm 62 0x00>;
+		qcom,sn-firm = <&tlmm 86 0x00>;
+		qcom,sn-clkreq = <&tlmm 63 0x00>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&nfc_enable_active &nfc_fwdl_active
+					&nfc_clk_req_active>;
+		pinctrl-1 = <&nfc_enable_suspend &nfc_fwdl_suspend
+					&nfc_clk_req_suspend>;
+	};
+};
+
 &sdhc_2 {
 	vdd-supply = <&pm8350c_l9>;
 	qcom,vdd-voltage-level = <2950000 2960000>;
diff --git a/qcom/lahaina-pinctrl.dtsi b/qcom/lahaina-pinctrl.dtsi
index be8c8f34c49a..79a988b94519 100644
--- a/qcom/lahaina-pinctrl.dtsi
+++ b/qcom/lahaina-pinctrl.dtsi
@@ -389,6 +389,92 @@
 		};
 	};
 
+	nfc {
+			nfc_enable_active: nfc_enable_active {
+				mux {
+					pins = "gpio62";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio62";
+					drive-strength = <2>; /* 2 MA */
+					bias-pull-up;
+				};
+			};
+
+			nfc_enable_suspend: nfc_enable_suspend {
+				mux {
+					pins = "gpio62";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio62";
+					drive-strength = <2>; /* 2 MA */
+					bias-disable;
+				};
+			};
+
+			nfc_fwdl_active: nfc_fwdl_active {
+				mux {
+					/* 86: Firmware */
+					pins = "gpio86";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio86";
+					drive-strength = <2>; /* 2 MA */
+					bias-disable;
+				};
+			};
+
+			nfc_fwdl_suspend: nfc_fwdl_suspend {
+				mux {
+					/*86: Firmware */
+					pins = "gpio86";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio86";
+					drive-strength = <2>; /* 2 MA */
+					bias-disable;
+				};
+			};
+
+			nfc_clk_req_active: nfc_clk_req_active {
+				/* active state */
+				mux {
+					/* GPIO 63: NFC CLOCK REQUEST */
+					pins = "gpio63";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio63";
+					drive-strength = <2>; /* 2 MA */
+					bias-pull-up;
+				};
+			};
+
+			nfc_clk_req_suspend: nfc_clk_req_suspend {
+				/* sleep state */
+				mux {
+					/* GPIO 63: NFC CLOCK REQUEST */
+					pins = "gpio63";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio63";
+					drive-strength = <2>; /* 2 MA */
+					bias-disable;
+				};
+			};
+	};
+
 	/* SPI */
 	qupv3_se0_spi_pins: qupv3_se0_spi_pins {
 		qupv3_se0_spi_active: qupv3_se0_spi_active {
diff --git a/qcom/lahaina-qrd.dtsi b/qcom/lahaina-qrd.dtsi
index f43b2b3e285b..7206b47aaafd 100644
--- a/qcom/lahaina-qrd.dtsi
+++ b/qcom/lahaina-qrd.dtsi
@@ -157,6 +157,26 @@
 	};
 };
 
+&i3c3 {
+	se-clock-frequency = <19200000>;
+	i3c-scl-hz = <3500000>;
+	i2c-scl-hz = <400000>;
+	status = "ok";
+
+	sn@0,23600000000 {
+		compatible = "qcom,sn-nci-i3c";
+		reg = <0x0 0x236 0x00000000>;
+		qcom,sn-ven = <&tlmm 62 0x00>;
+		qcom,sn-firm = <&tlmm 86 0x00>;
+		qcom,sn-clkreq = <&tlmm 63 0x00>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&nfc_enable_active &nfc_fwdl_active
+					&nfc_clk_req_active>;
+		pinctrl-1 = <&nfc_enable_suspend &nfc_fwdl_suspend
+					&nfc_clk_req_suspend>;
+	};
+};
+
 &dai_mi2s2 {
 	qcom,msm-mi2s-tx-lines = <1>;
 	pinctrl-names = "default", "sleep";