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ARM: dts: msm: Add monaco video dtsi in target dtsi

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Add monaco video dtsi to enable the video device.

Change-Id: I7f6f9583b12bbd379dbaa5de06da47804d5519a0
This commit is contained in:
Sachin Kumar Garg 2021-04-07 12:06:41 +05:30 • committed by Gerrit - the friendly Code Review server
commit 2075d459fb
1 changed files with 110 additions and 0 deletions
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qcom/monaco-vidc.dtsi Normal file
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#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/msm/msm-bus-ids.h>
&soc {
msm_vidc: qcom,vidc@5a00000 {
compatible = "qcom,msm-vidc", "qcom,monaco-vidc";
status = "ok"
reg = <0x5a00000 0x200000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
/* Supply */
venus-supply = <&gcc_venus_gdsc>;
venus-core0-supply = <&gcc_vcodec0_gdsc>;
/* Clocks */
clock-names = "core_clk", "iface_clk", "bus_clk",
"core0_clk", "core0_bus_clk", "throttle_clk";
clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
<&gcc GCC_VIDEO_AHB_CLK>,
<&gcc GCC_VENUS_CTL_AXI_CLK>,
<&gcc GCC_VIDEO_VCODEC0_SYS_CLK>,
<&gcc GCC_VCODEC0_AXI_CLK>,
<&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk",
"core0_clk", "core0_bus_clk", "throttle_clk";
qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0 0x0>;
qcom,allowed-clock-rates = <133330000 240000000>;
/* Buses */
bus_cnoc {
compatible = "qcom,msm-vidc,bus";
label = "cnoc";
qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
qcom,mode = "performance";
qcom,bus-range-kbps = <1000 1000>;
};
venus_bus_ddr {
compatible = "qcom,msm-vidc,bus";
label = "venus-ddr";
qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
qcom,mode = "vidc-ar50-ddr";
qcom,bus-range-kbps = <1000 2128000>;
};
arm9_bus_ddr {
compatible = "qcom,msm-vidc,bus";
label = "venus-arm9-ddr";
qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
qcom,mode = "performance";
qcom,bus-range-kbps = <1000 1000>;
};
/* MMUs */
non_secure_cb {
compatible = "qcom,msm-vidc,context-bank";
label = "venus_ns";
iommus =
<&apps_smmu 0x860 0x00>,
<&apps_smmu 0x880 0x00>;
qcom,iommu-dma-addr-pool = <0x70800000 0x6f800000>;
qcom,iommu-faults = "non-fatal";
buffer-types = <0xfff>;
virtual-addr-pool = <0x70800000 0x6f800000>;
};
secure_bitstream_cb {
compatible = "qcom,msm-vidc,context-bank";
label = "venus_sec_bitstream";
iommus =
<&apps_smmu 0x861 0x04>;
qcom,iommu-dma-addr-pool = <0x4b000000 0x25800000>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
buffer-types = <0x241>;
virtual-addr-pool = <0x4b000000 0x25800000>;
qcom,secure-context-bank;
};
secure_pixel_cb {
compatible = "qcom,msm-vidc,context-bank";
label = "venus_sec_pixel";
iommus =
<&apps_smmu 0x863 0x0>;
qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
buffer-types = <0x106>;
virtual-addr-pool = <0x25800000 0x25800000>;
qcom,secure-context-bank;
};
secure_non_pixel_cb {
compatible = "qcom,msm-vidc,context-bank";
label = "venus_sec_non_pixel";
iommus =
<&apps_smmu 0x804 0xE0>;
qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
buffer-types = <0x480>;
virtual-addr-pool = <0x1000000 0x24800000>;
qcom,secure-context-bank;
};
};
};